|
AMC13
Firmwares for the different applications of the AMC13 uTCA board made at Boston University
|
|
AMC13
Firmwares for the different applications of the AMC13 uTCA board made at Boston University
|
This is the complete list of members for DaqLSCXG10G, including all inherited members.
| ack_pckt (defined in Core_logic) | Core_logic | Port |
| ack_pckt (defined in build_pckt_s_XGMII) | build_pckt_s_XGMII | Port |
| aclr (defined in FIFO_sync) | FIFO_sync | Port |
| Addr (defined in SLINK_opt_XGMII) | SLINK_opt_XGMII | Port |
| addr (defined in fed_itf) | fed_itf | Port |
| addra (defined in Memory) | Memory | Port |
| addrb (defined in Memory) | Memory | Port |
| almost_f (defined in FIFO_sync) | FIFO_sync | Port |
| amc13_pack (defined in DaqLSCXG10G) | DaqLSCXG10G | use clause |
| Back_p (defined in event_generator) | event_generator | Port |
| base_clk (defined in freq_measure) | freq_measure | Port |
| block_free (defined in fed_itf) | fed_itf | Port |
| block_free (defined in Core_logic) | Core_logic | Port |
| block_sz_fed (defined in fed_itf) | fed_itf | Port |
| block_sz_fed (defined in Core_logic) | Core_logic | Port |
| BLOCKSYNC_OUT (defined in BLOCK_SYNC_SM) | BLOCK_SYNC_SM | Port |
| card_ID (defined in Core_logic) | Core_logic | Port |
| card_ID (defined in build_pckt_s_XGMII) | build_pckt_s_XGMII | Port |
| card_ID (defined in rcv_pckt_s_XGMII) | rcv_pckt_s_XGMII | Port |
| card_ID_rcv (defined in Core_logic) | Core_logic | Port |
| clear (defined in CRC_SLINKx) | CRC_SLINKx | Port |
| clk (defined in lpm_fifo) | lpm_fifo | Port |
| clk (defined in CRC_SLINKx) | CRC_SLINKx | Port |
| clk (defined in XGbEPCS32) | XGbEPCS32 | Port |
| clk156 (defined in XGMII_serdes_wapper) | XGMII_serdes_wapper | Port |
| clk2x (defined in XGbEPCS32) | XGbEPCS32 | Port |
| clk_r (defined in FIFO_sync) | FIFO_sync | Port |
| clk_w (defined in FIFO_sync) | FIFO_sync | Port |
| clka (defined in Memory) | Memory | Port |
| clkb (defined in Memory) | Memory | Port |
| clock (defined in SLINK_opt_XGMII) | SLINK_opt_XGMII | Port |
| clock_r (defined in SLINK_opt_XGMII) | SLINK_opt_XGMII | Port |
| clock_t (defined in rcv_pckt_s_XGMII) | rcv_pckt_s_XGMII | Port |
| clocki (defined in resync) | resync | Port |
| clocki (defined in resync) | resync | Port |
| clocki (defined in resync) | resync | Port |
| clocki (defined in resync) | resync | Port |
| clocko (defined in resync) | resync | Port |
| clocko (defined in resync) | resync | Port |
| clocko (defined in resync) | resync | Port |
| clocko (defined in resync) | resync | Port |
| cmd (defined in Core_logic) | Core_logic | Port |
| cmd (defined in build_pckt_s_XGMII) | build_pckt_s_XGMII | Port |
| cmd (defined in rcv_pckt_s_XGMII) | rcv_pckt_s_XGMII | Port |
| cmd_rcv (defined in Core_logic) | Core_logic | Port |
| cnt_evt (defined in fed_itf) | fed_itf | Port |
| cnt_pckt_rcv (defined in fed_itf) | fed_itf | Port |
| cnt_pckt_rcv (defined in rcv_pckt_s_XGMII) | rcv_pckt_s_XGMII | Port |
| cnt_pckt_snd (defined in fed_itf) | fed_itf | Port |
| cnt_pckt_snd (defined in build_pckt_s_XGMII) | build_pckt_s_XGMII | Port |
| CPLL_RESET (defined in SFP3_v2_7_TX_STARTUP_FSM) | SFP3_v2_7_TX_STARTUP_FSM | Port |
| CPLL_RESET (defined in SFP3_v2_7_RX_STARTUP_FSM) | SFP3_v2_7_RX_STARTUP_FSM | Port |
| CPLLLOCK (defined in SFP3_v2_7_TX_STARTUP_FSM) | SFP3_v2_7_TX_STARTUP_FSM | Port |
| CPLLLOCK (defined in SFP3_v2_7_RX_STARTUP_FSM) | SFP3_v2_7_RX_STARTUP_FSM | Port |
| CPLLREFCLKLOST (defined in SFP3_v2_7_TX_STARTUP_FSM) | SFP3_v2_7_TX_STARTUP_FSM | Port |
| CPLLREFCLKLOST (defined in SFP3_v2_7_RX_STARTUP_FSM) | SFP3_v2_7_RX_STARTUP_FSM | Port |
| crc (defined in crc_gen_32b) | crc_gen_32b | Port |
| crc (defined in crc_gen_32b) | crc_gen_32b | Port |
| CRC_out (defined in CRC_SLINKx) | CRC_SLINKx | Port |
| crc_valid (defined in crc_gen_32b) | crc_gen_32b | Port |
| crc_valid (defined in crc_gen_32b) | crc_gen_32b | Port |
| ctrl_i (defined in xaui_wd_align) | xaui_wd_align | Port |
| ctrl_o (defined in xaui_wd_align) | xaui_wd_align | Port |
| D (defined in CRC_SLINKx) | CRC_SLINKx | Port |
| data (defined in event_generator) | event_generator | Port |
| data (defined in crc_gen_32b) | crc_gen_32b | Port |
| data (defined in rcv_pckt_s_XGMII) | rcv_pckt_s_XGMII | Port |
| data_evt (defined in Core_logic) | Core_logic | Port |
| data_evt (defined in build_pckt_s_XGMII) | build_pckt_s_XGMII | Port |
| data_fed (defined in fed_itf) | fed_itf | Port |
| data_fed (defined in Core_logic) | Core_logic | Port |
| data_i (defined in xaui_wd_align) | xaui_wd_align | Port |
| data_o (defined in xaui_wd_align) | xaui_wd_align | Port |
| data_pckt (defined in Core_logic) | Core_logic | Port |
| data_pckt (defined in build_pckt_s_XGMII) | build_pckt_s_XGMII | Port |
| data_rcv (defined in Core_logic) | Core_logic | Port |
| data_rd (defined in fed_itf) | fed_itf | Port |
| data_rd (defined in Core_logic) | Core_logic | Port |
| DATA_VALID (defined in SFP3_v2_7_RX_STARTUP_FSM) | SFP3_v2_7_RX_STARTUP_FSM | Port |
| data_valid (defined in crc_gen_32b) | crc_gen_32b | Port |
| data_valid (defined in crc_gen_32b) | crc_gen_32b | Port |
| DATA_VALID_IN (defined in SCRAMBLER) | SCRAMBLER | Port |
| DATA_VALID_IN (defined in DESCRAMBLER) | DESCRAMBLER | Port |
| data_wr (defined in fed_itf) | fed_itf | Port |
| data_wr (defined in Core_logic) | Core_logic | Port |
| datai (defined in rcv_pckt_s_XGMII) | rcv_pckt_s_XGMII | Port |
| datao (defined in build_pckt_s_XGMII) | build_pckt_s_XGMII | Port |
| datar (defined in FIFO_sync) | FIFO_sync | Port |
| dataw (defined in FIFO_sync) | FIFO_sync | Port |
| din (defined in lpm_fifo) | lpm_fifo | Port |
| din (defined in lpm_fifo_dc) | lpm_fifo_dc | Port |
| dina (defined in Memory) | Memory | Port |
| DONT_RESET_ON_DATA_ERROR (defined in SFP3_v2_7_RX_STARTUP_FSM) | SFP3_v2_7_RX_STARTUP_FSM | Port |
| DONT_RESET_ON_DATA_ERROR_IN (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| dout (defined in lpm_fifo) | lpm_fifo | Port |
| dout (defined in lpm_fifo_dc) | lpm_fifo_dc | Port |
| doutb (defined in Memory) | Memory | Port |
| DRP_clk (defined in DaqLSCXG10G) | DaqLSCXG10G | Port |
| DRPADDR_IN (defined in SFP3_v2_7_GT) | SFP3_v2_7_GT | Port |
| DRPclk (defined in XGMII_serdes_wapper) | XGMII_serdes_wapper | Port |
| DRPCLK_IN (defined in SFP3_v2_7_GT) | SFP3_v2_7_GT | Port |
| DRPDI_IN (defined in SFP3_v2_7_GT) | SFP3_v2_7_GT | Port |
| DRPDO_OUT (defined in SFP3_v2_7_GT) | SFP3_v2_7_GT | Port |
| DRPEN_IN (defined in SFP3_v2_7_GT) | SFP3_v2_7_GT | Port |
| DRPRDY_OUT (defined in SFP3_v2_7_GT) | SFP3_v2_7_GT | Port |
| DRPWE_IN (defined in SFP3_v2_7_GT) | SFP3_v2_7_GT | Port |
| EmacPhyTxC (defined in XGbEPCS32) | XGbEPCS32 | Port |
| EmacPhyTxD (defined in XGbEPCS32) | XGbEPCS32 | Port |
| empty (defined in lpm_fifo) | lpm_fifo | Port |
| empty (defined in FIFO_sync) | FIFO_sync | Port |
| ena_ack (defined in Core_logic) | Core_logic | Port |
| ena_ack (defined in rcv_pckt_s_XGMII) | rcv_pckt_s_XGMII | Port |
| ena_cmd (defined in Core_logic) | Core_logic | Port |
| ena_cmd (defined in rcv_pckt_s_XGMII) | rcv_pckt_s_XGMII | Port |
| ena_PCIe (defined in trigger_gen) | trigger_gen | Port |
| enable (defined in CRC_SLINKx) | CRC_SLINKx | Port |
| end_blk_fed (defined in fed_itf) | fed_itf | Port |
| end_blk_fed (defined in Core_logic) | Core_logic | Port |
| end_evt (defined in trigger_gen) | trigger_gen | Port |
| end_evt (defined in memory_rnd) | memory_rnd | Port |
| end_pckt (defined in build_pckt_s_XGMII) | build_pckt_s_XGMII | Port |
| end_snd_pckt (defined in Core_logic) | Core_logic | Port |
| eoc (defined in crc_gen_32b) | crc_gen_32b | Port |
| eoc (defined in crc_gen_32b) | crc_gen_32b | Port |
| EQ_MODE (defined in SFP3_v2_7_RX_STARTUP_FSM) | SFP3_v2_7_RX_STARTUP_FSM | Generic |
| error_gen (defined in build_pckt_s_XGMII) | build_pckt_s_XGMII | Port |
| error_gen (defined in rcv_pckt_s_XGMII) | rcv_pckt_s_XGMII | Port |
| evt_clk (defined in event_generator) | event_generator | Port |
| EXAMPLE_SIM_GTRESET_SPEEDUP (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Generic |
| EXAMPLE_SIMULATION (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Generic |
| EXAMPLE_USE_CHIPSCOPE (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Generic |
| EYESCANDATAERROR_OUT (defined in SFP3_v2_7_GT) | SFP3_v2_7_GT | Port |
| fifo_deep (defined in FIFO_sync) | FIFO_sync | Generic |
| Free_clki (defined in resync) | resync | Port |
| Free_clki (defined in resync) | resync | Port |
| Free_clki (defined in resync) | resync | Port |
| Free_clki (defined in resync) | resync | Port |
| frequency (defined in freq_measure) | freq_measure | Port |
| full (defined in lpm_fifo) | lpm_fifo | Port |
| full (defined in lpm_fifo_dc) | lpm_fifo_dc | Port |
| func (defined in fed_itf) | fed_itf | Port |
| func (defined in Core_logic) | Core_logic | Port |
| generator (defined in fed_itf) | fed_itf | Generic |
| Greset_clk (defined in Core_logic) | Core_logic | Port |
| Greset_clk (defined in rcv_pckt_s_XGMII) | rcv_pckt_s_XGMII | Port |
| Greset_CLK (defined in fed_itf) | fed_itf | Port |
| Greset_CLK (defined in build_pckt_s_XGMII) | build_pckt_s_XGMII | Port |
| Greset_clkT (defined in rcv_pckt_s_XGMII) | rcv_pckt_s_XGMII | Port |
| Greset_sysCLK (defined in fed_itf) | fed_itf | Port |
| GT0_DATA_VALID_IN (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT0_DRPADDR_IN (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT0_DRPCLK_IN (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT0_DRPDI_IN (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT0_DRPDO_OUT (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT0_DRPEN_IN (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT0_DRPRDY_OUT (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT0_DRPWE_IN (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT0_EYESCANDATAERROR_OUT (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT0_GTREFCLK0_COMMON_IN (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT0_GTRXRESET_IN (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT0_GTTXRESET_IN (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT0_GTXRXN_IN (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT0_GTXRXP_IN (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT0_GTXTXN_OUT (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT0_GTXTXP_OUT (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT0_LOOPBACK_IN (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT0_QPLLLOCK_OUT (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT0_QPLLLOCKDETCLK_IN (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT0_QPLLREFCLKLOST_OUT (defined in SFP3_v2_7) | SFP3_v2_7 | Port |
| GT0_QPLLRESET_IN (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT0_RX_FSM_RESET_DONE_OUT (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT0_RXBUFRESET_IN (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT0_RXBUFSTATUS_OUT (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT0_RXCDRLOCK_OUT (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT0_RXDATA_OUT (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT0_RXDATAVALID_OUT (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT0_RXDFEAGCHOLD_IN (defined in SFP3_v2_7) | SFP3_v2_7 | Port |
| GT0_RXDFELFHOLD_IN (defined in SFP3_v2_7) | SFP3_v2_7 | Port |
| GT0_RXGEARBOXSLIP_IN (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT0_RXHEADER_OUT (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT0_RXHEADERVALID_OUT (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT0_RXLPMEN_IN (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT0_RXOUTCLK_OUT (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT0_RXPCSRESET_IN (defined in SFP3_v2_7) | SFP3_v2_7 | Port |
| GT0_RXPD_IN (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT0_RXPMARESET_IN (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT0_RXPRBSCNTRESET_IN (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT0_RXPRBSERR_OUT (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT0_RXPRBSSEL_IN (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT0_RXRESETDONE_OUT (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT0_RXUSERRDY_IN (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT0_RXUSRCLK2_IN (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT0_RXUSRCLK_IN (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT0_TX_FSM_RESET_DONE_OUT (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT0_TXDATA_IN (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT0_TXDIFFCTRL_IN (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT0_TXHEADER_IN (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT0_TXINHIBIT_IN (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT0_TXMAINCURSOR_IN (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT0_TXOUTCLK_OUT (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT0_TXOUTCLKFABRIC_OUT (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT0_TXOUTCLKPCS_OUT (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT0_TXPCSRESET_IN (defined in SFP3_v2_7) | SFP3_v2_7 | Port |
| GT0_TXPD_IN (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT0_TXPRBSSEL_IN (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT0_TXRESETDONE_OUT (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT0_TXSEQUENCE_IN (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT0_TXUSERRDY_IN (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT0_TXUSRCLK2_IN (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT0_TXUSRCLK_IN (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT1_DATA_VALID_IN (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT1_DRPADDR_IN (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT1_DRPCLK_IN (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT1_DRPDI_IN (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT1_DRPDO_OUT (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT1_DRPEN_IN (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT1_DRPRDY_OUT (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT1_DRPWE_IN (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT1_EYESCANDATAERROR_OUT (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT1_GTRXRESET_IN (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT1_GTTXRESET_IN (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT1_GTXRXN_IN (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT1_GTXRXP_IN (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT1_GTXTXN_OUT (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT1_GTXTXP_OUT (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT1_LOOPBACK_IN (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT1_RX_FSM_RESET_DONE_OUT (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT1_RXBUFRESET_IN (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT1_RXBUFSTATUS_OUT (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT1_RXCDRLOCK_OUT (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT1_RXDATA_OUT (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT1_RXDATAVALID_OUT (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT1_RXDFEAGCHOLD_IN (defined in SFP3_v2_7) | SFP3_v2_7 | Port |
| GT1_RXDFELFHOLD_IN (defined in SFP3_v2_7) | SFP3_v2_7 | Port |
| GT1_RXGEARBOXSLIP_IN (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT1_RXHEADER_OUT (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT1_RXHEADERVALID_OUT (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT1_RXLPMEN_IN (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT1_RXOUTCLK_OUT (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT1_RXPCSRESET_IN (defined in SFP3_v2_7) | SFP3_v2_7 | Port |
| GT1_RXPD_IN (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT1_RXPMARESET_IN (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT1_RXPRBSCNTRESET_IN (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT1_RXPRBSERR_OUT (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT1_RXPRBSSEL_IN (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT1_RXRESETDONE_OUT (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT1_RXUSERRDY_IN (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT1_RXUSRCLK2_IN (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT1_RXUSRCLK_IN (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT1_TX_FSM_RESET_DONE_OUT (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT1_TXDATA_IN (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT1_TXDIFFCTRL_IN (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT1_TXHEADER_IN (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT1_TXINHIBIT_IN (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT1_TXMAINCURSOR_IN (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT1_TXOUTCLK_OUT (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT1_TXOUTCLKFABRIC_OUT (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT1_TXOUTCLKPCS_OUT (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT1_TXPCSRESET_IN (defined in SFP3_v2_7) | SFP3_v2_7 | Port |
| GT1_TXPD_IN (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT1_TXPRBSSEL_IN (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT1_TXRESETDONE_OUT (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT1_TXSEQUENCE_IN (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT1_TXUSERRDY_IN (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT1_TXUSRCLK2_IN (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT1_TXUSRCLK_IN (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT2_DATA_VALID_IN (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT2_DRPADDR_IN (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT2_DRPCLK_IN (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT2_DRPDI_IN (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT2_DRPDO_OUT (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT2_DRPEN_IN (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT2_DRPRDY_OUT (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT2_DRPWE_IN (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT2_EYESCANDATAERROR_OUT (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT2_GTRXRESET_IN (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT2_GTTXRESET_IN (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT2_GTXRXN_IN (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT2_GTXRXP_IN (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT2_GTXTXN_OUT (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT2_GTXTXP_OUT (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT2_LOOPBACK_IN (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT2_RX_FSM_RESET_DONE_OUT (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT2_RXBUFRESET_IN (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT2_RXBUFSTATUS_OUT (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT2_RXCDRLOCK_OUT (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT2_RXDATA_OUT (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT2_RXDATAVALID_OUT (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT2_RXDFEAGCHOLD_IN (defined in SFP3_v2_7) | SFP3_v2_7 | Port |
| GT2_RXDFELFHOLD_IN (defined in SFP3_v2_7) | SFP3_v2_7 | Port |
| GT2_RXGEARBOXSLIP_IN (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT2_RXHEADER_OUT (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT2_RXHEADERVALID_OUT (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT2_RXLPMEN_IN (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT2_RXOUTCLK_OUT (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT2_RXPCSRESET_IN (defined in SFP3_v2_7) | SFP3_v2_7 | Port |
| GT2_RXPD_IN (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT2_RXPMARESET_IN (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT2_RXPRBSCNTRESET_IN (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT2_RXPRBSERR_OUT (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT2_RXPRBSSEL_IN (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT2_RXRESETDONE_OUT (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT2_RXUSERRDY_IN (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT2_RXUSRCLK2_IN (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT2_RXUSRCLK_IN (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT2_TX_FSM_RESET_DONE_OUT (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT2_TXDATA_IN (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT2_TXDIFFCTRL_IN (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT2_TXHEADER_IN (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT2_TXINHIBIT_IN (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT2_TXMAINCURSOR_IN (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT2_TXOUTCLK_OUT (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT2_TXOUTCLKFABRIC_OUT (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT2_TXOUTCLKPCS_OUT (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT2_TXPCSRESET_IN (defined in SFP3_v2_7) | SFP3_v2_7 | Port |
| GT2_TXPD_IN (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT2_TXPRBSSEL_IN (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT2_TXRESETDONE_OUT (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT2_TXSEQUENCE_IN (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT2_TXUSERRDY_IN (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT2_TXUSRCLK2_IN (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT2_TXUSRCLK_IN (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| GT_SIM_GTRESET_SPEEDUP (defined in SFP3_v2_7_GT) | SFP3_v2_7_GT | Generic |
| GT_TYPE (defined in SFP3_v2_7_TX_STARTUP_FSM) | SFP3_v2_7_TX_STARTUP_FSM | Generic |
| GT_TYPE (defined in SFP3_v2_7_RX_STARTUP_FSM) | SFP3_v2_7_RX_STARTUP_FSM | Generic |
| GTRXRESET (defined in SFP3_v2_7_RX_STARTUP_FSM) | SFP3_v2_7_RX_STARTUP_FSM | Port |
| GTRXRESET_IN (defined in SFP3_v2_7_GT) | SFP3_v2_7_GT | Port |
| GTTXRESET (defined in SFP3_v2_7_TX_STARTUP_FSM) | SFP3_v2_7_TX_STARTUP_FSM | Port |
| GTTXRESET_IN (defined in SFP3_v2_7_GT) | SFP3_v2_7_GT | Port |
| gtx_refclk_n (defined in DaqLSCXG10G) | DaqLSCXG10G | Port |
| gtx_refclk_p (defined in DaqLSCXG10G) | DaqLSCXG10G | Port |
| gtx_reset (defined in DaqLSCXG10G) | DaqLSCXG10G | Port |
| GTX_RXD (defined in XGbEPCS32) | XGbEPCS32 | Port |
| GTX_RXDVLD (defined in XGbEPCS32) | XGbEPCS32 | Port |
| GTX_RXGEARBOXSLIP_OUT (defined in XGbEPCS32) | XGbEPCS32 | Port |
| GTX_RXGOOD (defined in XGbEPCS32) | XGbEPCS32 | Port |
| GTX_RXHEADER (defined in XGbEPCS32) | XGbEPCS32 | Port |
| GTX_RXHEADERVLD (defined in XGbEPCS32) | XGbEPCS32 | Port |
| gtx_rxresetdone (defined in XGMII_serdes_wapper) | XGMII_serdes_wapper | Port |
| GTX_TX_PAUSE (defined in XGbEPCS32) | XGbEPCS32 | Port |
| GTX_TXD (defined in XGbEPCS32) | XGbEPCS32 | Port |
| GTX_TXHEADER (defined in XGbEPCS32) | XGbEPCS32 | Port |
| GTXRXN_IN (defined in SFP3_v2_7_GT) | SFP3_v2_7_GT | Port |
| GTXRXP_IN (defined in SFP3_v2_7_GT) | SFP3_v2_7_GT | Port |
| GTXTXN_OUT (defined in SFP3_v2_7_GT) | SFP3_v2_7_GT | Port |
| GTXTXP_OUT (defined in SFP3_v2_7_GT) | SFP3_v2_7_GT | Port |
| idle_state (defined in Core_logic) | Core_logic | Port |
| idle_state (defined in build_pckt_s_XGMII) | build_pckt_s_XGMII | Port |
| inh_TX (defined in XGbEPCS32) | XGbEPCS32 | Port |
| init_pckt (defined in Core_logic) | Core_logic | Port |
| init_pckt (defined in build_pckt_s_XGMII) | build_pckt_s_XGMII | Port |
| inject_err (defined in SLINK_opt_XGMII) | SLINK_opt_XGMII | Port |
| input (defined in resync) | resync | Port |
| input (defined in resync) | resync | Port |
| input (defined in resync) | resync | Port |
| input (defined in resync) | resync | Port |
| interval_retrans (defined in Core_logic) | Core_logic | Generic |
| k_byte (defined in build_pckt_s_XGMII) | build_pckt_s_XGMII | Port |
| k_byte (defined in rcv_pckt_s_XGMII) | rcv_pckt_s_XGMII | Port |
| len_pckt (defined in Core_logic) | Core_logic | Port |
| len_pckt (defined in build_pckt_s_XGMII) | build_pckt_s_XGMII | Port |
| LINK_LFF (defined in SLINK_opt_XGMII) | SLINK_opt_XGMII | Port |
| LinkAlmostFull (defined in fed_itf) | fed_itf | Port |
| LinkCtrl (defined in DaqLSCXG10G) | DaqLSCXG10G | Port |
| LINKCtrl (defined in SLINK_opt_XGMII) | SLINK_opt_XGMII | Port |
| LinkData (defined in DaqLSCXG10G) | DaqLSCXG10G | Port |
| LINKData (defined in SLINK_opt_XGMII) | SLINK_opt_XGMII | Port |
| LINKDown (defined in SLINK_opt_XGMII) | SLINK_opt_XGMII | Port |
| LinkDown (defined in DaqLSCXG10G) | DaqLSCXG10G | Port |
| LinkFull (defined in DaqLSCXG10G) | DaqLSCXG10G | Port |
| LinkWe (defined in DaqLSCXG10G) | DaqLSCXG10G | Port |
| LINKWe (defined in SLINK_opt_XGMII) | SLINK_opt_XGMII | Port |
| LOAD_SEED (defined in generate_3) | generate_3 | Port |
| LOOPBACK_IN (defined in SFP3_v2_7_GT) | SFP3_v2_7_GT | Port |
| low_clk (defined in event_generator) | event_generator | Port |
| MMCM_LOCK (defined in SFP3_v2_7_TX_STARTUP_FSM) | SFP3_v2_7_TX_STARTUP_FSM | Port |
| MMCM_LOCK (defined in SFP3_v2_7_RX_STARTUP_FSM) | SFP3_v2_7_RX_STARTUP_FSM | Port |
| MMCM_RESET (defined in SFP3_v2_7_TX_STARTUP_FSM) | SFP3_v2_7_TX_STARTUP_FSM | Port |
| MMCM_RESET (defined in SFP3_v2_7_RX_STARTUP_FSM) | SFP3_v2_7_RX_STARTUP_FSM | Port |
| mydefs (defined in DaqLSCXG10G) | DaqLSCXG10G | use clause |
| N_SFP (defined in XGMII_serdes_wapper) | XGMII_serdes_wapper | Generic |
| NUMERIC_STD (defined in SFP3_v2_7_TX_STARTUP_FSM) | SFP3_v2_7_TX_STARTUP_FSM | use clause |
| NUMERIC_STD (defined in SFP3_v2_7_RX_STARTUP_FSM) | SFP3_v2_7_RX_STARTUP_FSM | use clause |
| numeric_std (defined in SLINK_opt_XGMII) | SLINK_opt_XGMII | use clause |
| numeric_std (defined in BLOCK_SYNC_SM) | BLOCK_SYNC_SM | use clause |
| numeric_std (defined in SCRAMBLER) | SCRAMBLER | use clause |
| numeric_std (defined in DESCRAMBLER) | DESCRAMBLER | use clause |
| numeric_std (defined in SFP3_v2_7_init) | SFP3_v2_7_init | use clause |
| output (defined in resync) | resync | Port |
| output (defined in resync) | resync | Port |
| output (defined in resync) | resync | Port |
| output (defined in resync) | resync | Port |
| PCIe_clk (defined in event_generator) | event_generator | Port |
| PCIe_cs (defined in event_generator) | event_generator | Port |
| PCIe_dt (defined in memory_rnd) | memory_rnd | Port |
| PCIe_dti (defined in event_generator) | event_generator | Port |
| PCIe_dto (defined in event_generator) | event_generator | Port |
| PCIe_func (defined in event_generator) | event_generator | Port |
| PCIe_wen (defined in event_generator) | event_generator | Port |
| PCS_lock (defined in XGMII_serdes_wapper) | XGMII_serdes_wapper | Port |
| PCS_RSVD_ATTR_IN (defined in SFP3_v2_7_GT) | SFP3_v2_7_GT | Generic |
| PHALIGNMENT_DONE (defined in SFP3_v2_7_TX_STARTUP_FSM) | SFP3_v2_7_TX_STARTUP_FSM | Port |
| PHALIGNMENT_DONE (defined in SFP3_v2_7_RX_STARTUP_FSM) | SFP3_v2_7_RX_STARTUP_FSM | Port |
| PHASE_ALIGNMENT_MANUAL (defined in SFP3_v2_7_TX_STARTUP_FSM) | SFP3_v2_7_TX_STARTUP_FSM | Generic |
| PHASE_ALIGNMENT_MANUAL (defined in SFP3_v2_7_RX_STARTUP_FSM) | SFP3_v2_7_RX_STARTUP_FSM | Generic |
| PhyEmacRxC (defined in XGbEPCS32) | XGbEPCS32 | Port |
| PhyEmacRxD (defined in XGbEPCS32) | XGbEPCS32 | Port |
| PMA_RSV_IN (defined in SFP3_v2_7) | SFP3_v2_7 | Generic |
| QPLL_FBDIV_TOP (defined in SFP3_v2_7) | SFP3_v2_7 | Generic |
| QPLL_RESET (defined in SFP3_v2_7_TX_STARTUP_FSM) | SFP3_v2_7_TX_STARTUP_FSM | Port |
| QPLL_RESET (defined in SFP3_v2_7_RX_STARTUP_FSM) | SFP3_v2_7_RX_STARTUP_FSM | Port |
| QPLLCLK_IN (defined in SFP3_v2_7_GT) | SFP3_v2_7_GT | Port |
| QPLLLOCK (defined in SFP3_v2_7_TX_STARTUP_FSM) | SFP3_v2_7_TX_STARTUP_FSM | Port |
| QPLLLOCK (defined in SFP3_v2_7_RX_STARTUP_FSM) | SFP3_v2_7_RX_STARTUP_FSM | Port |
| QPLLREFCLK_IN (defined in SFP3_v2_7_GT) | SFP3_v2_7_GT | Port |
| QPLLREFCLKLOST (defined in SFP3_v2_7_TX_STARTUP_FSM) | SFP3_v2_7_TX_STARTUP_FSM | Port |
| QPLLREFCLKLOST (defined in SFP3_v2_7_RX_STARTUP_FSM) | SFP3_v2_7_RX_STARTUP_FSM | Port |
| rd_clk (defined in lpm_fifo_dc) | lpm_fifo_dc | Port |
| rd_dt (defined in Core_logic) | Core_logic | Port |
| rd_dt (defined in build_pckt_s_XGMII) | build_pckt_s_XGMII | Port |
| rd_en (defined in lpm_fifo) | lpm_fifo | Port |
| rd_en (defined in lpm_fifo_dc) | lpm_fifo_dc | Port |
| rd_rst (defined in lpm_fifo_dc) | lpm_fifo_dc | Port |
| read_bck (defined in build_pckt_s_XGMII) | build_pckt_s_XGMII | Port |
| read_CE (defined in SLINK_opt_XGMII) | SLINK_opt_XGMII | Port |
| read_ce (defined in fed_itf) | fed_itf | Port |
| RECCLK_MONITOR_RESTART (defined in SFP3_v2_7_RX_STARTUP_FSM) | SFP3_v2_7_RX_STARTUP_FSM | Port |
| RECCLK_STABLE (defined in SFP3_v2_7_RX_STARTUP_FSM) | SFP3_v2_7_RX_STARTUP_FSM | Port |
| ren (defined in FIFO_sync) | FIFO_sync | Port |
| req_reset_resync (defined in Core_logic) | Core_logic | Port |
| reset (defined in SLINK_opt_XGMII) | SLINK_opt_XGMII | Port |
| reset (defined in XGMII_serdes_wapper) | XGMII_serdes_wapper | Port |
| reset_clk (defined in Core_logic) | Core_logic | Port |
| reset_clk (defined in rcv_pckt_s_XGMII) | rcv_pckt_s_XGMII | Port |
| reset_CLK (defined in fed_itf) | fed_itf | Port |
| reset_CLK (defined in build_pckt_s_XGMII) | build_pckt_s_XGMII | Port |
| reset_clkT (defined in rcv_pckt_s_XGMII) | rcv_pckt_s_XGMII | Port |
| RESET_PHALIGNMENT (defined in SFP3_v2_7_TX_STARTUP_FSM) | SFP3_v2_7_TX_STARTUP_FSM | Port |
| RESET_PHALIGNMENT (defined in SFP3_v2_7_RX_STARTUP_FSM) | SFP3_v2_7_RX_STARTUP_FSM | Port |
| Reset_sync (defined in reset_resync) | reset_resync | Port |
| Reset_sync (defined in reset_resync) | reset_resync | Port |
| Reset_sync (defined in reset_resync) | reset_resync | Port |
| reset_sysCLK (defined in fed_itf) | fed_itf | Port |
| RESET_TXSync (defined in XGbEPCS32) | XGbEPCS32 | Port |
| retransmit (defined in Core_logic) | Core_logic | Port |
| retransmit_ena (defined in fed_itf) | fed_itf | Port |
| RETRY_COUNTER (defined in SFP3_v2_7_TX_STARTUP_FSM) | SFP3_v2_7_TX_STARTUP_FSM | Port |
| RETRY_COUNTER (defined in SFP3_v2_7_RX_STARTUP_FSM) | SFP3_v2_7_RX_STARTUP_FSM | Port |
| RETRY_COUNTER_BITWIDTH (defined in SFP3_v2_7_TX_STARTUP_FSM) | SFP3_v2_7_TX_STARTUP_FSM | Generic |
| RETRY_COUNTER_BITWIDTH (defined in SFP3_v2_7_RX_STARTUP_FSM) | SFP3_v2_7_RX_STARTUP_FSM | Generic |
| rnd (defined in generate_3) | generate_3 | Port |
| rst (defined in lpm_fifo) | lpm_fifo | Port |
| Rst_Evtclk (defined in trigger_gen) | trigger_gen | Port |
| RST_EvtClk (defined in memory_rnd) | memory_rnd | Port |
| rst_length (defined in Core_logic) | Core_logic | Generic |
| RST_lowClk (defined in memory_rnd) | memory_rnd | Port |
| Rst_Pciclk (defined in trigger_gen) | trigger_gen | Port |
| RST_PCIClk (defined in memory_rnd) | memory_rnd | Port |
| rstb (defined in Memory) | Memory | Port |
| run_mode (defined in trigger_gen) | trigger_gen | Port |
| RUN_PHALIGNMENT (defined in SFP3_v2_7_TX_STARTUP_FSM) | SFP3_v2_7_TX_STARTUP_FSM | Port |
| RUN_PHALIGNMENT (defined in SFP3_v2_7_RX_STARTUP_FSM) | SFP3_v2_7_RX_STARTUP_FSM | Port |
| RX_DATA_WIDTH (defined in DESCRAMBLER) | DESCRAMBLER | Generic |
| RX_DFE_KL_CFG2_IN (defined in SFP3_v2_7) | SFP3_v2_7 | Generic |
| RX_FSM_RESET_DONE (defined in SFP3_v2_7_RX_STARTUP_FSM) | SFP3_v2_7_RX_STARTUP_FSM | Port |
| RX_QPLL_USED (defined in SFP3_v2_7_TX_STARTUP_FSM) | SFP3_v2_7_TX_STARTUP_FSM | Generic |
| RX_QPLL_USED (defined in SFP3_v2_7_RX_STARTUP_FSM) | SFP3_v2_7_RX_STARTUP_FSM | Generic |
| RXBUFRESET_IN (defined in SFP3_v2_7_GT) | SFP3_v2_7_GT | Port |
| RXBUFSTATUS_OUT (defined in SFP3_v2_7_GT) | SFP3_v2_7_GT | Port |
| RXCDRLOCK_OUT (defined in SFP3_v2_7_GT) | SFP3_v2_7_GT | Port |
| RXDATA_OUT (defined in SFP3_v2_7_GT) | SFP3_v2_7_GT | Port |
| RXDATAVALID_OUT (defined in SFP3_v2_7_GT) | SFP3_v2_7_GT | Port |
| RXDFEAGCHOLD (defined in SFP3_v2_7_RX_STARTUP_FSM) | SFP3_v2_7_RX_STARTUP_FSM | Port |
| RXDFEAGCHOLD_IN (defined in SFP3_v2_7_GT) | SFP3_v2_7_GT | Port |
| RXDFELFHOLD (defined in SFP3_v2_7_RX_STARTUP_FSM) | SFP3_v2_7_RX_STARTUP_FSM | Port |
| RXDFELFHOLD_IN (defined in SFP3_v2_7_GT) | SFP3_v2_7_GT | Port |
| RXGEARBOXSLIP_IN (defined in SFP3_v2_7_GT) | SFP3_v2_7_GT | Port |
| RXGEARBOXSLIP_OUT (defined in BLOCK_SYNC_SM) | BLOCK_SYNC_SM | Port |
| RXHEADER_IN (defined in BLOCK_SYNC_SM) | BLOCK_SYNC_SM | Port |
| RXHEADER_OUT (defined in SFP3_v2_7_GT) | SFP3_v2_7_GT | Port |
| RXHEADERVALID_IN (defined in BLOCK_SYNC_SM) | BLOCK_SYNC_SM | Port |
| RXHEADERVALID_OUT (defined in SFP3_v2_7_GT) | SFP3_v2_7_GT | Port |
| RXLPMEN_IN (defined in SFP3_v2_7_GT) | SFP3_v2_7_GT | Port |
| RXLPMHFHOLD (defined in SFP3_v2_7_RX_STARTUP_FSM) | SFP3_v2_7_RX_STARTUP_FSM | Port |
| RXLPMLFHOLD (defined in SFP3_v2_7_RX_STARTUP_FSM) | SFP3_v2_7_RX_STARTUP_FSM | Port |
| RXOUTCLK_OUT (defined in SFP3_v2_7_GT) | SFP3_v2_7_GT | Port |
| RXPCSRESET_IN (defined in SFP3_v2_7_GT) | SFP3_v2_7_GT | Port |
| RXPD_IN (defined in SFP3_v2_7_GT) | SFP3_v2_7_GT | Port |
| RXPMARESET_IN (defined in SFP3_v2_7_GT) | SFP3_v2_7_GT | Port |
| RXPRBSCNTRESET_IN (defined in SFP3_v2_7_GT) | SFP3_v2_7_GT | Port |
| RXPRBSERR_OUT (defined in SFP3_v2_7_GT) | SFP3_v2_7_GT | Port |
| RXPRBSSEL_IN (defined in SFP3_v2_7_GT) | SFP3_v2_7_GT | Port |
| RXRESETDONE (defined in XGbEPCS32) | XGbEPCS32 | Port |
| RXRESETDONE (defined in SFP3_v2_7_RX_STARTUP_FSM) | SFP3_v2_7_RX_STARTUP_FSM | Port |
| RXRESETDONE_OUT (defined in SFP3_v2_7_GT) | SFP3_v2_7_GT | Port |
| RXUSERCLK (defined in SFP3_v2_7_RX_STARTUP_FSM) | SFP3_v2_7_RX_STARTUP_FSM | Port |
| RXUSERRDY (defined in SFP3_v2_7_RX_STARTUP_FSM) | SFP3_v2_7_RX_STARTUP_FSM | Port |
| RXUSERRDY_IN (defined in SFP3_v2_7_GT) | SFP3_v2_7_GT | Port |
| RXUSRCLK (defined in XGbEPCS32) | XGbEPCS32 | Port |
| RXUSRCLK2_IN (defined in SFP3_v2_7_GT) | SFP3_v2_7_GT | Port |
| RXUSRCLK_IN (defined in SFP3_v2_7_GT) | SFP3_v2_7_GT | Port |
| rxusrclk_o (defined in DaqLSCXG10G) | DaqLSCXG10G | Port |
| SCRAMBLED_DATA_IN (defined in DESCRAMBLER) | DESCRAMBLER | Port |
| SCRAMBLED_DATA_OUT (defined in SCRAMBLER) | SCRAMBLER | Port |
| SD_Data_i (defined in SLINK_opt_XGMII) | SLINK_opt_XGMII | Port |
| SD_Data_o (defined in SLINK_opt_XGMII) | SLINK_opt_XGMII | Port |
| SD_Kb_i (defined in SLINK_opt_XGMII) | SLINK_opt_XGMII | Port |
| SD_Kb_o (defined in SLINK_opt_XGMII) | SLINK_opt_XGMII | Port |
| SEED (defined in generate_3) | generate_3 | Port |
| Seq_nb (defined in Core_logic) | Core_logic | Port |
| Seq_nb (defined in build_pckt_s_XGMII) | build_pckt_s_XGMII | Port |
| seqnb (defined in rcv_pckt_s_XGMII) | rcv_pckt_s_XGMII | Port |
| seqnb_rcv (defined in Core_logic) | Core_logic | Port |
| serdes_init (defined in SLINK_opt_XGMII) | SLINK_opt_XGMII | Port |
| Serdes_status (defined in SLINK_opt_XGMII) | SLINK_opt_XGMII | Port |
| SFP0_RXN (defined in XGMII_serdes_wapper) | XGMII_serdes_wapper | Port |
| SFP0_RXP (defined in XGMII_serdes_wapper) | XGMII_serdes_wapper | Port |
| SFP0_TXN (defined in XGMII_serdes_wapper) | XGMII_serdes_wapper | Port |
| SFP0_TXP (defined in XGMII_serdes_wapper) | XGMII_serdes_wapper | Port |
| SFP1_RXN (defined in XGMII_serdes_wapper) | XGMII_serdes_wapper | Port |
| SFP1_RXP (defined in XGMII_serdes_wapper) | XGMII_serdes_wapper | Port |
| SFP1_TXN (defined in XGMII_serdes_wapper) | XGMII_serdes_wapper | Port |
| SFP1_TXP (defined in XGMII_serdes_wapper) | XGMII_serdes_wapper | Port |
| SFP2_RXN (defined in XGMII_serdes_wapper) | XGMII_serdes_wapper | Port |
| SFP2_RXP (defined in XGMII_serdes_wapper) | XGMII_serdes_wapper | Port |
| SFP2_TXN (defined in XGMII_serdes_wapper) | XGMII_serdes_wapper | Port |
| SFP2_TXP (defined in XGMII_serdes_wapper) | XGMII_serdes_wapper | Port |
| sfp_pd (defined in DaqLSCXG10G) | DaqLSCXG10G | Port |
| SFP_REFCLK_N (defined in XGMII_serdes_wapper) | XGMII_serdes_wapper | Port |
| SFP_REFCLK_P (defined in XGMII_serdes_wapper) | XGMII_serdes_wapper | Port |
| sfp_rxn (defined in DaqLSCXG10G) | DaqLSCXG10G | Port |
| sfp_rxp (defined in DaqLSCXG10G) | DaqLSCXG10G | Port |
| sfp_txn (defined in DaqLSCXG10G) | DaqLSCXG10G | Port |
| sfp_txp (defined in DaqLSCXG10G) | DaqLSCXG10G | Port |
| SH_CNT_MAX (defined in BLOCK_SYNC_SM) | BLOCK_SYNC_SM | Generic |
| SH_INVALID_CNT_MAX (defined in BLOCK_SYNC_SM) | BLOCK_SYNC_SM | Generic |
| SOFT_RESET (defined in SFP3_v2_7_TX_STARTUP_FSM) | SFP3_v2_7_TX_STARTUP_FSM | Port |
| SOFT_RESET (defined in SFP3_v2_7_RX_STARTUP_FSM) | SFP3_v2_7_RX_STARTUP_FSM | Port |
| SOFT_RESET_IN (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| src_ID (defined in SLINK_opt_XGMII) | SLINK_opt_XGMII | Port |
| srcID (defined in DaqLSCXG10G) | DaqLSCXG10G | Port |
| sta_dt (defined in Core_logic) | Core_logic | Port |
| STABLE_CLOCK (defined in SFP3_v2_7_TX_STARTUP_FSM) | SFP3_v2_7_TX_STARTUP_FSM | Port |
| STABLE_CLOCK (defined in SFP3_v2_7_RX_STARTUP_FSM) | SFP3_v2_7_RX_STARTUP_FSM | Port |
| STABLE_CLOCK_PERIOD (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Generic |
| START (defined in generate_3) | generate_3 | Port |
| start (defined in memory_rnd) | memory_rnd | Port |
| start_evt (defined in fed_itf) | fed_itf | Port |
| start_evt (defined in Core_logic) | Core_logic | Port |
| start_pckt (defined in Core_logic) | Core_logic | Port |
| start_pckt (defined in build_pckt_s_XGMII) | build_pckt_s_XGMII | Port |
| status (defined in Core_logic) | Core_logic | Port |
| status (defined in rcv_pckt_s_XGMII) | rcv_pckt_s_XGMII | Port |
| status (defined in XGbEPCS32) | XGbEPCS32 | Port |
| status_addr (defined in DaqLSCXG10G) | DaqLSCXG10G | Port |
| status_ce (defined in DaqLSCXG10G) | DaqLSCXG10G | Port |
| status_data (defined in SLINK_opt_XGMII) | SLINK_opt_XGMII | Port |
| status_port (defined in DaqLSCXG10G) | DaqLSCXG10G | Port |
| status_state (defined in Core_logic) | Core_logic | Port |
| status_state (defined in build_pckt_s_XGMII) | build_pckt_s_XGMII | Port |
| status_state_build_p (defined in fed_itf) | fed_itf | Port |
| status_state_core (defined in fed_itf) | fed_itf | Port |
| stop_evt (defined in fed_itf) | fed_itf | Port |
| stop_evt (defined in Core_logic) | Core_logic | Port |
| sync_loss (defined in DaqLSCXG10G) | DaqLSCXG10G | Port |
| SYS_CLK (defined in SLINK_opt_XGMII) | SLINK_opt_XGMII | Port |
| sys_clk (defined in DaqLSCXG10G) | DaqLSCXG10G | Port |
| sys_reset (defined in DaqLSCXG10G) | DaqLSCXG10G | Port |
| sysclk (defined in freq_measure) | freq_measure | Port |
| SYSCLK_IN (defined in SFP3_v2_7_init) | SFP3_v2_7_init | Port |
| SYSTEM_RESET (defined in BLOCK_SYNC_SM) | BLOCK_SYNC_SM | Port |
| SYSTEM_RESET (defined in SCRAMBLER) | SCRAMBLER | Port |
| SYSTEM_RESET (defined in DESCRAMBLER) | DESCRAMBLER | Port |
| time_out_val (defined in Core_logic) | Core_logic | Generic |
| trig_nb (defined in trigger_gen) | trigger_gen | Port |
| trigger (defined in trigger_gen) | trigger_gen | Port |
| trigger (defined in memory_rnd) | memory_rnd | Port |
| ttc_trigger (defined in trigger_gen) | trigger_gen | Port |
| TX_DATA_WIDTH (defined in SCRAMBLER) | SCRAMBLER | Generic |
| TX_FSM_RESET_DONE (defined in SFP3_v2_7_TX_STARTUP_FSM) | SFP3_v2_7_TX_STARTUP_FSM | Port |
| TX_high (defined in XGbEPCS32) | XGbEPCS32 | Port |
| TX_QPLL_USED (defined in SFP3_v2_7_TX_STARTUP_FSM) | SFP3_v2_7_TX_STARTUP_FSM | Generic |
| TX_QPLL_USED (defined in SFP3_v2_7_RX_STARTUP_FSM) | SFP3_v2_7_RX_STARTUP_FSM | Generic |
| TXDATA_IN (defined in SFP3_v2_7_GT) | SFP3_v2_7_GT | Port |
| TXDIFFCTRL_IN (defined in SFP3_v2_7_GT) | SFP3_v2_7_GT | Port |
| TXHEADER_IN (defined in SFP3_v2_7_GT) | SFP3_v2_7_GT | Port |
| TXINHIBIT_IN (defined in SFP3_v2_7_GT) | SFP3_v2_7_GT | Port |
| TXMAINCURSOR_IN (defined in SFP3_v2_7_GT) | SFP3_v2_7_GT | Port |
| TXOUTCLK_OUT (defined in SFP3_v2_7_GT) | SFP3_v2_7_GT | Port |
| TXOUTCLKFABRIC_OUT (defined in SFP3_v2_7_GT) | SFP3_v2_7_GT | Port |
| TXOUTCLKPCS_OUT (defined in SFP3_v2_7_GT) | SFP3_v2_7_GT | Port |
| TXPCSRESET_IN (defined in SFP3_v2_7_GT) | SFP3_v2_7_GT | Port |
| TXPD_IN (defined in SFP3_v2_7_GT) | SFP3_v2_7_GT | Port |
| TXPRBSSEL_IN (defined in SFP3_v2_7_GT) | SFP3_v2_7_GT | Port |
| TXRESETDONE (defined in SFP3_v2_7_TX_STARTUP_FSM) | SFP3_v2_7_TX_STARTUP_FSM | Port |
| TXRESETDONE_OUT (defined in SFP3_v2_7_GT) | SFP3_v2_7_GT | Port |
| TXSEQUENCE_IN (defined in SFP3_v2_7_GT) | SFP3_v2_7_GT | Port |
| TXUSERCLK (defined in SFP3_v2_7_TX_STARTUP_FSM) | SFP3_v2_7_TX_STARTUP_FSM | Port |
| TXUSERRDY (defined in SFP3_v2_7_TX_STARTUP_FSM) | SFP3_v2_7_TX_STARTUP_FSM | Port |
| TXUSERRDY (defined in SFP3_v2_7_RX_STARTUP_FSM) | SFP3_v2_7_RX_STARTUP_FSM | Port |
| TXUSERRDY_IN (defined in SFP3_v2_7_GT) | SFP3_v2_7_GT | Port |
| TXUSRCLK (defined in XGbEPCS32) | XGbEPCS32 | Port |
| TXUSRCLK2_IN (defined in SFP3_v2_7_GT) | SFP3_v2_7_GT | Port |
| TXUSRCLK_IN (defined in SFP3_v2_7_GT) | SFP3_v2_7_GT | Port |
| txusrclk_o (defined in DaqLSCXG10G) | DaqLSCXG10G | Port |
| uctrl (defined in event_generator) | event_generator | Port |
| UNISIM (defined in DaqLSCXG10G) | DaqLSCXG10G | Library |
| UNSCRAMBLED_DATA_IN (defined in SCRAMBLER) | SCRAMBLER | Port |
| UNSCRAMBLED_DATA_OUT (defined in DESCRAMBLER) | DESCRAMBLER | Port |
| USER_CLK (defined in BLOCK_SYNC_SM) | BLOCK_SYNC_SM | Port |
| USER_CLK (defined in SCRAMBLER) | SCRAMBLER | Port |
| USER_CLK (defined in DESCRAMBLER) | DESCRAMBLER | Port |
| VComponents (defined in DaqLSCXG10G) | DaqLSCXG10G | use clause |
| VCOMPONENTS (defined in BLOCK_SYNC_SM) | BLOCK_SYNC_SM | use clause |
| VCOMPONENTS (defined in SCRAMBLER) | SCRAMBLER | use clause |
| VCOMPONENTS (defined in DESCRAMBLER) | DESCRAMBLER | use clause |
| VCOMPONENTS (defined in SFP3_v2_7_init) | SFP3_v2_7_init | use clause |
| wc (defined in memory_rnd) | memory_rnd | Port |
| wea (defined in Memory) | Memory | Port |
| wen (defined in event_generator) | event_generator | Port |
| wen (defined in FIFO_sync) | FIFO_sync | Port |
| wen (defined in Core_logic) | Core_logic | Port |
| work (defined in fed_itf) | fed_itf | Library |
| wr_clk (defined in lpm_fifo_dc) | lpm_fifo_dc | Port |
| wr_cmd (defined in fed_itf) | fed_itf | Port |
| wr_cmd (defined in Core_logic) | Core_logic | Port |
| wr_data_count (defined in lpm_fifo_dc) | lpm_fifo_dc | Port |
| wr_en (defined in lpm_fifo) | lpm_fifo | Port |
| wr_en (defined in lpm_fifo_dc) | lpm_fifo_dc | Port |
| wr_ena (defined in fed_itf) | fed_itf | Port |
| wr_rst (defined in lpm_fifo_dc) | lpm_fifo_dc | Port |
| WRAPPER_SIM_GTRESET_SPEEDUP (defined in SFP3_v2_7) | SFP3_v2_7 | Generic |
| xgmii_rxc (defined in XGMII_serdes_wapper) | XGMII_serdes_wapper | Port |
| xgmii_rxd (defined in XGMII_serdes_wapper) | XGMII_serdes_wapper | Port |
| xgmii_txc (defined in XGMII_serdes_wapper) | XGMII_serdes_wapper | Port |
| xgmii_txd (defined in XGMII_serdes_wapper) | XGMII_serdes_wapper | Port |
| XilinxCoreLib (defined in lpm_fifo) | lpm_fifo | Library |
| XilinxCoreLib (defined in lpm_fifo_dc) | lpm_fifo_dc | Library |
| XilinxCoreLib (defined in Memory) | Memory | Library |
1.8.1
