Memory Entity Reference

Inheritance diagram for Memory:

List of all members.

Entities
Memory_a	architecture

Libraries
XilinxCoreLib

Ports
clka	in STD_LOGIC
wea	in STD_LOGIC_VECTOR ( 0 downto 0 )
addra	in STD_LOGIC_VECTOR ( 10 downto 0 )
dina	in STD_LOGIC_VECTOR ( 63 downto 0 )
clkb	in STD_LOGIC
rstb	in STD_LOGIC
addrb	in STD_LOGIC_VECTOR ( 10 downto 0 )
doutb	out STD_LOGIC_VECTOR ( 63 downto 0 )

---

Detailed Description

Definition at line 43 of file Memory.vhd.

---

The documentation for this class was generated from the following file:

• src/CMS_DAQ_if/5Gb/slink/Memory.vhd