trigger_gen Entity Reference

Inheritance diagram for trigger_gen:

List of all members.

Entities
behavioral	architecture

Use Clauses
numeric_std

Ports
Rst_Pciclk	in std_logic
PCIe_clk	in std_logic
PCIe_func	in std_logic_vector ( 15 downto 0 )
PCIe_wen	in std_logic
PCIe_dti	in std_logic_vector ( 31 downto 0 )
PCIe_dto	out std_logic_vector ( 31 downto 0 )
PCIe_cs	in std_logic
ttc_trigger	in std_logic
Rst_Evtclk	in std_logic
evt_clk	in std_logic
ena_PCIe	out std_logic
run_mode	out std_logic
trig_nb	out std_logic_vector ( 23 downto 0 )
trigger	out std_logic
end_evt	in std_logic
Back_p	in std_logic

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Detailed Description

Definition at line 26 of file trigger_gen.vhd.

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The documentation for this class was generated from the following files:

• src/CMS_DAQ_if/10Gb/slink/trigger_gen.vhd
• src/CMS_DAQ_if/5Gb/slink/trigger_gen.vhd