AMC13
Firmwares for the different applications of the AMC13 uTCA board made at Boston University
 All Classes Variables
Entities | Public Attributes
Core_logic Entity Reference
Inheritance diagram for Core_logic:
Inheritance graph
[legend]

List of all members.

Entities

behavioral  architecture

Use Clauses

numeric_std 

Generics

time_out_val  std_logic_vector ( 15 downto 0 ) := x " 0200 "
interval_retrans  std_logic_vector ( 19 downto 0 ) := x " 186A0 "
rst_length  integer := 4

Ports

reset_clk   in std_logic
Greset_clk   in std_logic
clock   in std_logic
data_fed   in std_logic_vector ( 63 downto 0 )
wen   in std_logic
start_evt   in std_logic
stop_evt   in std_logic
block_sz_fed   in std_logic_vector ( 15 downto 0 )
end_blk_fed   in std_logic
block_free   out std_logic
src_ID   in std_logic_vector ( 15 downto 0 )
req_reset_resync   out std_logic
start_pckt   out std_logic
init_pckt   out std_logic
ack_pckt   out std_logic
data_pckt   out std_logic
data_evt   out std_logic_vector ( 63 downto 0 )
status   out std_logic_vector ( 63 downto 0 )
card_ID   out std_logic_vector ( 15 downto 0 )
Seq_nb   out std_logic_vector ( 30 downto 0 )
len_pckt   out std_logic_vector ( 15 downto 0 )
cmd   out std_logic_vector ( 63 downto 0 )
rd_dt   in std_logic
end_snd_pckt   in std_logic
idle_state   in std_logic
serdes_init   in std_logic
cmd_rcv   in std_logic_vector ( 31 downto 0 )
data_rcv   in std_logic_vector ( 31 downto 0 )
ena_cmd   in std_logic
sta_dt   in std_logic_vector ( 63 downto 0 )
ena_ack   in std_logic
seqnb_rcv   in std_logic_vector ( 30 downto 0 )
card_ID_rcv   in std_logic_vector ( 15 downto 0 )
retransmit   out std_logic
wr_cmd   out std_logic
func   out std_logic_vector ( 31 downto 0 )
data_wr   out std_logic_vector ( 31 downto 0 )
data_rd   in std_logic_vector ( 63 downto 0 )
status_state   out std_logic_vector ( 31 downto 0 )

Detailed Description

Definition at line 19 of file core_logic.vhd.


The documentation for this class was generated from the following files: