arch_ddr3_1_9a Architecture Reference

List of all members.

Functions
integer	clogb2 ( size: in integer )
string	TEMP_MON ( )

Components
mig_7series_v1_9_iodelay_ctrl	<Entity mig_7series_v1_9_iodelay_ctrl>
mig_7series_v1_9_clk_ibuf	<Entity mig_7series_v1_9_clk_ibuf>
mig_7series_v1_9_infrastructure	<Entity mig_7series_v1_9_infrastructure>
mig_7series_v1_9_tempmon	<Entity mig_7series_v1_9_tempmon>
mig_7series_v1_9_memc_ui_top_std	<Entity mig_7series_v1_9_memc_ui_top_std>

Constants
BM_CNT_WIDTH	integer := clogb2 ( nBANK_MACHS )
RANK_WIDTH	integer := clogb2 ( RANKS )
APP_DATA_WIDTH	integer := 2 * nCK_PER_CLK * PAYLOAD_WIDTH
APP_MASK_WIDTH	integer := APP_DATA_WIDTH / 8
TEMP_MON_EN	string := TEMP_MON
tTEMPSAMPLE	integer := 10000000
XADC_CLK_PERIOD	integer := 5000

Signals
bank_mach_next	std_logic_vector ( BM_CNT_WIDTH - 1 downto 0 )
clk	std_logic
clk_ref	std_logic
iodelay_ctrl_rdy	std_logic
clk_ref_in	std_logic
sys_rst_o	std_logic
freq_refclk	std_logic
mem_refclk	std_logic
pll_locked	std_logic
sync_pulse	std_logic
ref_dll_lock	std_logic
rst_phaser_ref	std_logic
rst	std_logic
app_ecc_multiple_err	std_logic_vector ( 2 * nCK_PER_CLK - 1 downto 0 )
ddr3_parity	std_logic
init_calib_complete_i	std_logic
sys_clk_i	std_logic
mmcm_clk	std_logic
clk_ref_p	std_logic
clk_ref_n	std_logic
device_temp	std_logic_vector ( 11 downto 0 )
dbg_idel_down_all	std_logic
dbg_idel_down_cpt	std_logic
dbg_idel_up_all	std_logic
dbg_idel_up_cpt	std_logic
dbg_sel_all_idel_cpt	std_logic
dbg_sel_idel_cpt	std_logic_vector ( DQS_CNT_WIDTH - 1 downto 0 )
dbg_po_f_stg23_sel	std_logic
dbg_sel_pi_incdec	std_logic
dbg_sel_po_incdec	std_logic
dbg_byte_sel	std_logic_vector ( DQS_CNT_WIDTH downto 0 )
dbg_pi_f_inc	std_logic
dbg_po_f_inc	std_logic
dbg_pi_f_dec	std_logic
dbg_po_f_dec	std_logic
dbg_pi_counter_read_val	std_logic_vector ( 5 downto 0 )
dbg_po_counter_read_val	std_logic_vector ( 8 downto 0 )
dbg_cpt_tap_cnt	std_logic_vector ( 6 * DQS_WIDTH * RANKS - 1 downto 0 )
dbg_dq_idelay_tap_cnt	std_logic_vector ( 5 * DQS_WIDTH * RANKS - 1 downto 0 )
dbg_calib_top	std_logic_vector ( 255 downto 0 )
dbg_cpt_first_edge_cnt	std_logic_vector ( 6 * DQS_WIDTH * RANKS - 1 downto 0 )
dbg_cpt_second_edge_cnt	std_logic_vector ( 6 * DQS_WIDTH * RANKS - 1 downto 0 )
dbg_rd_data_offset	std_logic_vector ( 6 * RANKS - 1 downto 0 )
dbg_phy_rdlvl	std_logic_vector ( 255 downto 0 )
dbg_phy_wrcal	std_logic_vector ( 99 downto 0 )
dbg_final_po_fine_tap_cnt	std_logic_vector ( 6 * DQS_WIDTH - 1 downto 0 )
dbg_final_po_coarse_tap_cnt	std_logic_vector ( 3 * DQS_WIDTH - 1 downto 0 )
dbg_phy_wrlvl	std_logic_vector ( 255 downto 0 )
dbg_phy_init	std_logic_vector ( 255 downto 0 )
dbg_prbs_rdlvl	std_logic_vector ( 255 downto 0 )
dbg_dqs_found_cal	std_logic_vector ( 255 downto 0 )
dbg_pi_phaselock_start	std_logic
dbg_pi_phaselocked_done	std_logic
dbg_pi_phaselock_err	std_logic
dbg_pi_dqsfound_start	std_logic
dbg_pi_dqsfound_done	std_logic
dbg_pi_dqsfound_err	std_logic
dbg_wrcal_start	std_logic
dbg_wrcal_done	std_logic
dbg_wrcal_err	std_logic
dbg_pi_dqs_found_lanes_phy4lanes	std_logic_vector ( 11 downto 0 )
dbg_pi_phase_locked_phy4lanes	std_logic_vector ( 11 downto 0 )
dbg_oclkdelay_calib_start	std_logic
dbg_oclkdelay_calib_done	std_logic
dbg_phy_oclkdelay_cal	std_logic_vector ( 255 downto 0 )
dbg_oclkdelay_rd_data	std_logic_vector ( DRAM_WIDTH * 16 - 1 downto 0 )
dbg_rd_data_edge_detect	std_logic_vector ( DQS_WIDTH - 1 downto 0 )
dbg_rddata	std_logic_vector ( 2 * nCK_PER_CLK * DQ_WIDTH - 1 downto 0 )
dbg_rddata_valid	std_logic
dbg_rdlvl_done	std_logic_vector ( 1 downto 0 )
dbg_rdlvl_err	std_logic_vector ( 1 downto 0 )
dbg_rdlvl_start	std_logic_vector ( 1 downto 0 )
dbg_wrlvl_fine_tap_cnt	std_logic_vector ( 6 * DQS_WIDTH - 1 downto 0 )
dbg_wrlvl_coarse_tap_cnt	std_logic_vector ( 3 * DQS_WIDTH - 1 downto 0 )
dbg_tap_cnt_during_wrlvl	std_logic_vector ( 5 downto 0 )
dbg_wl_edge_detect_valid	std_logic
dbg_wrlvl_done	std_logic
dbg_wrlvl_err	std_logic
dbg_wrlvl_start	std_logic
dbg_rddata_r	std_logic_vector ( 63 downto 0 )
dbg_rddata_valid_r	std_logic
ocal_tap_cnt	std_logic_vector ( 53 downto 0 )
dbg_dqs	std_logic_vector ( 3 downto 0 )
dbg_bit	std_logic_vector ( 8 downto 0 )
rd_data_edge_detect_r	std_logic_vector ( 8 downto 0 )
wl_po_fine_cnt	std_logic_vector ( 53 downto 0 )
wl_po_coarse_cnt	std_logic_vector ( 26 downto 0 )
dbg_calib_rd_data_offset_1	std_logic_vector ( 6 * RANKS - 1 downto 0 )
dbg_calib_rd_data_offset_2	std_logic_vector ( 6 * RANKS - 1 downto 0 )
dbg_data_offset	std_logic_vector ( 5 downto 0 )
dbg_data_offset_1	std_logic_vector ( 5 downto 0 )
dbg_data_offset_2	std_logic_vector ( 5 downto 0 )
all_zeros	std_logic_vector ( 2 * nCK_PER_CLK - 1 downto 0 ) := ( others = > ' 0 ' )

Instantiations
u_iodelay_ctrl	mig_7series_v1_9_iodelay_ctrl <Entity mig_7series_v1_9_iodelay_ctrl>
u_ddr3_clk_ibuf	mig_7series_v1_9_clk_ibuf <Entity mig_7series_v1_9_clk_ibuf>
u_tempmon	mig_7series_v1_9_tempmon <Entity mig_7series_v1_9_tempmon>
u_ddr3_infrastructure	mig_7series_v1_9_infrastructure <Entity mig_7series_v1_9_infrastructure>
u_memc_ui_top_std	mig_7series_v1_9_memc_ui_top_std <Entity mig_7series_v1_9_memc_ui_top_std>

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Detailed Description

Definition at line 526 of file ddr3_1_9a.vhd.

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The documentation for this class was generated from the following file:

• src/common/DDR/ddr3_1_9_a/ddr3_1_9a.vhd