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AMC13
Firmwares for the different applications of the AMC13 uTCA board made at Boston University
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AMC13
Firmwares for the different applications of the AMC13 uTCA board made at Boston University
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This is the complete list of members for arch_ddr3_1_9a, including all inherited members.
| all_zeros (defined in arch_ddr3_1_9a) | arch_ddr3_1_9a | Signal |
| APP_DATA_WIDTH (defined in arch_ddr3_1_9a) | arch_ddr3_1_9a | Constant |
| app_ecc_multiple_err (defined in arch_ddr3_1_9a) | arch_ddr3_1_9a | Signal |
| APP_MASK_WIDTH (defined in arch_ddr3_1_9a) | arch_ddr3_1_9a | Constant |
| bank_mach_next (defined in arch_ddr3_1_9a) | arch_ddr3_1_9a | Signal |
| BM_CNT_WIDTH (defined in arch_ddr3_1_9a) | arch_ddr3_1_9a | Constant |
| clk (defined in arch_ddr3_1_9a) | arch_ddr3_1_9a | Signal |
| clk_ref (defined in arch_ddr3_1_9a) | arch_ddr3_1_9a | Signal |
| clk_ref_in (defined in arch_ddr3_1_9a) | arch_ddr3_1_9a | Signal |
| clk_ref_n (defined in arch_ddr3_1_9a) | arch_ddr3_1_9a | Signal |
| clk_ref_p (defined in arch_ddr3_1_9a) | arch_ddr3_1_9a | Signal |
| clogb2size, (defined in arch_ddr3_1_9a) | arch_ddr3_1_9a | Function |
| dbg_bit (defined in arch_ddr3_1_9a) | arch_ddr3_1_9a | Signal |
| dbg_byte_sel (defined in arch_ddr3_1_9a) | arch_ddr3_1_9a | Signal |
| dbg_calib_rd_data_offset_1 (defined in arch_ddr3_1_9a) | arch_ddr3_1_9a | Signal |
| dbg_calib_rd_data_offset_2 (defined in arch_ddr3_1_9a) | arch_ddr3_1_9a | Signal |
| dbg_calib_top (defined in arch_ddr3_1_9a) | arch_ddr3_1_9a | Signal |
| dbg_cpt_first_edge_cnt (defined in arch_ddr3_1_9a) | arch_ddr3_1_9a | Signal |
| dbg_cpt_second_edge_cnt (defined in arch_ddr3_1_9a) | arch_ddr3_1_9a | Signal |
| dbg_cpt_tap_cnt (defined in arch_ddr3_1_9a) | arch_ddr3_1_9a | Signal |
| dbg_data_offset (defined in arch_ddr3_1_9a) | arch_ddr3_1_9a | Signal |
| dbg_data_offset_1 (defined in arch_ddr3_1_9a) | arch_ddr3_1_9a | Signal |
| dbg_data_offset_2 (defined in arch_ddr3_1_9a) | arch_ddr3_1_9a | Signal |
| dbg_dq_idelay_tap_cnt (defined in arch_ddr3_1_9a) | arch_ddr3_1_9a | Signal |
| dbg_dqs (defined in arch_ddr3_1_9a) | arch_ddr3_1_9a | Signal |
| dbg_dqs_found_cal (defined in arch_ddr3_1_9a) | arch_ddr3_1_9a | Signal |
| dbg_final_po_coarse_tap_cnt (defined in arch_ddr3_1_9a) | arch_ddr3_1_9a | Signal |
| dbg_final_po_fine_tap_cnt (defined in arch_ddr3_1_9a) | arch_ddr3_1_9a | Signal |
| dbg_idel_down_all (defined in arch_ddr3_1_9a) | arch_ddr3_1_9a | Signal |
| dbg_idel_down_cpt (defined in arch_ddr3_1_9a) | arch_ddr3_1_9a | Signal |
| dbg_idel_up_all (defined in arch_ddr3_1_9a) | arch_ddr3_1_9a | Signal |
| dbg_idel_up_cpt (defined in arch_ddr3_1_9a) | arch_ddr3_1_9a | Signal |
| dbg_oclkdelay_calib_done (defined in arch_ddr3_1_9a) | arch_ddr3_1_9a | Signal |
| dbg_oclkdelay_calib_start (defined in arch_ddr3_1_9a) | arch_ddr3_1_9a | Signal |
| dbg_oclkdelay_rd_data (defined in arch_ddr3_1_9a) | arch_ddr3_1_9a | Signal |
| dbg_phy_init (defined in arch_ddr3_1_9a) | arch_ddr3_1_9a | Signal |
| dbg_phy_oclkdelay_cal (defined in arch_ddr3_1_9a) | arch_ddr3_1_9a | Signal |
| dbg_phy_rdlvl (defined in arch_ddr3_1_9a) | arch_ddr3_1_9a | Signal |
| dbg_phy_wrcal (defined in arch_ddr3_1_9a) | arch_ddr3_1_9a | Signal |
| dbg_phy_wrlvl (defined in arch_ddr3_1_9a) | arch_ddr3_1_9a | Signal |
| dbg_pi_counter_read_val (defined in arch_ddr3_1_9a) | arch_ddr3_1_9a | Signal |
| dbg_pi_dqs_found_lanes_phy4lanes (defined in arch_ddr3_1_9a) | arch_ddr3_1_9a | Signal |
| dbg_pi_dqsfound_done (defined in arch_ddr3_1_9a) | arch_ddr3_1_9a | Signal |
| dbg_pi_dqsfound_err (defined in arch_ddr3_1_9a) | arch_ddr3_1_9a | Signal |
| dbg_pi_dqsfound_start (defined in arch_ddr3_1_9a) | arch_ddr3_1_9a | Signal |
| dbg_pi_f_dec (defined in arch_ddr3_1_9a) | arch_ddr3_1_9a | Signal |
| dbg_pi_f_inc (defined in arch_ddr3_1_9a) | arch_ddr3_1_9a | Signal |
| dbg_pi_phase_locked_phy4lanes (defined in arch_ddr3_1_9a) | arch_ddr3_1_9a | Signal |
| dbg_pi_phaselock_err (defined in arch_ddr3_1_9a) | arch_ddr3_1_9a | Signal |
| dbg_pi_phaselock_start (defined in arch_ddr3_1_9a) | arch_ddr3_1_9a | Signal |
| dbg_pi_phaselocked_done (defined in arch_ddr3_1_9a) | arch_ddr3_1_9a | Signal |
| dbg_po_counter_read_val (defined in arch_ddr3_1_9a) | arch_ddr3_1_9a | Signal |
| dbg_po_f_dec (defined in arch_ddr3_1_9a) | arch_ddr3_1_9a | Signal |
| dbg_po_f_inc (defined in arch_ddr3_1_9a) | arch_ddr3_1_9a | Signal |
| dbg_po_f_stg23_sel (defined in arch_ddr3_1_9a) | arch_ddr3_1_9a | Signal |
| dbg_prbs_rdlvl (defined in arch_ddr3_1_9a) | arch_ddr3_1_9a | Signal |
| dbg_rd_data_edge_detect (defined in arch_ddr3_1_9a) | arch_ddr3_1_9a | Signal |
| dbg_rd_data_offset (defined in arch_ddr3_1_9a) | arch_ddr3_1_9a | Signal |
| dbg_rddata (defined in arch_ddr3_1_9a) | arch_ddr3_1_9a | Signal |
| dbg_rddata_r (defined in arch_ddr3_1_9a) | arch_ddr3_1_9a | Signal |
| dbg_rddata_valid (defined in arch_ddr3_1_9a) | arch_ddr3_1_9a | Signal |
| dbg_rddata_valid_r (defined in arch_ddr3_1_9a) | arch_ddr3_1_9a | Signal |
| dbg_rdlvl_done (defined in arch_ddr3_1_9a) | arch_ddr3_1_9a | Signal |
| dbg_rdlvl_err (defined in arch_ddr3_1_9a) | arch_ddr3_1_9a | Signal |
| dbg_rdlvl_start (defined in arch_ddr3_1_9a) | arch_ddr3_1_9a | Signal |
| dbg_sel_all_idel_cpt (defined in arch_ddr3_1_9a) | arch_ddr3_1_9a | Signal |
| dbg_sel_idel_cpt (defined in arch_ddr3_1_9a) | arch_ddr3_1_9a | Signal |
| dbg_sel_pi_incdec (defined in arch_ddr3_1_9a) | arch_ddr3_1_9a | Signal |
| dbg_sel_po_incdec (defined in arch_ddr3_1_9a) | arch_ddr3_1_9a | Signal |
| dbg_tap_cnt_during_wrlvl (defined in arch_ddr3_1_9a) | arch_ddr3_1_9a | Signal |
| dbg_wl_edge_detect_valid (defined in arch_ddr3_1_9a) | arch_ddr3_1_9a | Signal |
| dbg_wrcal_done (defined in arch_ddr3_1_9a) | arch_ddr3_1_9a | Signal |
| dbg_wrcal_err (defined in arch_ddr3_1_9a) | arch_ddr3_1_9a | Signal |
| dbg_wrcal_start (defined in arch_ddr3_1_9a) | arch_ddr3_1_9a | Signal |
| dbg_wrlvl_coarse_tap_cnt (defined in arch_ddr3_1_9a) | arch_ddr3_1_9a | Signal |
| dbg_wrlvl_done (defined in arch_ddr3_1_9a) | arch_ddr3_1_9a | Signal |
| dbg_wrlvl_err (defined in arch_ddr3_1_9a) | arch_ddr3_1_9a | Signal |
| dbg_wrlvl_fine_tap_cnt (defined in arch_ddr3_1_9a) | arch_ddr3_1_9a | Signal |
| dbg_wrlvl_start (defined in arch_ddr3_1_9a) | arch_ddr3_1_9a | Signal |
| ddr3_parity (defined in arch_ddr3_1_9a) | arch_ddr3_1_9a | Signal |
| device_temp (defined in arch_ddr3_1_9a) | arch_ddr3_1_9a | Signal |
| freq_refclk (defined in arch_ddr3_1_9a) | arch_ddr3_1_9a | Signal |
| init_calib_complete_i (defined in arch_ddr3_1_9a) | arch_ddr3_1_9a | Signal |
| iodelay_ctrl_rdy (defined in arch_ddr3_1_9a) | arch_ddr3_1_9a | Signal |
| mem_refclk (defined in arch_ddr3_1_9a) | arch_ddr3_1_9a | Signal |
| mig_7series_v1_9_clk_ibuf (defined in arch_ddr3_1_9a) | arch_ddr3_1_9a | Component |
| mig_7series_v1_9_infrastructure (defined in arch_ddr3_1_9a) | arch_ddr3_1_9a | Component |
| mig_7series_v1_9_iodelay_ctrl (defined in arch_ddr3_1_9a) | arch_ddr3_1_9a | Component |
| mig_7series_v1_9_memc_ui_top_std (defined in arch_ddr3_1_9a) | arch_ddr3_1_9a | Component |
| mig_7series_v1_9_tempmon (defined in arch_ddr3_1_9a) | arch_ddr3_1_9a | Component |
| mmcm_clk (defined in arch_ddr3_1_9a) | arch_ddr3_1_9a | Signal |
| ocal_tap_cnt (defined in arch_ddr3_1_9a) | arch_ddr3_1_9a | Signal |
| pll_locked (defined in arch_ddr3_1_9a) | arch_ddr3_1_9a | Signal |
| RANK_WIDTH (defined in arch_ddr3_1_9a) | arch_ddr3_1_9a | Constant |
| rd_data_edge_detect_r (defined in arch_ddr3_1_9a) | arch_ddr3_1_9a | Signal |
| ref_dll_lock (defined in arch_ddr3_1_9a) | arch_ddr3_1_9a | Signal |
| rst (defined in arch_ddr3_1_9a) | arch_ddr3_1_9a | Signal |
| rst_phaser_ref (defined in arch_ddr3_1_9a) | arch_ddr3_1_9a | Signal |
| sync_pulse (defined in arch_ddr3_1_9a) | arch_ddr3_1_9a | Signal |
| sys_clk_i (defined in arch_ddr3_1_9a) | arch_ddr3_1_9a | Signal |
| sys_rst_o (defined in arch_ddr3_1_9a) | arch_ddr3_1_9a | Signal |
| TEMP_MON (defined in arch_ddr3_1_9a) | arch_ddr3_1_9a | Function |
| TEMP_MON_EN (defined in arch_ddr3_1_9a) | arch_ddr3_1_9a | Constant |
| tTEMPSAMPLE (defined in arch_ddr3_1_9a) | arch_ddr3_1_9a | Constant |
| wl_po_coarse_cnt (defined in arch_ddr3_1_9a) | arch_ddr3_1_9a | Signal |
| wl_po_fine_cnt (defined in arch_ddr3_1_9a) | arch_ddr3_1_9a | Signal |
| XADC_CLK_PERIOD (defined in arch_ddr3_1_9a) | arch_ddr3_1_9a | Constant |
1.8.1
