AMC13
Firmwares for the different applications of the AMC13 uTCA board made at Boston University
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ddr3_1_9a.vhd
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49 -- ____ ____
50 -- / /\/ /
51 -- /___/ \ / Vendor : Xilinx
52 -- \ \ \/ Version : 1.9
53 -- \ \ Application : MIG
54 -- / / Filename : ddr3_1_9a.vhd
55 -- /___/ /\ Date Last Modified : $Date: 2011/06/02 08:35:03 $
56 -- \ \ / \ Date Created : Wed Feb 01 2012
57 -- \___\/\___\
58 --
59 -- Device : 7 Series
60 -- Design Name : DDR3 SDRAM
61 -- Purpose :
62 -- Top-level module. This module can be instantiated in the
63 -- system and interconnect as shown in example design (example_top module).
64 -- In addition to the memory controller, the module instantiates:
65 -- 1. Clock generation/distribution, reset logic
66 -- 2. IDELAY control block
67 -- 3. Debug logic
68 -- Reference :
69 -- Revision History :
70 --*****************************************************************************
71 
72 library ieee;
73 use ieee.std_logic_1164.all;
74 use ieee.numeric_std.all;
75 
76 
77 entity ddr3_1_9a is
78  generic
79  (
80 
81 
82  --***************************************************************************
83  -- The following parameters refer to width of various ports
84  --***************************************************************************
85  BANK_WIDTH : integer := 3;
86  -- # of memory Bank Address bits.
87  CK_WIDTH : integer := 1;
88  -- # of CK/CK# outputs to memory.
89  COL_WIDTH : integer := 10;
90  -- # of memory Column Address bits.
91  CS_WIDTH : integer := 1;
92  -- # of unique CS outputs to memory.
93  nCS_PER_RANK : integer := 1;
94  -- # of unique CS outputs per rank for phy
95  CKE_WIDTH : integer := 1;
96  -- # of CKE outputs to memory.
97  DATA_BUF_ADDR_WIDTH : integer := 5;
98  DQ_CNT_WIDTH : integer := 5;
99  -- = ceil(log2(DQ_WIDTH))
100  DQ_PER_DM : integer := 8;
101  DM_WIDTH : integer := 4;
102  -- # of DM (data mask)
103  DQ_WIDTH : integer := 32;
104  -- # of DQ (data)
105  DQS_WIDTH : integer := 4;
106  DQS_CNT_WIDTH : integer := 2;
107  -- = ceil(log2(DQS_WIDTH))
108  DRAM_WIDTH : integer := 8;
109  -- # of DQ per DQS
110  ECC : string := "OFF";
111  DATA_WIDTH : integer := 32;
112  ECC_TEST : string := "OFF";
113  PAYLOAD_WIDTH : integer := 32;
114  ECC_WIDTH : integer := 8;
115  MC_ERR_ADDR_WIDTH : integer := 31;
116  MEM_ADDR_ORDER
117  : string := "BANK_ROW_COLUMN";
118 
119 
120  nBANK_MACHS : integer := 4;
121  RANKS : integer := 1;
122  -- # of Ranks.
123  ODT_WIDTH : integer := 1;
124  -- # of ODT outputs to memory.
125  ROW_WIDTH : integer := 14;
126  -- # of memory Row Address bits.
127  ADDR_WIDTH : integer := 28;
128  -- # = RANK_WIDTH + BANK_WIDTH
129  -- + ROW_WIDTH + COL_WIDTH;
130  -- Chip Select is always tied to low for
131  -- single rank devices
132  USE_CS_PORT : integer := 0;
133  -- # = 1, When Chip Select (CS#) output is enabled
134  -- = 0, When Chip Select (CS#) output is disabled
135  -- If CS_N disabled, user must connect
136  -- DRAM CS_N input(s) to ground
137  USE_DM_PORT : integer := 1;
138  -- # = 1, When Data Mask option is enabled
139  -- = 0, When Data Mask option is disbaled
140  -- When Data Mask option is disabled in
141  -- MIG Controller Options page, the logic
142  -- related to Data Mask should not get
143  -- synthesized
144  USE_ODT_PORT : integer := 1;
145  -- # = 1, When ODT output is enabled
146  -- = 0, When ODT output is disabled
147  -- Parameter configuration for Dynamic ODT support:
148  -- USE_ODT_PORT = 0, RTT_NOM = "DISABLED", RTT_WR = "60/120".
149  -- This configuration allows to save ODT pin mapping from FPGA.
150  -- The user can tie the ODT input of DRAM to HIGH.
151  PHY_CONTROL_MASTER_BANK : integer := 1;
152  -- The bank index where master PHY_CONTROL resides,
153  -- equal to the PLL residing bank
154  MEM_DENSITY : string := "2Gb";
155  -- Indicates the density of the Memory part
156  -- Added for the sake of Vivado simulations
157  MEM_SPEEDGRADE : string := "107E";
158  -- Indicates the Speed grade of Memory Part
159  -- Added for the sake of Vivado simulations
160  MEM_DEVICE_WIDTH : integer := 16;
161  -- Indicates the device width of the Memory Part
162  -- Added for the sake of Vivado simulations
163 
164  --***************************************************************************
165  -- The following parameters are mode register settings
166  --***************************************************************************
167  AL : string := "0";
168  -- DDR3 SDRAM:
169  -- Additive Latency (Mode Register 1).
170  -- # = "0", "CL-1", "CL-2".
171  -- DDR2 SDRAM:
172  -- Additive Latency (Extended Mode Register).
173  nAL : integer := 0;
174  -- # Additive Latency in number of clock
175  -- cycles.
176  BURST_MODE : string := "8";
177  -- DDR3 SDRAM:
178  -- Burst Length (Mode Register 0).
179  -- # = "8", "4", "OTF".
180  -- DDR2 SDRAM:
181  -- Burst Length (Mode Register).
182  -- # = "8", "4".
183  BURST_TYPE : string := "SEQ";
184  -- DDR3 SDRAM: Burst Type (Mode Register 0).
185  -- DDR2 SDRAM: Burst Type (Mode Register).
186  -- # = "SEQ" - (Sequential),
187  -- = "INT" - (Interleaved).
188  CL : integer := 13;
189  -- in number of clock cycles
190  -- DDR3 SDRAM: CAS Latency (Mode Register 0).
191  -- DDR2 SDRAM: CAS Latency (Mode Register).
192  CWL : integer := 9;
193  -- in number of clock cycles
194  -- DDR3 SDRAM: CAS Write Latency (Mode Register 2).
195  -- DDR2 SDRAM: Can be ignored
196  OUTPUT_DRV : string := "LOW";
197  -- Output Driver Impedance Control (Mode Register 1).
198  -- # = "HIGH" - RZQ/7,
199  -- = "LOW" - RZQ/6.
200  RTT_NOM : string := "60";
201  -- RTT_NOM (ODT) (Mode Register 1).
202  -- = "120" - RZQ/2,
203  -- = "60" - RZQ/4,
204  -- = "40" - RZQ/6.
205  RTT_WR : string := "OFF";
206  -- RTT_WR (ODT) (Mode Register 2).
207  -- # = "OFF" - Dynamic ODT off,
208  -- = "120" - RZQ/2,
209  -- = "60" - RZQ/4,
210  ADDR_CMD_MODE : string := "1T" ;
211  -- # = "1T", "2T".
212  REG_CTRL : string := "OFF";
213  -- # = "ON" - RDIMMs,
214  -- = "OFF" - Components, SODIMMs, UDIMMs.
215  CA_MIRROR : string := "OFF";
216  -- C/A mirror opt for DDR3 dual rank
217 
218  --***************************************************************************
219  -- The following parameters are multiplier and divisor factors for PLLE2.
220  -- Based on the selected design frequency these parameters vary.
221  --***************************************************************************
222  CLKIN_PERIOD : integer := 4288;
223  -- Input Clock Period
224  CLKFBOUT_MULT : integer := 8;
225  -- write PLL VCO multiplier
226  DIVCLK_DIVIDE : integer := 1;
227  -- write PLL VCO divisor
228  CLKOUT0_PHASE : real := 337.5;
229  -- Phase for PLL output clock (CLKOUT0)
230  CLKOUT0_DIVIDE : integer := 2;
231  -- VCO output divisor for PLL output clock (CLKOUT0)
232  CLKOUT1_DIVIDE : integer := 2;
233  -- VCO output divisor for PLL output clock (CLKOUT1)
234  CLKOUT2_DIVIDE : integer := 32;
235  -- VCO output divisor for PLL output clock (CLKOUT2)
236  CLKOUT3_DIVIDE : integer := 8;
237  -- VCO output divisor for PLL output clock (CLKOUT3)
238 
239  --***************************************************************************
240  -- Memory Timing Parameters. These parameters varies based on the selected
241  -- memory part.
242  --***************************************************************************
243  tCKE : integer := 5000;
244  -- memory tCKE paramter in pS
245  tFAW : integer := 25000;
246  -- memory tRAW paramter in pS.
247  tPRDI : integer := 1000000;
248  -- memory tPRDI paramter in pS.
249  tRAS : integer := 34000;
250  -- memory tRAS paramter in pS.
251  tRCD : integer := 13910;
252  -- memory tRCD paramter in pS.
253  tREFI : integer := 7800000;
254  -- memory tREFI paramter in pS.
255  tRFC : integer := 160000;
256  -- memory tRFC paramter in pS.
257  tRP : integer := 13910;
258  -- memory tRP paramter in pS.
259  tRRD : integer := 5000;
260  -- memory tRRD paramter in pS.
261  tRTP : integer := 7500;
262  -- memory tRTP paramter in pS.
263  tWTR : integer := 7500;
264  -- memory tWTR paramter in pS.
265  tZQI : integer := 128000000;
266  -- memory tZQI paramter in nS.
267  tZQCS : integer := 64;
268  -- memory tZQCS paramter in clock cycles.
269 
270  --***************************************************************************
271  -- Simulation parameters
272  --***************************************************************************
273  SIM_BYPASS_INIT_CAL : string := "OFF";
274  -- # = "OFF" - Complete memory init &
275  -- calibration sequence
276  -- # = "SKIP" - Not supported
277  -- # = "FAST" - Complete memory init & use
278  -- abbreviated calib sequence
279 
280  SIMULATION : string := "FALSE";
281  -- Should be TRUE during design simulations and
282  -- FALSE during implementations
283 
284  --***************************************************************************
285  -- The following parameters varies based on the pin out entered in MIG GUI.
286  -- Do not change any of these parameters directly by editing the RTL.
287  -- Any changes required should be done through GUI and the design regenerated.
288  --***************************************************************************
289  BYTE_LANES_B0 : std_logic_vector(3 downto 0) := "0011";
290  -- Byte lanes used in an IO column.
291  BYTE_LANES_B1 : std_logic_vector(3 downto 0) := "1111";
292  -- Byte lanes used in an IO column.
293  BYTE_LANES_B2 : std_logic_vector(3 downto 0) := "1100";
294  -- Byte lanes used in an IO column.
295  BYTE_LANES_B3 : std_logic_vector(3 downto 0) := "0000";
296  -- Byte lanes used in an IO column.
297  BYTE_LANES_B4 : std_logic_vector(3 downto 0) := "0000";
298  -- Byte lanes used in an IO column.
299  DATA_CTL_B0 : std_logic_vector(3 downto 0) := "0011";
300  -- Indicates Byte lane is data byte lane
301  -- or control Byte lane. '1' in a bit
302  -- position indicates a data byte lane and
303  -- a '0' indicates a control byte lane
304  DATA_CTL_B1 : std_logic_vector(3 downto 0) := "0000";
305  -- Indicates Byte lane is data byte lane
306  -- or control Byte lane. '1' in a bit
307  -- position indicates a data byte lane and
308  -- a '0' indicates a control byte lane
309  DATA_CTL_B2 : std_logic_vector(3 downto 0) := "1100";
310  -- Indicates Byte lane is data byte lane
311  -- or control Byte lane. '1' in a bit
312  -- position indicates a data byte lane and
313  -- a '0' indicates a control byte lane
314  DATA_CTL_B3 : std_logic_vector(3 downto 0) := "0000";
315  -- Indicates Byte lane is data byte lane
316  -- or control Byte lane. '1' in a bit
317  -- position indicates a data byte lane and
318  -- a '0' indicates a control byte lane
319  DATA_CTL_B4 : std_logic_vector(3 downto 0) := "0000";
320  -- Indicates Byte lane is data byte lane
321  -- or control Byte lane. '1' in a bit
322  -- position indicates a data byte lane and
323  -- a '0' indicates a control byte lane
324  PHY_0_BITLANES : std_logic_vector(47 downto 0) := X"00000037F2FF";
325  PHY_1_BITLANES : std_logic_vector(47 downto 0) := X"000004F3FDFF";
326  PHY_2_BITLANES : std_logic_vector(47 downto 0) := X"3FE3DF000000";
327 
328  -- control/address/data pin mapping parameters
329  CK_BYTE_MAP
330  : std_logic_vector(143 downto 0) := X"000000000000000000000000000000000013";
331  ADDR_MAP
332  : std_logic_vector(191 downto 0) := X"00000010610710A10210510811B10110010B111113122119";
333  BANK_MAP : std_logic_vector(35 downto 0) := X"11510311A";
334  CAS_MAP : std_logic_vector(11 downto 0) := X"118";
335  CKE_ODT_BYTE_MAP : std_logic_vector(7 downto 0) := X"00";
336  CKE_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000104";
337  ODT_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000112";
338  CS_MAP : std_logic_vector(119 downto 0) := X"000000000000000000000000000000";
339  PARITY_MAP : std_logic_vector(11 downto 0) := X"000";
340  RAS_MAP : std_logic_vector(11 downto 0) := X"110";
341  WE_MAP : std_logic_vector(11 downto 0) := X"114";
342  DQS_BYTE_MAP
343  : std_logic_vector(143 downto 0) := X"000000000000000000000000000000012223";
344  DATA0_MAP : std_logic_vector(95 downto 0) := X"232235237234238231236233";
345  DATA1_MAP : std_logic_vector(95 downto 0) := X"220226221224223227228229";
346  DATA2_MAP : std_logic_vector(95 downto 0) := X"012015013016018011014019";
347  DATA3_MAP : std_logic_vector(95 downto 0) := X"000002001009006003005007";
348  DATA4_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
349  DATA5_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
350  DATA6_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
351  DATA7_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
352  DATA8_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
353  DATA9_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
354  DATA10_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
355  DATA11_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
356  DATA12_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
357  DATA13_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
358  DATA14_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
359  DATA15_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
360  DATA16_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
361  DATA17_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
362  MASK0_MAP : std_logic_vector(107 downto 0) := X"000000000000000004010222239";
363  MASK1_MAP : std_logic_vector(107 downto 0) := X"000000000000000000000000000";
364 
365  SLOT_0_CONFIG : std_logic_vector(7 downto 0) := "00000001";
366  -- Mapping of Ranks.
367  SLOT_1_CONFIG : std_logic_vector(7 downto 0) := "00000000";
368  -- Mapping of Ranks.
369 
370  --***************************************************************************
371  -- IODELAY and PHY related parameters
372  --***************************************************************************
373  IODELAY_HP_MODE : string := "ON";
374  -- to phy_top
375  IBUF_LPWR_MODE : string := "OFF";
376  -- to phy_top
377  DATA_IO_IDLE_PWRDWN : string := "ON";
378  -- # = "ON", "OFF"
379  BANK_TYPE : string := "HP_IO";
380  -- # = "HP_IO", "HPL_IO", "HR_IO", "HRL_IO"
381  DATA_IO_PRIM_TYPE : string := "HP_LP";
382  -- # = "HP_LP", "HR_LP", "DEFAULT"
383  CKE_ODT_AUX : string := "FALSE";
384  USER_REFRESH : string := "OFF";
385  WRLVL : string := "ON";
386  -- # = "ON" - DDR3 SDRAM
387  -- = "OFF" - DDR2 SDRAM.
388  ORDERING : string := "NORM";
389  -- # = "NORM", "STRICT", "RELAXED".
390  CALIB_ROW_ADD : std_logic_vector(15 downto 0) := X"0000";
391  -- Calibration row address will be used for
392  -- calibration read and write operations
393  CALIB_COL_ADD : std_logic_vector(11 downto 0) := X"000";
394  -- Calibration column address will be used for
395  -- calibration read and write operations
396  CALIB_BA_ADD : std_logic_vector(2 downto 0) := "000";
397  -- Calibration bank address will be used for
398  -- calibration read and write operations
399  TCQ : integer := 100;
400  IODELAY_GRP : string := "IODELAY_MIG";
401  -- It is associated to a set of IODELAYs with
402  -- an IDELAYCTRL that have same IODELAY CONTROLLER
403  -- clock frequency.
404  SYSCLK_TYPE : string := "DIFFERENTIAL";
405  -- System clock type DIFFERENTIAL, SINGLE_ENDED,
406  -- NO_BUFFER
407  REFCLK_TYPE : string := "NO_BUFFER";
408  -- Reference clock type DIFFERENTIAL, SINGLE_ENDED
409  -- NO_BUFFER, USE_SYSTEM_CLOCK
410  SYS_RST_PORT : string := "FALSE";
411  -- "TRUE" - if pin is selected for sys_rst
412  -- and IBUF will be instantiated.
413  -- "FALSE" - if pin is not selected for sys_rst
414 
415  CMD_PIPE_PLUS1 : string := "ON";
416  -- add pipeline stage between MC and PHY
417  DRAM_TYPE : string := "DDR3";
418  CAL_WIDTH : string := "HALF";
419  STARVE_LIMIT : integer := 2;
420  -- # = 2,3,4.
421 
422  --***************************************************************************
423  -- Referece clock frequency parameters
424  --***************************************************************************
425  REFCLK_FREQ : real := 200.0;
426  -- IODELAYCTRL reference clock frequency
427  DIFF_TERM_REFCLK : string := "TRUE";
428  -- Differential Termination for idelay
429  -- reference clock input pins
430  --***************************************************************************
431  -- System clock frequency parameters
432  --***************************************************************************
433  tCK : integer := 1072;
434  -- memory tCK paramter.
435  -- # = Clock Period in pS.
436  nCK_PER_CLK : integer := 4;
437  -- # of memory CKs per fabric CLK
438  DIFF_TERM_SYSCLK : string := "FALSE";
439  -- Differential Termination for System
440  -- clock input pins
441 
442  --***************************************************************************
443  -- Debug parameters
444  --***************************************************************************
445  DEBUG_PORT : string := "OFF";
446  -- # = "ON" Enable debug signals/controls.
447  -- = "OFF" Disable debug signals/controls.
448 
449  --***************************************************************************
450  -- Temparature monitor parameter
451  --***************************************************************************
452  TEMP_MON_CONTROL : string := "EXTERNAL";
453  -- # = "INTERNAL", "EXTERNAL"
454 
455  RST_ACT_LOW : integer := 0
456  -- =1 for active low reset,
457  -- =0 for active high.
458  );
459  port
460  (
461 
462  -- Inouts
463  ddr3_dq : inout std_logic_vector(DQ_WIDTH-1 downto 0);
464  ddr3_dqs_p : inout std_logic_vector(DQS_WIDTH-1 downto 0);
465  ddr3_dqs_n : inout std_logic_vector(DQS_WIDTH-1 downto 0);
466 
467  -- Outputs
468  ddr3_addr : out std_logic_vector(ROW_WIDTH-1 downto 0);
469  ddr3_ba : out std_logic_vector(BANK_WIDTH-1 downto 0);
470  ddr3_ras_n : out std_logic;
471  ddr3_cas_n : out std_logic;
472  ddr3_we_n : out std_logic;
473  ddr3_reset_n : out std_logic;
474  ddr3_ck_p : out std_logic_vector(CK_WIDTH-1 downto 0);
475  ddr3_ck_n : out std_logic_vector(CK_WIDTH-1 downto 0);
476  ddr3_cke : out std_logic_vector(CKE_WIDTH-1 downto 0);
477 
478  ddr3_dm : out std_logic_vector(DM_WIDTH-1 downto 0);
479  ddr3_odt : out std_logic_vector(ODT_WIDTH-1 downto 0);
480 
481  -- Inputs
482  -- Differential system clocks
483  sys_clk_p : in std_logic;
484  sys_clk_n : in std_logic;
485  -- Single-ended iodelayctrl clk (reference clock)
486  clk_ref_i : in std_logic;
487  -- user interface signals
488  app_addr : in std_logic_vector(ADDR_WIDTH-1 downto 0);
489  app_cmd : in std_logic_vector(2 downto 0);
490  app_en : in std_logic;
491  app_wdf_data : in std_logic_vector((nCK_PER_CLK*2*PAYLOAD_WIDTH)-1 downto 0);
492  app_wdf_end : in std_logic;
493  app_wdf_mask : in std_logic_vector((nCK_PER_CLK*2*PAYLOAD_WIDTH)/8-1 downto 0) ;
494  app_wdf_wren : in std_logic;
495  app_rd_data : out std_logic_vector((nCK_PER_CLK*2*PAYLOAD_WIDTH)-1 downto 0);
496  app_rd_data_end : out std_logic;
497  app_rd_data_valid : out std_logic;
498  app_rdy : out std_logic;
499  app_wdf_rdy : out std_logic;
500  app_sr_req : in std_logic;
501  app_sr_active : out std_logic;
502  app_ref_req : in std_logic;
503  app_ref_ack : out std_logic;
504  app_zq_req : in std_logic;
505  app_zq_ack : out std_logic;
506  ui_clk : out std_logic;
507  ui_clk_sync_rst : out std_logic;
508 
509 
510 
511  init_calib_complete : out std_logic;
512  device_temp_i : in std_logic_vector(11 downto 0);
513  -- The 12 MSB bits of the temperature sensor transfer
514  -- function need to be connected to this port. This port
515  -- will be synchronized w.r.t. to fabric clock internally.
516 
517 
518  -- System reset - Default polarity of sys_rst pin is Active Low.
519  -- System reset polarity will change based on the option
520  -- selected in GUI.
521  sys_rst : in std_logic
522  );
523 
524 end entity ddr3_1_9a;
525 
526 architecture arch_ddr3_1_9a of ddr3_1_9a is
527 
528 
529  -- clogb2 function - ceiling of log base 2
530  function clogb2 (size : integer) return integer is
531  variable base : integer := 1;
532  variable inp : integer := 0;
533  begin
534  inp := size - 1;
535  while (inp > 1) loop
536  inp := inp/2 ;
537  base := base + 1;
538  end loop;
539  return base;
540  end function;
541  function TEMP_MON return string is
542  begin
543  if(SIMULATION = "FALSE") then
544  return "ON";
545  else
546  return "OFF";
547  end if;
548  end function;
549 
550 
551 
552  constant BM_CNT_WIDTH : integer := clogb2(nBANK_MACHS);
553  constant RANK_WIDTH : integer := clogb2(RANKS);
554 
555  constant APP_DATA_WIDTH : integer := 2 * nCK_PER_CLK * PAYLOAD_WIDTH;
556  constant APP_MASK_WIDTH : integer := APP_DATA_WIDTH / 8;
557  constant TEMP_MON_EN : string := TEMP_MON;
558  -- Enable or disable the temp monitor module
559  constant tTEMPSAMPLE : integer := 10000000; -- sample every 10 us
560  constant XADC_CLK_PERIOD : integer := 5000; -- Use 200 MHz IODELAYCTRL clock
561 
562 
563 
564 
565 
566 
567  component mig_7series_v1_9_iodelay_ctrl is
568  generic(
569  TCQ : integer;
570  IODELAY_GRP : string;
571  REFCLK_TYPE : string;
572  SYSCLK_TYPE : string;
573  SYS_RST_PORT : string;
574  RST_ACT_LOW : integer;
575  DIFF_TERM_REFCLK : string
576  );
577  port (
578  clk_ref_p : in std_logic;
579  clk_ref_n : in std_logic;
580  clk_ref_i : in std_logic;
581  sys_rst : in std_logic;
582  clk_ref : out std_logic;
583  sys_rst_o : out std_logic;
584  iodelay_ctrl_rdy : out std_logic
585  );
586  end component mig_7series_v1_9_iodelay_ctrl;
587 
588  component mig_7series_v1_9_clk_ibuf is
589  generic (
590  SYSCLK_TYPE : string;
591  DIFF_TERM_SYSCLK : string
592  );
593  port (
594  sys_clk_p : in std_logic;
595  sys_clk_n : in std_logic;
596  sys_clk_i : in std_logic;
597  mmcm_clk : out std_logic
598  );
599  end component mig_7series_v1_9_clk_ibuf;
600 
601  component mig_7series_v1_9_infrastructure is
602  generic (
603  TCQ : integer;
604  CLKIN_PERIOD : integer;
605  nCK_PER_CLK : integer;
606  SYSCLK_TYPE : string;
607  CLKFBOUT_MULT : integer;
608  DIVCLK_DIVIDE : integer;
609  CLKOUT0_PHASE : real;
610  CLKOUT0_DIVIDE : integer;
611  CLKOUT1_DIVIDE : integer;
612  CLKOUT2_DIVIDE : integer;
613  CLKOUT3_DIVIDE : integer;
614  RST_ACT_LOW : integer
615  );
616  port (
617  mmcm_clk : in std_logic;
618  sys_rst : in std_logic;
619  iodelay_ctrl_rdy : in std_logic;
620  clk : out std_logic;
621  mem_refclk : out std_logic;
622  freq_refclk : out std_logic;
623  sync_pulse : out std_logic;
624  auxout_clk : out std_logic;
625  ui_addn_clk_0 : out std_logic;
626  ui_addn_clk_1 : out std_logic;
627  ui_addn_clk_2 : out std_logic;
628  ui_addn_clk_3 : out std_logic;
629  ui_addn_clk_4 : out std_logic;
630  pll_locked : out std_logic;
631  mmcm_locked : out std_logic;
632  rstdiv0 : out std_logic;
633  rst_phaser_ref : out std_logic;
634  ref_dll_lock : in std_logic
635  );
636  end component mig_7series_v1_9_infrastructure;
637 
638  component mig_7series_v1_9_tempmon is
639  generic (
640  TCQ : integer;
641  TEMP_MON_CONTROL : string;
642  XADC_CLK_PERIOD : integer;
643  tTEMPSAMPLE : integer
644  );
645  port (
646  clk : in std_logic;
647  xadc_clk : in std_logic;
648  rst : in std_logic;
649  device_temp_i : in std_logic_vector(11 downto 0);
650  device_temp : out std_logic_vector(11 downto 0)
651  );
652  end component mig_7series_v1_9_tempmon;
653 
654  component mig_7series_v1_9_memc_ui_top_std is
655  generic (
656  TCQ : integer;
657  PAYLOAD_WIDTH : integer;
658  BANK_WIDTH : integer;
659  BM_CNT_WIDTH : integer;
660  CK_WIDTH : integer;
661  COL_WIDTH : integer;
662  CS_WIDTH : integer;
663  nCS_PER_RANK : integer;
664  CKE_WIDTH : integer;
665  DATA_BUF_ADDR_WIDTH : integer;
666  DQ_CNT_WIDTH : integer;
667  DM_WIDTH : integer;
668  DQ_WIDTH : integer;
669  DQS_WIDTH : integer;
670  DQS_CNT_WIDTH : integer;
671  DRAM_WIDTH : integer;
672  ECC : string;
673  nBANK_MACHS : integer;
674  DATA_WIDTH : integer;
675  ECC_TEST : string;
676  ECC_WIDTH : integer;
677  MC_ERR_ADDR_WIDTH : integer;
678  RANKS : integer;
679  ODT_WIDTH : integer;
680  ROW_WIDTH : integer;
681  ADDR_WIDTH : integer;
682  APP_DATA_WIDTH : integer;
683  APP_MASK_WIDTH : integer;
684  USE_CS_PORT : integer;
685  USE_DM_PORT : integer;
686  USE_ODT_PORT : integer;
687  MASTER_PHY_CTL : integer;
688  AL : string;
689  nAL : integer;
690  BURST_MODE : string;
691  BURST_TYPE : string;
692  CL : integer;
693  CWL : integer;
694  OUTPUT_DRV : string;
695  RTT_NOM : string;
696  RTT_WR : string;
697  ADDR_CMD_MODE : string;
698  REG_CTRL : string;
699  CA_MIRROR : string;
700  tCKE : integer;
701  tFAW : integer;
702  tPRDI : integer;
703  tRAS : integer;
704  tRCD : integer;
705  tREFI : integer;
706  tRFC : integer;
707  tRP : integer;
708  tRRD : integer;
709  tRTP : integer;
710  tWTR : integer;
711  tZQI : integer;
712  tZQCS : integer;
713  SIM_BYPASS_INIT_CAL : string;
714  BYTE_LANES_B0 : std_logic_vector(3 downto 0);
715  BYTE_LANES_B1 : std_logic_vector(3 downto 0);
716  BYTE_LANES_B2 : std_logic_vector(3 downto 0);
717  BYTE_LANES_B3 : std_logic_vector(3 downto 0);
718  BYTE_LANES_B4 : std_logic_vector(3 downto 0);
719  DATA_CTL_B0 : std_logic_vector(3 downto 0);
720  DATA_CTL_B1 : std_logic_vector(3 downto 0);
721  DATA_CTL_B2 : std_logic_vector(3 downto 0);
722  DATA_CTL_B3 : std_logic_vector(3 downto 0);
723  DATA_CTL_B4 : std_logic_vector(3 downto 0);
724  PHY_0_BITLANES : std_logic_vector(47 downto 0);
725  PHY_1_BITLANES : std_logic_vector(47 downto 0);
726  PHY_2_BITLANES : std_logic_vector(47 downto 0);
727  CK_BYTE_MAP : std_logic_vector(143 downto 0);
728  ADDR_MAP : std_logic_vector(191 downto 0);
729  BANK_MAP : std_logic_vector(35 downto 0);
730  CAS_MAP : std_logic_vector(11 downto 0);
731  CKE_ODT_BYTE_MAP : std_logic_vector(7 downto 0);
732  CKE_MAP : std_logic_vector(95 downto 0);
733  ODT_MAP : std_logic_vector(95 downto 0);
734  CS_MAP : std_logic_vector(119 downto 0);
735  PARITY_MAP : std_logic_vector(11 downto 0);
736  RAS_MAP : std_logic_vector(11 downto 0);
737  WE_MAP : std_logic_vector(11 downto 0);
738  DQS_BYTE_MAP : std_logic_vector(143 downto 0);
739  DATA0_MAP : std_logic_vector(95 downto 0);
740  DATA1_MAP : std_logic_vector(95 downto 0);
741  DATA2_MAP : std_logic_vector(95 downto 0);
742  DATA3_MAP : std_logic_vector(95 downto 0);
743  DATA4_MAP : std_logic_vector(95 downto 0);
744  DATA5_MAP : std_logic_vector(95 downto 0);
745  DATA6_MAP : std_logic_vector(95 downto 0);
746  DATA7_MAP : std_logic_vector(95 downto 0);
747  DATA8_MAP : std_logic_vector(95 downto 0);
748  DATA9_MAP : std_logic_vector(95 downto 0);
749  DATA10_MAP : std_logic_vector(95 downto 0);
750  DATA11_MAP : std_logic_vector(95 downto 0);
751  DATA12_MAP : std_logic_vector(95 downto 0);
752  DATA13_MAP : std_logic_vector(95 downto 0);
753  DATA14_MAP : std_logic_vector(95 downto 0);
754  DATA15_MAP : std_logic_vector(95 downto 0);
755  DATA16_MAP : std_logic_vector(95 downto 0);
756  DATA17_MAP : std_logic_vector(95 downto 0);
757  MASK0_MAP : std_logic_vector(107 downto 0);
758  MASK1_MAP : std_logic_vector(107 downto 0);
759  SLOT_0_CONFIG : std_logic_vector(7 downto 0);
760  SLOT_1_CONFIG : std_logic_vector(7 downto 0);
761  MEM_ADDR_ORDER : string;
762  IODELAY_HP_MODE : string;
763  IBUF_LPWR_MODE : string;
764  DATA_IO_IDLE_PWRDWN : string;
765  BANK_TYPE : string;
766  DATA_IO_PRIM_TYPE : string;
767  CKE_ODT_AUX : string;
768  USER_REFRESH : string;
769  TEMP_MON_EN : string;
770  WRLVL : string;
771  ORDERING : string;
772  CALIB_ROW_ADD : std_logic_vector(15 downto 0);
773  CALIB_COL_ADD : std_logic_vector(11 downto 0);
774  CALIB_BA_ADD : std_logic_vector(2 downto 0);
775  IODELAY_GRP : string;
776  CMD_PIPE_PLUS1 : string;
777  DRAM_TYPE : string;
778  CAL_WIDTH : string;
779  RANK_WIDTH : integer;
780  STARVE_LIMIT : integer;
781  REFCLK_FREQ : real;
782  tCK : integer;
783  nCK_PER_CLK : integer;
784  DEBUG_PORT : string
785  );
786  port (
787  clk : in std_logic;
788  clk_ref : in std_logic;
789  mem_refclk : in std_logic;
790  freq_refclk : in std_logic;
791  pll_lock : in std_logic;
792  sync_pulse : in std_logic;
793  rst : in std_logic;
794  rst_phaser_ref : in std_logic;
795  ref_dll_lock : out std_logic;
796 
797  ddr_dq : inout std_logic_vector(DQ_WIDTH-1 downto 0);
798  ddr_dqs_n : inout std_logic_vector(DQS_WIDTH-1 downto 0);
799  ddr_dqs : inout std_logic_vector(DQS_WIDTH-1 downto 0);
800  ddr_addr : out std_logic_vector(ROW_WIDTH-1 downto 0);
801  ddr_ba : out std_logic_vector(BANK_WIDTH-1 downto 0);
802  ddr_cas_n : out std_logic;
803  ddr_ck_n : out std_logic_vector(CK_WIDTH-1 downto 0);
804  ddr_ck : out std_logic_vector(CK_WIDTH-1 downto 0);
805  ddr_cke : out std_logic_vector(CKE_WIDTH-1 downto 0);
806  ddr_cs_n : out std_logic_vector((CS_WIDTH*nCS_PER_RANK)-1 downto 0);
807  ddr_dm : out std_logic_vector(DM_WIDTH-1 downto 0);
808  ddr_odt : out std_logic_vector(ODT_WIDTH-1 downto 0);
809  ddr_ras_n : out std_logic;
810  ddr_reset_n : out std_logic;
811  ddr_parity : out std_logic;
812  ddr_we_n : out std_logic;
813 
814  bank_mach_next : out std_logic_vector(BM_CNT_WIDTH-1 downto 0);
815 
816  app_addr : in std_logic_vector(ADDR_WIDTH-1 downto 0);
817  app_cmd : in std_logic_vector(2 downto 0);
818  app_en : in std_logic;
819  app_hi_pri : in std_logic;
820  app_wdf_data : in std_logic_vector((nCK_PER_CLK*2*PAYLOAD_WIDTH)-1 downto 0);
821  app_wdf_end : in std_logic;
822  app_wdf_mask : in std_logic_vector((nCK_PER_CLK*2*PAYLOAD_WIDTH)/8-1 downto 0);
823  app_wdf_wren : in std_logic;
824  app_correct_en_i : in std_logic;
825  app_raw_not_ecc : in std_logic_vector(2*nCK_PER_CLK-1 downto 0);
826  app_ecc_multiple_err : out std_logic_vector(2*nCK_PER_CLK-1 downto 0);
827  app_rd_data : out std_logic_vector((nCK_PER_CLK*2*PAYLOAD_WIDTH)-1 downto 0);
828  app_rd_data_end : out std_logic;
829  app_rd_data_valid : out std_logic;
830  app_rdy : out std_logic;
831  app_wdf_rdy : out std_logic;
832  app_sr_req : in std_logic;
833  app_sr_active : out std_logic;
834  app_ref_req : in std_logic;
835  app_ref_ack : out std_logic;
836  app_zq_req : in std_logic;
837  app_zq_ack : out std_logic;
838 
839  device_temp : in std_logic_vector(11 downto 0);
840 
841  dbg_idel_down_all : in std_logic;
842  dbg_idel_down_cpt : in std_logic;
843  dbg_idel_up_all : in std_logic;
844  dbg_idel_up_cpt : in std_logic;
845  dbg_sel_all_idel_cpt : in std_logic;
846  dbg_sel_idel_cpt : in std_logic_vector(DQS_CNT_WIDTH-1 downto 0);
847  dbg_cpt_first_edge_cnt : out std_logic_vector(6*DQS_WIDTH*RANKS-1 downto 0);
848  dbg_cpt_second_edge_cnt : out std_logic_vector(6*DQS_WIDTH*RANKS-1 downto 0);
849  dbg_rd_data_edge_detect : out std_logic_vector(DQS_WIDTH-1 downto 0);
850  dbg_rddata : out std_logic_vector(2*nCK_PER_CLK*DQ_WIDTH-1 downto 0);
851  dbg_rdlvl_done : out std_logic_vector(1 downto 0);
852  dbg_rdlvl_err : out std_logic_vector(1 downto 0);
853  dbg_rdlvl_start : out std_logic_vector(1 downto 0);
854  dbg_tap_cnt_during_wrlvl : out std_logic_vector(5 downto 0);
855  dbg_wl_edge_detect_valid : out std_logic;
856  dbg_wrlvl_done : out std_logic;
857  dbg_wrlvl_err : out std_logic;
858  dbg_wrlvl_start : out std_logic;
859  dbg_final_po_fine_tap_cnt : out std_logic_vector(6*DQS_WIDTH-1 downto 0);
860  dbg_final_po_coarse_tap_cnt : out std_logic_vector(3*DQS_WIDTH-1 downto 0);
861  init_calib_complete : out std_logic;
862  dbg_sel_pi_incdec : in std_logic;
863  dbg_sel_po_incdec : in std_logic;
864  dbg_byte_sel : in std_logic_vector(DQS_CNT_WIDTH downto 0);
865  dbg_pi_f_inc : in std_logic;
866  dbg_pi_f_dec : in std_logic;
867  dbg_po_f_inc : in std_logic;
868  dbg_po_f_stg23_sel : in std_logic;
869  dbg_po_f_dec : in std_logic;
870  dbg_cpt_tap_cnt : out std_logic_vector(6*DQS_WIDTH*RANKS-1 downto 0);
871  dbg_dq_idelay_tap_cnt : out std_logic_vector(5*DQS_WIDTH*RANKS-1 downto 0);
872  dbg_rddata_valid : out std_logic;
873  dbg_wrlvl_fine_tap_cnt : out std_logic_vector(6*DQS_WIDTH-1 downto 0);
874  dbg_wrlvl_coarse_tap_cnt : out std_logic_vector(3*DQS_WIDTH-1 downto 0);
875  dbg_rd_data_offset : out std_logic_vector(6*RANKS-1 downto 0);
876  dbg_calib_top : out std_logic_vector(255 downto 0);
877  dbg_phy_wrlvl : out std_logic_vector(255 downto 0);
878  dbg_phy_rdlvl : out std_logic_vector(255 downto 0);
879  dbg_phy_wrcal : out std_logic_vector(99 downto 0);
880  dbg_phy_init : out std_logic_vector(255 downto 0);
881  dbg_prbs_rdlvl : out std_logic_vector(255 downto 0);
882  dbg_dqs_found_cal : out std_logic_vector(255 downto 0);
883  dbg_pi_counter_read_val : out std_logic_vector(5 downto 0);
884  dbg_po_counter_read_val : out std_logic_vector(8 downto 0);
885  dbg_pi_phaselock_start : out std_logic;
886  dbg_pi_phaselocked_done : out std_logic;
887  dbg_pi_phaselock_err : out std_logic;
888  dbg_pi_dqsfound_start : out std_logic;
889  dbg_pi_dqsfound_done : out std_logic;
890  dbg_pi_dqsfound_err : out std_logic;
891  dbg_wrcal_start : out std_logic;
892  dbg_wrcal_done : out std_logic;
893  dbg_wrcal_err : out std_logic;
894  dbg_pi_dqs_found_lanes_phy4lanes : out std_logic_vector(11 downto 0);
895  dbg_pi_phase_locked_phy4lanes : out std_logic_vector(11 downto 0);
896  dbg_calib_rd_data_offset_1 : out std_logic_vector(6*RANKS-1 downto 0);
897  dbg_calib_rd_data_offset_2 : out std_logic_vector(6*RANKS-1 downto 0);
898  dbg_data_offset : out std_logic_vector(5 downto 0);
899  dbg_data_offset_1 : out std_logic_vector(5 downto 0);
900  dbg_data_offset_2 : out std_logic_vector(5 downto 0);
901  dbg_oclkdelay_calib_start : out std_logic;
902  dbg_oclkdelay_calib_done : out std_logic;
903  dbg_phy_oclkdelay_cal : out std_logic_vector(255 downto 0);
904  dbg_oclkdelay_rd_data : out std_logic_vector(DRAM_WIDTH*16-1 downto 0)
905  );
906  end component mig_7series_v1_9_memc_ui_top_std;
907 
908 
909  -- Signal declarations
910 
911  signal bank_mach_next : std_logic_vector(BM_CNT_WIDTH-1 downto 0);
912  signal clk : std_logic;
913  signal clk_ref : std_logic;
914  signal iodelay_ctrl_rdy : std_logic;
915  signal clk_ref_in : std_logic;
916  signal sys_rst_o : std_logic;
917  signal freq_refclk : std_logic;
918  signal mem_refclk : std_logic;
919  signal pll_locked : std_logic;
920  signal sync_pulse : std_logic;
921  signal ref_dll_lock : std_logic;
922  signal rst_phaser_ref : std_logic;
923 
924  signal rst : std_logic;
925 
926  signal app_ecc_multiple_err : std_logic_vector(2*nCK_PER_CLK-1 downto 0);
927  signal ddr3_parity : std_logic;
928 
929  signal init_calib_complete_i : std_logic;
930 
931  signal sys_clk_i : std_logic;
932  signal mmcm_clk : std_logic;
933  signal clk_ref_p : std_logic;
934  signal clk_ref_n : std_logic;
935  signal device_temp : std_logic_vector(11 downto 0);
936 
937  -- Debug port signals
938  signal dbg_idel_down_all : std_logic;
939  signal dbg_idel_down_cpt : std_logic;
940  signal dbg_idel_up_all : std_logic;
941  signal dbg_idel_up_cpt : std_logic;
942  signal dbg_sel_all_idel_cpt : std_logic;
943  signal dbg_sel_idel_cpt : std_logic_vector(DQS_CNT_WIDTH-1 downto 0);
944  signal dbg_po_f_stg23_sel : std_logic;
945  signal dbg_sel_pi_incdec : std_logic;
946  signal dbg_sel_po_incdec : std_logic;
947  signal dbg_byte_sel : std_logic_vector(DQS_CNT_WIDTH downto 0);
948  signal dbg_pi_f_inc : std_logic;
949  signal dbg_po_f_inc : std_logic;
950  signal dbg_pi_f_dec : std_logic;
951  signal dbg_po_f_dec : std_logic;
952  signal dbg_pi_counter_read_val : std_logic_vector(5 downto 0);
953  signal dbg_po_counter_read_val : std_logic_vector(8 downto 0);
954  signal dbg_cpt_tap_cnt : std_logic_vector(6*DQS_WIDTH*RANKS-1 downto 0);
955  signal dbg_dq_idelay_tap_cnt : std_logic_vector(5*DQS_WIDTH*RANKS-1 downto 0);
956  signal dbg_calib_top : std_logic_vector(255 downto 0);
957  signal dbg_cpt_first_edge_cnt : std_logic_vector(6*DQS_WIDTH*RANKS-1 downto 0);
958  signal dbg_cpt_second_edge_cnt : std_logic_vector(6*DQS_WIDTH*RANKS-1 downto 0);
959  signal dbg_rd_data_offset : std_logic_vector(6*RANKS-1 downto 0);
960  signal dbg_phy_rdlvl : std_logic_vector(255 downto 0);
961  signal dbg_phy_wrcal : std_logic_vector(99 downto 0);
962  signal dbg_final_po_fine_tap_cnt : std_logic_vector(6*DQS_WIDTH-1 downto 0);
963  signal dbg_final_po_coarse_tap_cnt : std_logic_vector(3*DQS_WIDTH-1 downto 0);
964  signal dbg_phy_wrlvl : std_logic_vector(255 downto 0);
965  signal dbg_phy_init : std_logic_vector(255 downto 0);
966  signal dbg_prbs_rdlvl : std_logic_vector(255 downto 0);
967  signal dbg_dqs_found_cal : std_logic_vector(255 downto 0);
968  signal dbg_pi_phaselock_start : std_logic;
969  signal dbg_pi_phaselocked_done : std_logic;
970  signal dbg_pi_phaselock_err : std_logic;
971  signal dbg_pi_dqsfound_start : std_logic;
972  signal dbg_pi_dqsfound_done : std_logic;
973  signal dbg_pi_dqsfound_err : std_logic;
974  signal dbg_wrcal_start : std_logic;
975  signal dbg_wrcal_done : std_logic;
976  signal dbg_wrcal_err : std_logic;
977  signal dbg_pi_dqs_found_lanes_phy4lanes : std_logic_vector(11 downto 0);
978  signal dbg_pi_phase_locked_phy4lanes : std_logic_vector(11 downto 0);
979  signal dbg_oclkdelay_calib_start : std_logic;
980  signal dbg_oclkdelay_calib_done : std_logic;
981  signal dbg_phy_oclkdelay_cal : std_logic_vector(255 downto 0);
982  signal dbg_oclkdelay_rd_data : std_logic_vector(DRAM_WIDTH*16-1 downto 0);
983  signal dbg_rd_data_edge_detect : std_logic_vector(DQS_WIDTH-1 downto 0);
984  signal dbg_rddata : std_logic_vector(2*nCK_PER_CLK*DQ_WIDTH-1 downto 0);
985  signal dbg_rddata_valid : std_logic;
986  signal dbg_rdlvl_done : std_logic_vector(1 downto 0);
987  signal dbg_rdlvl_err : std_logic_vector(1 downto 0);
988  signal dbg_rdlvl_start : std_logic_vector(1 downto 0);
989  signal dbg_wrlvl_fine_tap_cnt : std_logic_vector(6*DQS_WIDTH-1 downto 0);
990  signal dbg_wrlvl_coarse_tap_cnt : std_logic_vector(3*DQS_WIDTH-1 downto 0);
991  signal dbg_tap_cnt_during_wrlvl : std_logic_vector(5 downto 0);
992  signal dbg_wl_edge_detect_valid : std_logic;
993  signal dbg_wrlvl_done : std_logic;
994  signal dbg_wrlvl_err : std_logic;
995  signal dbg_wrlvl_start : std_logic;
996  signal dbg_rddata_r : std_logic_vector(63 downto 0);
997  signal dbg_rddata_valid_r : std_logic;
998  signal ocal_tap_cnt : std_logic_vector(53 downto 0);
999  signal dbg_dqs : std_logic_vector(3 downto 0);
1000  signal dbg_bit : std_logic_vector(8 downto 0);
1001  signal rd_data_edge_detect_r : std_logic_vector(8 downto 0);
1002  signal wl_po_fine_cnt : std_logic_vector(53 downto 0);
1003  signal wl_po_coarse_cnt : std_logic_vector(26 downto 0);
1004  signal dbg_calib_rd_data_offset_1 : std_logic_vector(6*RANKS-1 downto 0);
1005  signal dbg_calib_rd_data_offset_2 : std_logic_vector(6*RANKS-1 downto 0);
1006  signal dbg_data_offset : std_logic_vector(5 downto 0);
1007  signal dbg_data_offset_1 : std_logic_vector(5 downto 0);
1008  signal dbg_data_offset_2 : std_logic_vector(5 downto 0);
1009  signal all_zeros : std_logic_vector(2*nCK_PER_CLK-1 downto 0) := (others => '0');
1010 
1011 
1012 begin
1013 
1014 --***************************************************************************
1015 
1016 
1017 
1018 
1019 
1020  ui_clk <= clk;
1021  ui_clk_sync_rst <= rst;
1022 
1023  sys_clk_i <= '0';
1024  clk_ref_p <= '0';
1025  clk_ref_n <= '0';
1026  init_calib_complete <= init_calib_complete_i;
1027 
1028 
1029 
1030  clk_ref_in_use_sys_clk : if (REFCLK_TYPE = "USE_SYSTEM_CLOCK") generate
1031  clk_ref_in <= mmcm_clk;
1032  end generate;
1033 
1034  clk_ref_in_others : if (REFCLK_TYPE /= "USE_SYSTEM_CLOCK") generate
1035  clk_ref_in <= clk_ref_i;
1036  end generate;
1037 
1038  u_iodelay_ctrl : mig_7series_v1_9_iodelay_ctrl
1039  generic map
1040  (
1041  TCQ => TCQ,
1042  IODELAY_GRP => IODELAY_GRP,
1043  REFCLK_TYPE => REFCLK_TYPE,
1044  SYSCLK_TYPE => SYSCLK_TYPE,
1045  SYS_RST_PORT => SYS_RST_PORT,
1046  RST_ACT_LOW => RST_ACT_LOW,
1047  DIFF_TERM_REFCLK => DIFF_TERM_REFCLK
1048  )
1049  port map
1050  (
1051  -- Outputs
1052  iodelay_ctrl_rdy => iodelay_ctrl_rdy,
1053  sys_rst_o => sys_rst_o,
1054  clk_ref => clk_ref,
1055  -- Inputs
1056  clk_ref_p => clk_ref_p,
1057  clk_ref_n => clk_ref_n,
1058  clk_ref_i => clk_ref_in,
1059  sys_rst => sys_rst
1060  );
1061  u_ddr3_clk_ibuf : mig_7series_v1_9_clk_ibuf
1062  generic map
1063  (
1064  SYSCLK_TYPE => SYSCLK_TYPE,
1065  DIFF_TERM_SYSCLK => DIFF_TERM_SYSCLK
1066  )
1067  port map
1068  (
1069  sys_clk_p => sys_clk_p,
1070  sys_clk_n => sys_clk_n,
1071  sys_clk_i => sys_clk_i,
1072  mmcm_clk => mmcm_clk
1073  );
1074  -- Temperature monitoring logic
1075 
1076  temp_mon_enabled : if (TEMP_MON_EN = "ON") generate
1077  u_tempmon : mig_7series_v1_9_tempmon
1078  generic map
1079  (
1080  TCQ => TCQ,
1081  TEMP_MON_CONTROL => TEMP_MON_CONTROL,
1082  XADC_CLK_PERIOD => XADC_CLK_PERIOD,
1083  tTEMPSAMPLE => tTEMPSAMPLE
1084  )
1085  port map
1086  (
1087  clk => clk,
1088  xadc_clk => clk_ref,
1089  rst => rst,
1090  device_temp_i => device_temp_i,
1091  device_temp => device_temp
1092  );
1093  end generate;
1094 
1095  temp_mon_disabled : if (TEMP_MON_EN /= "ON") generate
1096  device_temp <= (others => '0');
1097  end generate;
1098 
1099 
1100  u_ddr3_infrastructure : mig_7series_v1_9_infrastructure
1101  generic map
1102  (
1103  TCQ => TCQ,
1104  nCK_PER_CLK => nCK_PER_CLK,
1105  CLKIN_PERIOD => CLKIN_PERIOD,
1106  SYSCLK_TYPE => SYSCLK_TYPE,
1107  CLKFBOUT_MULT => CLKFBOUT_MULT,
1108  DIVCLK_DIVIDE => DIVCLK_DIVIDE,
1109  CLKOUT0_PHASE => CLKOUT0_PHASE,
1110  CLKOUT0_DIVIDE => CLKOUT0_DIVIDE ,
1111  CLKOUT1_DIVIDE => CLKOUT1_DIVIDE ,
1112  CLKOUT2_DIVIDE => CLKOUT2_DIVIDE ,
1113  CLKOUT3_DIVIDE => CLKOUT3_DIVIDE ,
1114  RST_ACT_LOW => RST_ACT_LOW
1115  )
1116  port map
1117  (
1118  -- Outputs
1119  rstdiv0 => rst,
1120  clk => clk,
1121  mem_refclk => mem_refclk,
1122  freq_refclk => freq_refclk,
1123  sync_pulse => sync_pulse,
1124  auxout_clk => open,
1125  ui_addn_clk_0 => open,
1126  ui_addn_clk_1 => open,
1127  ui_addn_clk_2 => open,
1128  ui_addn_clk_3 => open,
1129  ui_addn_clk_4 => open,
1130  pll_locked => pll_locked,
1131  mmcm_locked => open,
1132  rst_phaser_ref => rst_phaser_ref ,
1133  -- Inputs
1134  mmcm_clk => mmcm_clk,
1135  sys_rst => sys_rst_o,
1136  iodelay_ctrl_rdy => iodelay_ctrl_rdy,
1137  ref_dll_lock => ref_dll_lock
1138  );
1139 
1140 
1141  u_memc_ui_top_std : mig_7series_v1_9_memc_ui_top_std
1142  generic map (
1143  TCQ => TCQ,
1144  ADDR_CMD_MODE => ADDR_CMD_MODE,
1145  AL => AL,
1146  PAYLOAD_WIDTH => PAYLOAD_WIDTH,
1147  BANK_WIDTH => BANK_WIDTH,
1148  BM_CNT_WIDTH => BM_CNT_WIDTH,
1149  BURST_MODE => BURST_MODE,
1150  BURST_TYPE => BURST_TYPE,
1151  CA_MIRROR => CA_MIRROR,
1152  CK_WIDTH => CK_WIDTH,
1153  COL_WIDTH => COL_WIDTH,
1154  CMD_PIPE_PLUS1 => CMD_PIPE_PLUS1 ,
1155  CS_WIDTH => CS_WIDTH,
1156  nCS_PER_RANK => nCS_PER_RANK,
1157  CKE_WIDTH => CKE_WIDTH,
1158  DATA_WIDTH => DATA_WIDTH,
1159  DATA_BUF_ADDR_WIDTH => DATA_BUF_ADDR_WIDTH,
1160  DM_WIDTH => DM_WIDTH,
1161  DQ_CNT_WIDTH => DQ_CNT_WIDTH,
1162  DQ_WIDTH => DQ_WIDTH,
1163  DQS_CNT_WIDTH => DQS_CNT_WIDTH,
1164  DQS_WIDTH => DQS_WIDTH,
1165  DRAM_TYPE => DRAM_TYPE,
1166  DRAM_WIDTH => DRAM_WIDTH,
1167  ECC => ECC,
1168  ECC_WIDTH => ECC_WIDTH,
1169  ECC_TEST => ECC_TEST,
1170  MC_ERR_ADDR_WIDTH => MC_ERR_ADDR_WIDTH,
1171  REFCLK_FREQ => REFCLK_FREQ,
1172  nAL => nAL,
1173  nBANK_MACHS => nBANK_MACHS,
1174  CKE_ODT_AUX => CKE_ODT_AUX,
1175  nCK_PER_CLK => nCK_PER_CLK,
1176  ORDERING => ORDERING,
1177  OUTPUT_DRV => OUTPUT_DRV,
1178  IBUF_LPWR_MODE => IBUF_LPWR_MODE ,
1179  IODELAY_HP_MODE => IODELAY_HP_MODE,
1180  DATA_IO_IDLE_PWRDWN => DATA_IO_IDLE_PWRDWN,
1181  BANK_TYPE => BANK_TYPE,
1182  DATA_IO_PRIM_TYPE => DATA_IO_PRIM_TYPE,
1183  IODELAY_GRP => IODELAY_GRP,
1184  REG_CTRL => REG_CTRL,
1185  RTT_NOM => RTT_NOM,
1186  RTT_WR => RTT_WR,
1187  CL => CL,
1188  CWL => CWL,
1189  tCK => tCK,
1190  tCKE => tCKE,
1191  tFAW => tFAW,
1192  tPRDI => tPRDI,
1193  tRAS => tRAS,
1194  tRCD => tRCD,
1195  tREFI => tREFI,
1196  tRFC => tRFC,
1197  tRP => tRP,
1198  tRRD => tRRD,
1199  tRTP => tRTP,
1200  tWTR => tWTR,
1201  tZQI => tZQI,
1202  tZQCS => tZQCS,
1203  USER_REFRESH => USER_REFRESH,
1204  TEMP_MON_EN => TEMP_MON_EN,
1205  WRLVL => WRLVL,
1206  DEBUG_PORT => DEBUG_PORT,
1207  CAL_WIDTH => CAL_WIDTH,
1208  RANK_WIDTH => RANK_WIDTH,
1209  RANKS => RANKS,
1210  ODT_WIDTH => ODT_WIDTH,
1211  ROW_WIDTH => ROW_WIDTH,
1212  ADDR_WIDTH => ADDR_WIDTH,
1213  APP_DATA_WIDTH => APP_DATA_WIDTH ,
1214  APP_MASK_WIDTH => APP_MASK_WIDTH ,
1215  SIM_BYPASS_INIT_CAL => SIM_BYPASS_INIT_CAL,
1216  BYTE_LANES_B0 => BYTE_LANES_B0,
1217  BYTE_LANES_B1 => BYTE_LANES_B1,
1218  BYTE_LANES_B2 => BYTE_LANES_B2,
1219  BYTE_LANES_B3 => BYTE_LANES_B3,
1220  BYTE_LANES_B4 => BYTE_LANES_B4,
1221  DATA_CTL_B0 => DATA_CTL_B0,
1222  DATA_CTL_B1 => DATA_CTL_B1,
1223  DATA_CTL_B2 => DATA_CTL_B2,
1224  DATA_CTL_B3 => DATA_CTL_B3,
1225  DATA_CTL_B4 => DATA_CTL_B4,
1226  PHY_0_BITLANES => PHY_0_BITLANES ,
1227  PHY_1_BITLANES => PHY_1_BITLANES ,
1228  PHY_2_BITLANES => PHY_2_BITLANES ,
1229  CK_BYTE_MAP => CK_BYTE_MAP,
1230  ADDR_MAP => ADDR_MAP,
1231  BANK_MAP => BANK_MAP,
1232  CAS_MAP => CAS_MAP,
1233  CKE_ODT_BYTE_MAP => CKE_ODT_BYTE_MAP,
1234  CKE_MAP => CKE_MAP,
1235  ODT_MAP => ODT_MAP,
1236  CS_MAP => CS_MAP ,
1237  PARITY_MAP => PARITY_MAP,
1238  RAS_MAP => RAS_MAP,
1239  WE_MAP => WE_MAP,
1240  DQS_BYTE_MAP => DQS_BYTE_MAP,
1241  DATA0_MAP => DATA0_MAP,
1242  DATA1_MAP => DATA1_MAP,
1243  DATA2_MAP => DATA2_MAP,
1244  DATA3_MAP => DATA3_MAP,
1245  DATA4_MAP => DATA4_MAP,
1246  DATA5_MAP => DATA5_MAP,
1247  DATA6_MAP => DATA6_MAP,
1248  DATA7_MAP => DATA7_MAP,
1249  DATA8_MAP => DATA8_MAP,
1250  DATA9_MAP => DATA9_MAP,
1251  DATA10_MAP => DATA10_MAP,
1252  DATA11_MAP => DATA11_MAP,
1253  DATA12_MAP => DATA12_MAP,
1254  DATA13_MAP => DATA13_MAP,
1255  DATA14_MAP => DATA14_MAP,
1256  DATA15_MAP => DATA15_MAP,
1257  DATA16_MAP => DATA16_MAP,
1258  DATA17_MAP => DATA17_MAP,
1259  MASK0_MAP => MASK0_MAP,
1260  MASK1_MAP => MASK1_MAP,
1261  CALIB_ROW_ADD => CALIB_ROW_ADD,
1262  CALIB_COL_ADD => CALIB_COL_ADD,
1263  CALIB_BA_ADD => CALIB_BA_ADD,
1264  SLOT_0_CONFIG => SLOT_0_CONFIG,
1265  SLOT_1_CONFIG => SLOT_1_CONFIG,
1266  MEM_ADDR_ORDER => MEM_ADDR_ORDER ,
1267  STARVE_LIMIT => STARVE_LIMIT,
1268  USE_CS_PORT => USE_CS_PORT,
1269  USE_DM_PORT => USE_DM_PORT,
1270  USE_ODT_PORT => USE_ODT_PORT,
1271  MASTER_PHY_CTL => PHY_CONTROL_MASTER_BANK
1272  )
1273  port map (
1274  clk => clk,
1275  clk_ref => clk_ref,
1276  mem_refclk => mem_refclk, --memory clock
1277  freq_refclk => freq_refclk,
1278  pll_lock => pll_locked,
1279  sync_pulse => sync_pulse,
1280  rst => rst,
1281  rst_phaser_ref => rst_phaser_ref ,
1282  ref_dll_lock => ref_dll_lock,
1283 
1284 -- Memory interface ports
1285  ddr_dq => ddr3_dq,
1286  ddr_dqs_n => ddr3_dqs_n,
1287  ddr_dqs => ddr3_dqs_p,
1288  ddr_addr => ddr3_addr,
1289  ddr_ba => ddr3_ba ,
1290  ddr_cas_n => ddr3_cas_n,
1291  ddr_ck_n => ddr3_ck_n,
1292  ddr_ck => ddr3_ck_p,
1293  ddr_cke => ddr3_cke,
1294  ddr_cs_n => open,
1295  ddr_dm => ddr3_dm,
1296  ddr_odt => ddr3_odt,
1297  ddr_ras_n => ddr3_ras_n,
1298  ddr_reset_n => ddr3_reset_n,
1299  ddr_parity => ddr3_parity,
1300  ddr_we_n => ddr3_we_n,
1301  bank_mach_next => bank_mach_next ,
1302 
1303 -- Application interface ports
1304  app_addr => app_addr,
1305  app_cmd => app_cmd,
1306  app_en => app_en,
1307  app_hi_pri => '0',
1308  app_wdf_data => app_wdf_data,
1309  app_wdf_end => app_wdf_end,
1310  app_wdf_mask => app_wdf_mask,
1311  app_wdf_wren => app_wdf_wren,
1312  app_ecc_multiple_err => app_ecc_multiple_err,
1313  app_rd_data => app_rd_data,
1314  app_rd_data_end => app_rd_data_end ,
1315  app_rd_data_valid => app_rd_data_valid ,
1316  app_rdy => app_rdy,
1317  app_wdf_rdy => app_wdf_rdy,
1318  app_sr_req => app_sr_req,
1319  app_sr_active => app_sr_active ,
1320  app_ref_req => app_ref_req,
1321  app_ref_ack => app_ref_ack,
1322  app_zq_req => app_zq_req,
1323  app_zq_ack => app_zq_ack,
1324  app_raw_not_ecc => all_zeros,
1325  app_correct_en_i => '1',
1326 
1327  device_temp => device_temp,
1328 
1329 -- Debug logic ports
1330  dbg_idel_up_all => dbg_idel_up_all ,
1331  dbg_idel_down_all => dbg_idel_down_all ,
1332  dbg_idel_up_cpt => dbg_idel_up_cpt ,
1333  dbg_idel_down_cpt => dbg_idel_down_cpt ,
1334  dbg_sel_idel_cpt => dbg_sel_idel_cpt ,
1335  dbg_sel_all_idel_cpt => dbg_sel_all_idel_cpt,
1336  dbg_sel_pi_incdec => dbg_sel_pi_incdec ,
1337  dbg_sel_po_incdec => dbg_sel_po_incdec ,
1338  dbg_byte_sel => dbg_byte_sel,
1339  dbg_pi_f_inc => dbg_pi_f_inc,
1340  dbg_pi_f_dec => dbg_pi_f_dec,
1341  dbg_po_f_inc => dbg_po_f_inc,
1342  dbg_po_f_stg23_sel => dbg_po_f_stg23_sel,
1343  dbg_po_f_dec => dbg_po_f_dec,
1344  dbg_cpt_tap_cnt => dbg_cpt_tap_cnt ,
1345  dbg_dq_idelay_tap_cnt => dbg_dq_idelay_tap_cnt,
1346  dbg_calib_top => dbg_calib_top ,
1347  dbg_cpt_first_edge_cnt => dbg_cpt_first_edge_cnt,
1348  dbg_cpt_second_edge_cnt => dbg_cpt_second_edge_cnt ,
1349  dbg_rd_data_offset => dbg_rd_data_offset,
1350  dbg_phy_rdlvl => dbg_phy_rdlvl ,
1351  dbg_phy_wrcal => dbg_phy_wrcal ,
1352  dbg_final_po_fine_tap_cnt => dbg_final_po_fine_tap_cnt,
1353  dbg_final_po_coarse_tap_cnt => dbg_final_po_coarse_tap_cnt,
1354  dbg_rd_data_edge_detect => dbg_rd_data_edge_detect ,
1355  dbg_rddata => dbg_rddata,
1356  dbg_rddata_valid => dbg_rddata_valid ,
1357  dbg_rdlvl_done => dbg_rdlvl_done ,
1358  dbg_rdlvl_err => dbg_rdlvl_err ,
1359  dbg_rdlvl_start => dbg_rdlvl_start ,
1360  dbg_wrlvl_fine_tap_cnt => dbg_wrlvl_fine_tap_cnt,
1361  dbg_wrlvl_coarse_tap_cnt => dbg_wrlvl_coarse_tap_cnt,
1362  dbg_tap_cnt_during_wrlvl => dbg_tap_cnt_during_wrlvl,
1363  dbg_wl_edge_detect_valid => dbg_wl_edge_detect_valid,
1364  dbg_wrlvl_done => dbg_wrlvl_done,
1365  dbg_wrlvl_err => dbg_wrlvl_err ,
1366  dbg_wrlvl_start => dbg_wrlvl_start ,
1367  dbg_phy_wrlvl => dbg_phy_wrlvl ,
1368  dbg_phy_init => dbg_phy_init,
1369  dbg_prbs_rdlvl => dbg_prbs_rdlvl ,
1370  dbg_dqs_found_cal => dbg_dqs_found_cal ,
1371  dbg_pi_counter_read_val => dbg_pi_counter_read_val,
1372  dbg_po_counter_read_val => dbg_po_counter_read_val,
1373  dbg_pi_phaselock_start => dbg_pi_phaselock_start,
1374  dbg_pi_phaselocked_done => dbg_pi_phaselocked_done ,
1375  dbg_pi_phaselock_err => dbg_pi_phaselock_err,
1376  dbg_pi_phase_locked_phy4lanes => dbg_pi_phase_locked_phy4lanes,
1377  dbg_pi_dqsfound_start => dbg_pi_dqsfound_start,
1378  dbg_pi_dqsfound_done => dbg_pi_dqsfound_done,
1379  dbg_pi_dqsfound_err => dbg_pi_dqsfound_err,
1380  dbg_pi_dqs_found_lanes_phy4lanes => dbg_pi_dqs_found_lanes_phy4lanes,
1381  dbg_calib_rd_data_offset_1 => dbg_calib_rd_data_offset_1,
1382  dbg_calib_rd_data_offset_2 => dbg_calib_rd_data_offset_2,
1383  dbg_data_offset => dbg_data_offset ,
1384  dbg_data_offset_1 => dbg_data_offset_1 ,
1385  dbg_data_offset_2 => dbg_data_offset_2 ,
1386  dbg_wrcal_start => dbg_wrcal_start ,
1387  dbg_wrcal_done => dbg_wrcal_done ,
1388  dbg_wrcal_err => dbg_wrcal_err ,
1389  dbg_phy_oclkdelay_cal => dbg_phy_oclkdelay_cal,
1390  dbg_oclkdelay_rd_data => dbg_oclkdelay_rd_data,
1391  dbg_oclkdelay_calib_start => dbg_oclkdelay_calib_start,
1392  dbg_oclkdelay_calib_done => dbg_oclkdelay_calib_done,
1393  init_calib_complete => init_calib_complete_i
1394  );
1395 
1396 
1397 
1398 
1399 
1400 
1401 
1402  --*********************************************************************
1403  -- Resetting all RTL debug inputs as the debug ports are not enabled
1404  --*********************************************************************
1405  dbg_idel_down_all <= '0';
1406  dbg_idel_down_cpt <= '0';
1407  dbg_idel_up_all <= '0';
1408  dbg_idel_up_cpt <= '0';
1409  dbg_sel_all_idel_cpt <= '0';
1410  dbg_sel_idel_cpt <= (others => '0');
1411  dbg_byte_sel <= (others => '0');
1412  dbg_sel_pi_incdec <= '0';
1413  dbg_pi_f_inc <= '0';
1414  dbg_pi_f_dec <= '0';
1415  dbg_po_f_inc <= '0';
1416  dbg_po_f_dec <= '0';
1417  dbg_po_f_stg23_sel <= '0';
1418  dbg_sel_po_incdec <= '0';
1419 
1420 
1421 
1422 end architecture arch_ddr3_1_9a;
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