AMC13
Firmwares for the different applications of the AMC13 uTCA board made at Boston University
 All Classes Variables
ddr_if.vhd
1 ----------------------------------------------------------------------------------
2 -- Company:
3 -- Engineer:
4 --
5 -- Create Date: 11:31:47 07/26/2010
6 -- Design Name:
7 -- Module Name: ddr_if - Behavioral
8 -- Project Name:
9 -- Target Devices:
10 -- Tool versions:
11 -- Description:
12 --
13 -- Dependencies:
14 --
15 -- Revision:
16 -- Revision 0.01 - File Created
17 -- Additional Comments:
18 --
19 ----------------------------------------------------------------------------------
20 library IEEE,work;
21 use IEEE.STD_LOGIC_1164.ALL;
22 use IEEE.STD_LOGIC_ARITH.ALL;
23 use IEEE.STD_LOGIC_UNSIGNED.ALL;
24 use IEEE.std_logic_misc.all;
25 use work.amc13_pack.all;
26 
27 -- Uncomment the following library declaration if using
28 -- arithmetic functions with Signed or Unsigned values
29 --use IEEE.NUMERIC_STD.ALL;
30 
31 -- Uncomment the following library declaration if instantiating
32 -- any Xilinx primitives in this code.
33 library UNISIM;
34 use UNISIM.VComponents.all;
35 
36 entity ddr_if is
37  generic(SIM_BYPASS_INIT_CAL : string := "OFF"; SIMULATION : string := "FALSE");
38  port(
39  clk_ref : in std_logic;
40  mem_clk_p : in std_logic;
41  mem_clk_n : in std_logic;
42  mem_rst : in std_logic;
43  sysclk : in std_logic;
44  TCPclk : in std_logic;
45  reset : in std_logic;
46  resetsys : in std_logic;
47  run : in std_logic;
48  mem_test : in std_logic_VECTOR(1 downto 0);
49  EventData : in array3X67;
50  EventData_we : in std_logic_VECTOR(2 downto 0);
51  wport_rdy : out std_logic_VECTOR(2 downto 0);
52  WrtMonBlkDone : out std_logic_VECTOR(2 downto 0);
53  WrtMonEvtDone : out std_logic_VECTOR(2 downto 0);
54  KiloByte_toggle : out std_logic_VECTOR(2 downto 0);
55  EoB_toggle : out std_logic_VECTOR(2 downto 0);
56  EventBufAddr : in array3x14;
57  EventBufAddr_we : in std_logic_VECTOR(2 downto 0);
58  EventFIFOfull : out std_logic_VECTOR(2 downto 0);
59  TCP_din : in STD_LOGIC_VECTOR(31 downto 0);
60  TCP_channel : in STD_LOGIC_VECTOR(1 downto 0);
61  TCP_we : in STD_LOGIC;
62  TCP_wcount : out STD_LOGIC_VECTOR (2 downto 0);
63  TCP_dout : out STD_LOGIC_VECTOR(31 downto 0); -- TCP data are written in unit of 32-bit words
64  TCP_dout_type : out STD_LOGIC_VECTOR(2 downto 0); -- TCP data destination
65  TCP_raddr : in std_logic_vector(28 downto 0); -- 28-26 encoded request source 25-0 address in 64 bit word
66  TCP_length : in std_logic_vector(12 downto 0); -- in 64 bit word, actual length - 1
67  TCP_dout_valid : out STD_LOGIC;
68  TCP_rrqst : in STD_LOGIC;
69  TCP_rack : out STD_LOGIC;
70  TCP_lastword : out STD_LOGIC;
71  cs_out : out STD_LOGIC_VECTOR (511 downto 0);
72 -- ipbus signals
73  ipb_clk : in STD_LOGIC;
74  ipb_write : in STD_LOGIC;
75  ipb_strobe : in STD_LOGIC;
76  page_addr : in STD_LOGIC_VECTOR(9 downto 0);
77  ipb_addr : in STD_LOGIC_VECTOR(31 downto 0);
78  ipb_wdata : in STD_LOGIC_VECTOR(31 downto 0);
79  ipb_rdata : out STD_LOGIC_VECTOR(31 downto 0);
80  ipb_ack : out STD_LOGIC;
81  mem_stat : out STD_LOGIC_VECTOR (63 downto 0);
82  device_temp : in STD_LOGIC_VECTOR(11 downto 0);
83 -- ddr3 memory pins
84  ddr3_dq : inout STD_LOGIC_VECTOR (31 downto 0);
85  ddr3_dm : out STD_LOGIC_VECTOR (3 downto 0);
86  ddr3_addr : out STD_LOGIC_VECTOR (13 downto 0);
87  ddr3_ba : out STD_LOGIC_VECTOR (2 downto 0);
88  ddr3_dqs_p : inout STD_LOGIC_VECTOR (3 downto 0);
89  ddr3_dqs_n : inout STD_LOGIC_VECTOR (3 downto 0);
90  ddr3_ras_n : out STD_LOGIC;
91  ddr3_cas_n : out STD_LOGIC;
92  ddr3_we_n : out STD_LOGIC;
93  ddr3_reset_n : out STD_LOGIC;
94  ddr3_cke : out STD_LOGIC_vector(0 to 0);
95  ddr3_odt : out STD_LOGIC_vector(0 to 0);
96  ddr3_ck_p : out STD_LOGIC_vector(0 to 0);
97  ddr3_ck_n : out STD_LOGIC_vector(0 to 0)
98  );
99 end ddr_if;
100 
101 architecture Behavioral of ddr_if is
102 component ddr3_1_9a
103  generic
104  (
105 
106 
107  --***************************************************************************
108  -- The following parameters refer to width of various ports
109  --***************************************************************************
110  BANK_WIDTH : integer := 3;
111  -- # of memory Bank Address bits.
112  CK_WIDTH : integer := 1;
113  -- # of CK/CK# outputs to memory.
114  COL_WIDTH : integer := 10;
115  -- # of memory Column Address bits.
116  CS_WIDTH : integer := 1;
117  -- # of unique CS outputs to memory.
118  nCS_PER_RANK : integer := 1;
119  -- # of unique CS outputs per rank for phy
120  CKE_WIDTH : integer := 1;
121  -- # of CKE outputs to memory.
122  DATA_BUF_ADDR_WIDTH : integer := 5;
123  DQ_CNT_WIDTH : integer := 5;
124  -- = ceil(log2(DQ_WIDTH))
125  DQ_PER_DM : integer := 8;
126  DM_WIDTH : integer := 4;
127  -- # of DM (data mask)
128  DQ_WIDTH : integer := 32;
129  -- # of DQ (data)
130  DQS_WIDTH : integer := 4;
131  DQS_CNT_WIDTH : integer := 2;
132  -- = ceil(log2(DQS_WIDTH))
133  DRAM_WIDTH : integer := 8;
134  -- # of DQ per DQS
135  ECC : string := "OFF";
136  DATA_WIDTH : integer := 32;
137  ECC_TEST : string := "OFF";
138  PAYLOAD_WIDTH : integer := 32;
139  ECC_WIDTH : integer := 8;
140  MC_ERR_ADDR_WIDTH : integer := 31;
141 
142  nBANK_MACHS : integer := 4;
143  RANKS : integer := 1;
144  -- # of Ranks.
145  ODT_WIDTH : integer := 1;
146  -- # of ODT outputs to memory.
147  ROW_WIDTH : integer := 14;
148  -- # of memory Row Address bits.
149  ADDR_WIDTH : integer := 28;
150  -- # = RANK_WIDTH + BANK_WIDTH
151  -- + ROW_WIDTH + COL_WIDTH;
152  -- Chip Select is always tied to low for
153  -- single rank devices
154  USE_CS_PORT : integer := 0;
155  -- # = 1, When Chip Select (CS#) output is enabled
156  -- = 0, When Chip Select (CS#) output is disabled
157  -- If CS_N disabled, user must connect
158  -- DRAM CS_N input(s) to ground
159  USE_DM_PORT : integer := 1;
160  -- # = 1, When Data Mask option is enabled
161  -- = 0, When Data Mask option is disbaled
162  -- When Data Mask option is disabled in
163  -- MIG Controller Options page, the logic
164  -- related to Data Mask should not get
165  -- synthesized
166  USE_ODT_PORT : integer := 1;
167  -- # = 1, When ODT output is enabled
168  -- = 0, When ODT output is disabled
169  PHY_CONTROL_MASTER_BANK : integer := 1;
170  -- The bank index where master PHY_CONTROL resides,
171  -- equal to the PLL residing bank
172  MEM_DENSITY : string := "2Gb";
173  -- Indicates the density of the Memory part
174  -- Added for the sake of Vivado simulations
175  MEM_SPEEDGRADE : string := "107E";
176  -- Indicates the Speed grade of Memory Part
177  -- Added for the sake of Vivado simulations
178  MEM_DEVICE_WIDTH : integer := 16;
179  -- Indicates the device width of the Memory Part
180  -- Added for the sake of Vivado simulations
181 
182  --***************************************************************************
183  -- The following parameters are mode register settings
184  --***************************************************************************
185  AL : string := "0";
186  -- DDR3 SDRAM:
187  -- Additive Latency (Mode Register 1).
188  -- # = "0", "CL-1", "CL-2".
189  -- DDR2 SDRAM:
190  -- Additive Latency (Extended Mode Register).
191  nAL : integer := 0;
192  -- # Additive Latency in number of clock
193  -- cycles.
194  BURST_MODE : string := "8";
195  -- DDR3 SDRAM:
196  -- Burst Length (Mode Register 0).
197  -- # = "8", "4", "OTF".
198  -- DDR2 SDRAM:
199  -- Burst Length (Mode Register).
200  -- # = "8", "4".
201  BURST_TYPE : string := "SEQ";
202  -- DDR3 SDRAM: Burst Type (Mode Register 0).
203  -- DDR2 SDRAM: Burst Type (Mode Register).
204  -- # = "SEQ" - (Sequential),
205  -- = "INT" - (Interleaved).
206  CL : integer := 13;
207  -- in number of clock cycles
208  -- DDR3 SDRAM: CAS Latency (Mode Register 0).
209  -- DDR2 SDRAM: CAS Latency (Mode Register).
210  CWL : integer := 9;
211  -- in number of clock cycles
212  -- DDR3 SDRAM: CAS Write Latency (Mode Register 2).
213  -- DDR2 SDRAM: Can be ignored
214  OUTPUT_DRV : string := "LOW";
215  -- Output Driver Impedance Control (Mode Register 1).
216  -- # = "HIGH" - RZQ/7,
217  -- = "LOW" - RZQ/6.
218  RTT_NOM : string := "60";
219  -- RTT_NOM (ODT) (Mode Register 1).
220  -- = "120" - RZQ/2,
221  -- = "60" - RZQ/4,
222  -- = "40" - RZQ/6.
223  RTT_WR : string := "OFF";
224  -- RTT_WR (ODT) (Mode Register 2).
225  -- # = "OFF" - Dynamic ODT off,
226  -- = "120" - RZQ/2,
227  -- = "60" - RZQ/4,
228  ADDR_CMD_MODE : string := "1T" ;
229  -- # = "1T", "2T".
230  REG_CTRL : string := "OFF";
231  -- # = "ON" - RDIMMs,
232  -- = "OFF" - Components, SODIMMs, UDIMMs.
233  CA_MIRROR : string := "OFF";
234  -- C/A mirror opt for DDR3 dual rank
235 
236  --***************************************************************************
237  -- The following parameters are multiplier and divisor factors for PLLE2.
238  -- Based on the selected design frequency these parameters vary.
239  --***************************************************************************
240  CLKIN_PERIOD : integer := 4288;
241  -- Input Clock Period
242  CLKFBOUT_MULT : integer := 8;
243  -- write PLL VCO multiplier
244  DIVCLK_DIVIDE : integer := 1;
245  -- write PLL VCO divisor
246  CLKOUT0_PHASE : real := 337.5;
247  -- Phase for PLL output clock (CLKOUT0)
248  CLKOUT0_DIVIDE : integer := 2;
249  -- VCO output divisor for PLL output clock (CLKOUT0)
250  CLKOUT1_DIVIDE : integer := 2;
251  -- VCO output divisor for PLL output clock (CLKOUT1)
252  CLKOUT2_DIVIDE : integer := 32;
253  -- VCO output divisor for PLL output clock (CLKOUT2)
254  CLKOUT3_DIVIDE : integer := 8;
255  -- VCO output divisor for PLL output clock (CLKOUT3)
256 
257  --***************************************************************************
258  -- Memory Timing Parameters. These parameters varies based on the selected
259  -- memory part.
260  --***************************************************************************
261  tCKE : integer := 5000;
262  -- memory tCKE paramter in pS
263  tFAW : integer := 25000;
264  -- memory tRAW paramter in pS.
265  tPRDI : integer := 1000000;
266  -- memory tPRDI paramter in pS.
267  tRAS : integer := 34000;
268  -- memory tRAS paramter in pS.
269  tRCD : integer := 13910;
270  -- memory tRCD paramter in pS.
271  tREFI : integer := 7800000;
272  -- memory tREFI paramter in pS.
273  tRFC : integer := 160000;
274  -- memory tRFC paramter in pS.
275  tRP : integer := 13910;
276  -- memory tRP paramter in pS.
277  tRRD : integer := 5000;
278  -- memory tRRD paramter in pS.
279  tRTP : integer := 7500;
280  -- memory tRTP paramter in pS.
281  tWTR : integer := 7500;
282  -- memory tWTR paramter in pS.
283  tZQI : integer := 128000000;
284  -- memory tZQI paramter in nS.
285  tZQCS : integer := 64;
286  -- memory tZQCS paramter in clock cycles.
287 
288  --***************************************************************************
289  -- Simulation parameters
290  --***************************************************************************
291  SIM_BYPASS_INIT_CAL : string := "OFF";
292  -- # = "OFF" - Complete memory init &
293  -- calibration sequence
294  -- # = "SKIP" - Not supported
295  -- # = "FAST" - Complete memory init & use
296  -- abbreviated calib sequence
297 
298  SIMULATION : string := "FALSE";
299  -- Should be TRUE during design simulations and
300  -- FALSE during implementations
301 
302  --***************************************************************************
303  -- The following parameters varies based on the pin out entered in MIG GUI.
304  -- Do not change any of these parameters directly by editing the RTL.
305  -- Any changes required should be done through GUI and the design regenerated.
306  --***************************************************************************
307  BYTE_LANES_B0 : std_logic_vector(3 downto 0) := "0011";
308  -- Byte lanes used in an IO column.
309  BYTE_LANES_B1 : std_logic_vector(3 downto 0) := "1111";
310  -- Byte lanes used in an IO column.
311  BYTE_LANES_B2 : std_logic_vector(3 downto 0) := "1100";
312  -- Byte lanes used in an IO column.
313  BYTE_LANES_B3 : std_logic_vector(3 downto 0) := "0000";
314  -- Byte lanes used in an IO column.
315  BYTE_LANES_B4 : std_logic_vector(3 downto 0) := "0000";
316  -- Byte lanes used in an IO column.
317  DATA_CTL_B0 : std_logic_vector(3 downto 0) := "0011";
318  -- Indicates Byte lane is data byte lane
319  -- or control Byte lane. '1' in a bit
320  -- position indicates a data byte lane and
321  -- a '0' indicates a control byte lane
322  DATA_CTL_B1 : std_logic_vector(3 downto 0) := "0000";
323  -- Indicates Byte lane is data byte lane
324  -- or control Byte lane. '1' in a bit
325  -- position indicates a data byte lane and
326  -- a '0' indicates a control byte lane
327  DATA_CTL_B2 : std_logic_vector(3 downto 0) := "1100";
328  -- Indicates Byte lane is data byte lane
329  -- or control Byte lane. '1' in a bit
330  -- position indicates a data byte lane and
331  -- a '0' indicates a control byte lane
332  DATA_CTL_B3 : std_logic_vector(3 downto 0) := "0000";
333  -- Indicates Byte lane is data byte lane
334  -- or control Byte lane. '1' in a bit
335  -- position indicates a data byte lane and
336  -- a '0' indicates a control byte lane
337  DATA_CTL_B4 : std_logic_vector(3 downto 0) := "0000";
338  -- Indicates Byte lane is data byte lane
339  -- or control Byte lane. '1' in a bit
340  -- position indicates a data byte lane and
341  -- a '0' indicates a control byte lane
342  PHY_0_BITLANES : std_logic_vector(47 downto 0) := X"00000037F2FF";
343  PHY_1_BITLANES : std_logic_vector(47 downto 0) := X"000004F3FDFF";
344  PHY_2_BITLANES : std_logic_vector(47 downto 0) := X"3FE3DF000000";
345 
346  -- control/address/data pin mapping parameters
347  CK_BYTE_MAP
348  : std_logic_vector(143 downto 0) := X"000000000000000000000000000000000013";
349  ADDR_MAP
350  : std_logic_vector(191 downto 0) := X"00000010610710A10210510811B10110010B111113122119";
351  BANK_MAP : std_logic_vector(35 downto 0) := X"11510311A";
352  CAS_MAP : std_logic_vector(11 downto 0) := X"118";
353  CKE_ODT_BYTE_MAP : std_logic_vector(7 downto 0) := X"00";
354  CKE_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000104";
355  ODT_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000112";
356  CS_MAP : std_logic_vector(119 downto 0) := X"000000000000000000000000000000";
357  PARITY_MAP : std_logic_vector(11 downto 0) := X"000";
358  RAS_MAP : std_logic_vector(11 downto 0) := X"110";
359  WE_MAP : std_logic_vector(11 downto 0) := X"114";
360  DQS_BYTE_MAP
361  : std_logic_vector(143 downto 0) := X"000000000000000000000000000000012223";
362  DATA0_MAP : std_logic_vector(95 downto 0) := X"232235237234238231236233";
363  DATA1_MAP : std_logic_vector(95 downto 0) := X"220226221224223227228229";
364  DATA2_MAP : std_logic_vector(95 downto 0) := X"012015013016018011014019";
365  DATA3_MAP : std_logic_vector(95 downto 0) := X"000002001009006003005007";
366  DATA4_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
367  DATA5_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
368  DATA6_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
369  DATA7_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
370  DATA8_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
371  DATA9_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
372  DATA10_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
373  DATA11_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
374  DATA12_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
375  DATA13_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
376  DATA14_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
377  DATA15_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
378  DATA16_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
379  DATA17_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
380  MASK0_MAP : std_logic_vector(107 downto 0) := X"000000000000000004010222239";
381  MASK1_MAP : std_logic_vector(107 downto 0) := X"000000000000000000000000000";
382 
383  SLOT_0_CONFIG : std_logic_vector(7 downto 0) := "00000001";
384  -- Mapping of Ranks.
385  SLOT_1_CONFIG : std_logic_vector(7 downto 0) := "00000000";
386  -- Mapping of Ranks.
387  MEM_ADDR_ORDER
388  : string := "BANK_ROW_COLUMN";
389 
390  --***************************************************************************
391  -- IODELAY and PHY related parameters
392  --***************************************************************************
393  IODELAY_HP_MODE : string := "ON";
394  -- to phy_top
395  IBUF_LPWR_MODE : string := "OFF";
396  -- to phy_top
397  DATA_IO_IDLE_PWRDWN : string := "ON";
398  -- # = "ON", "OFF"
399  BANK_TYPE : string := "HP_IO";
400  -- # = "HP_IO", "HPL_IO", "HR_IO", "HRL_IO"
401  DATA_IO_PRIM_TYPE : string := "HP_LP";
402  -- # = "HP_LP", "HR_LP", "DEFAULT"
403  CKE_ODT_AUX : string := "FALSE";
404  USER_REFRESH : string := "OFF";
405  WRLVL : string := "ON";
406  -- # = "ON" - DDR3 SDRAM
407  -- = "OFF" - DDR2 SDRAM.
408  ORDERING : string := "NORM";
409  -- # = "NORM", "STRICT", "RELAXED".
410  CALIB_ROW_ADD : std_logic_vector(15 downto 0) := X"0000";
411  -- Calibration row address will be used for
412  -- calibration read and write operations
413  CALIB_COL_ADD : std_logic_vector(11 downto 0) := X"000";
414  -- Calibration column address will be used for
415  -- calibration read and write operations
416  CALIB_BA_ADD : std_logic_vector(2 downto 0) := "000";
417  -- Calibration bank address will be used for
418  -- calibration read and write operations
419  TCQ : integer := 100;
420  IODELAY_GRP : string := "IODELAY_MIG";
421  -- It is associated to a set of IODELAYs with
422  -- an IDELAYCTRL that have same IODELAY CONTROLLER
423  -- clock frequency.
424  SYSCLK_TYPE : string := "DIFFERENTIAL";
425  -- System clock type DIFFERENTIAL, SINGLE_ENDED,
426  -- NO_BUFFER
427  REFCLK_TYPE : string := "NO_BUFFER";
428  -- Reference clock type DIFFERENTIAL, SINGLE_ENDED
429  -- NO_BUFFER, USE_SYSTEM_CLOCK
430 
431  CMD_PIPE_PLUS1 : string := "ON";
432  -- add pipeline stage between MC and PHY
433  DRAM_TYPE : string := "DDR3";
434  CAL_WIDTH : string := "HALF";
435  STARVE_LIMIT : integer := 2;
436  -- # = 2,3,4.
437 
438  --***************************************************************************
439  -- Referece clock frequency parameters
440  --***************************************************************************
441  REFCLK_FREQ : real := 200.0;
442  -- IODELAYCTRL reference clock frequency
443  DIFF_TERM_REFCLK : string := "TRUE";
444  -- Differential Termination for idelay
445  -- reference clock input pins
446  --***************************************************************************
447  -- System clock frequency parameters
448  --***************************************************************************
449  tCK : integer := 1072;
450  -- memory tCK paramter.
451  -- # = Clock Period in pS.
452  nCK_PER_CLK : integer := 4;
453  -- # of memory CKs per fabric CLK
454  DIFF_TERM_SYSCLK : string := "FALSE";
455  -- Differential Termination for System
456  -- clock input pins
457 
458  --***************************************************************************
459  -- Debug parameters
460  --***************************************************************************
461  DEBUG_PORT : string := "OFF";
462  -- # = "ON" Enable debug signals/controls.
463  -- = "OFF" Disable debug signals/controls.
464 
465  --***************************************************************************
466  -- Temparature monitor parameter
467  --***************************************************************************
468  TEMP_MON_CONTROL : string := "EXTERNAL";
469  -- # = "INTERNAL", "EXTERNAL"
470 
471  RST_ACT_LOW : integer := 0
472  -- =1 for active low reset,
473  -- =0 for active high.
474  );
475  port
476  (
477 
478  -- Inouts
479  ddr3_dq : inout std_logic_vector(DQ_WIDTH-1 downto 0);
480  ddr3_dqs_p : inout std_logic_vector(DQS_WIDTH-1 downto 0);
481  ddr3_dqs_n : inout std_logic_vector(DQS_WIDTH-1 downto 0);
482 
483  -- Outputs
484  ddr3_addr : out std_logic_vector(ROW_WIDTH-1 downto 0);
485  ddr3_ba : out std_logic_vector(BANK_WIDTH-1 downto 0);
486  ddr3_ras_n : out std_logic;
487  ddr3_cas_n : out std_logic;
488  ddr3_we_n : out std_logic;
489  ddr3_reset_n : out std_logic;
490  ddr3_ck_p : out std_logic_vector(CK_WIDTH-1 downto 0);
491  ddr3_ck_n : out std_logic_vector(CK_WIDTH-1 downto 0);
492  ddr3_cke : out std_logic_vector(CKE_WIDTH-1 downto 0);
493 
494  ddr3_dm : out std_logic_vector(DM_WIDTH-1 downto 0);
495  ddr3_odt : out std_logic_vector(ODT_WIDTH-1 downto 0);
496 
497  -- Inputs
498  -- Differential system clocks
499  sys_clk_p : in std_logic;
500  sys_clk_n : in std_logic;
501  -- Single-ended iodelayctrl clk (reference clock)
502  clk_ref_i : in std_logic;
503  -- user interface signals
504  app_addr : in std_logic_vector(ADDR_WIDTH-1 downto 0);
505  app_cmd : in std_logic_vector(2 downto 0);
506  app_en : in std_logic;
507  app_wdf_data : in std_logic_vector((nCK_PER_CLK*2*PAYLOAD_WIDTH)-1 downto 0);
508  app_wdf_end : in std_logic;
509  app_wdf_mask : in std_logic_vector((nCK_PER_CLK*2*PAYLOAD_WIDTH)/8-1 downto 0) ;
510  app_wdf_wren : in std_logic;
511  app_rd_data : out std_logic_vector((nCK_PER_CLK*2*PAYLOAD_WIDTH)-1 downto 0);
512  app_rd_data_end : out std_logic;
513  app_rd_data_valid : out std_logic;
514  app_rdy : out std_logic;
515  app_wdf_rdy : out std_logic;
516  app_sr_req : in std_logic;
517  app_sr_active : out std_logic;
518  app_ref_req : in std_logic;
519  app_ref_ack : out std_logic;
520  app_zq_req : in std_logic;
521  app_zq_ack : out std_logic;
522  ui_clk : out std_logic;
523  ui_clk_sync_rst : out std_logic;
524 
525 
526 
527  init_calib_complete : out std_logic;
528  device_temp_i : in std_logic_vector(11 downto 0);
529  -- The 12 MSB bits of the temperature sensor transfer
530  -- function need to be connected to this port. This port
531  -- will be synchronized w.r.t. to fabric clock internally.
532 
533 
534  -- System reset
535  sys_rst : in std_logic
536  );
537 END COMPONENT;
538 COMPONENT ddr_rport
539  PORT(
540  memclk : IN std_logic;
541  sysclk : IN std_logic;
542  reset : IN std_logic;
543  resetSys : IN std_logic;
544  resetMem : IN std_logic;
545  run : IN std_logic;
546  test : IN std_logic_vector(1 downto 0);
547  test_block_sent : IN std_logic;
548  TCP_addr : IN std_logic_vector(28 downto 0);
549  TCP_length : IN std_logic_vector(12 downto 0);
550  TCP_rqst : IN std_logic;
551  ipb_clk : IN std_logic;
552  ipb_write : IN std_logic;
553  ipb_strobe : IN std_logic;
554  ipb_addr : IN std_logic_vector(31 downto 0);
555  page_addr : IN std_logic_vector(9 downto 0);
556  app_ack : IN std_logic;
557  app_rdy : IN std_logic;
558  app_rd_data_valid : IN std_logic;
559  app_rd_data : IN std_logic_vector(255 downto 0);
560  test_pause : OUT std_logic;
561  test_status : OUT std_logic_vector(63 downto 0);
562  TCP_dout : OUT std_logic_vector(31 downto 0);
563  TCP_dout_type : OUT std_logic_vector(2 downto 0);
564  TCP_dout_valid : OUT std_logic;
565  TCP_ack : OUT std_logic;
566  TCP_lastword : OUT std_logic;
567  cs_out : OUT std_logic_vector(511 downto 0);
568  ipb_rdata : OUT std_logic_vector(31 downto 0);
569  ipb_ack : OUT std_logic;
570  app_rqst : OUT std_logic;
571  app_en : OUT std_logic;
572  app_addr : OUT std_logic_vector(27 downto 0)
573  );
574 END COMPONENT;
575 COMPONENT ddr_wportA
576  PORT(
577  sysclk : IN std_logic;
578  memclk : IN std_logic;
579  fifo_rst : IN std_logic;
580  fifo_en : IN std_logic;
581  resetSys : in STD_LOGIC;
582  resetMem : in STD_LOGIC;
583  run : IN std_logic;
584  din : IN std_logic_vector(65 downto 0);
585  din_we : IN std_logic;
586  event_addr : IN std_logic_vector(13 downto 0);
587  addr_we : IN std_logic;
588  ack : IN std_logic;
589  app_wdf_rdy : IN std_logic;
590  app_rdy : IN std_logic;
591  port_rdy : OUT std_logic;
592  WrtMonBlkDone : out std_logic;
593  WrtMonEvtDone : out std_logic;
594  KiloByte_toggle : out std_logic;
595  EoB_toggle : out std_logic;
596  buf_full : OUT std_logic;
597  rqst : OUT std_logic;
598  app_en : OUT std_logic;
599  app_wdf_wren : OUT std_logic;
600  app_addr : OUT std_logic_vector(23 downto 0);
601  dout : OUT std_logic_vector(255 downto 0);
602  cs_out : OUT std_logic_vector(511 downto 0);
603  debug : OUT std_logic_vector(63 downto 0)
604  );
605 END COMPONENT;
606 COMPONENT ddr_wportB
607  PORT(
608  memclk : IN std_logic;
609  sysclk : IN std_logic;
610  reset : IN std_logic;
611  resetSys : in STD_LOGIC;
612  resetMem : in STD_LOGIC;
613  run : IN std_logic;
614  test : IN std_logic_vector(1 downto 0);
615  TCP_din : in STD_LOGIC_VECTOR(31 downto 0);
616  TCP_channel : in STD_LOGIC_VECTOR(1 downto 0);
617  TCP_we : IN std_logic;
618  TCP_wcount : out STD_LOGIC_VECTOR (2 downto 0);
619  ipb_clk : IN std_logic;
620  ipb_write : IN std_logic;
621  ipb_strobe : IN std_logic;
622  ipb_addr : IN std_logic_vector(31 downto 0);
623  ipb_wdata : IN std_logic_vector(31 downto 0);
624  app_ack : IN std_logic;
625  app_wdf_rdy : IN std_logic;
626  app_rdy : IN std_logic;
627  test_block_sent : OUT std_logic;
628  test_pause : IN STD_LOGIC;
629  ipb_ack : OUT std_logic;
630  app_rqst : OUT std_logic;
631  app_en : OUT std_logic;
632  app_wdf_wren : OUT std_logic;
633  app_wdf_mask : OUT std_logic_vector(7 downto 0);
634  app_addr : OUT std_logic_vector(23 downto 0);
635  dout : OUT std_logic_vector(255 downto 0);
636  debug_out : OUT std_logic_vector(63 downto 0)
637  );
638 END COMPONENT;
639 COMPONENT FIFO_RESET_7S
640  PORT(
641  reset : IN std_logic;
642  clk : IN std_logic;
643  fifo_rst : OUT std_logic;
644  fifo_en : OUT std_logic
645  );
646 END COMPONENT;
647 signal ipb_wack : std_logic := '0';
648 signal ipb_rack : std_logic := '0';
649 type array4X256 is array(0 to 3) of std_logic_vector(255 downto 0);
650 signal w_data : array4X256 := (others => (others => '0'));
651 type array4X24 is array(0 to 3) of std_logic_vector(23 downto 0);
652 signal w_addr : array4X24 := (others => (others => '0'));
653 signal test_stat : std_logic_vector(63 downto 0) := (others => '0');
654 signal w_mask : std_logic_vector(7 downto 0) := (others => '0');
655 signal app_wdf_wren : std_logic := '0';
656 signal app_en : std_logic := '0';
657 signal app_cmd : std_logic_vector(2 downto 0) := (others => '0');
658 signal app_addr : std_logic_vector(27 downto 0) := (others => '0');
659 signal app_raddr : std_logic_vector(27 downto 0) := (others => '0');
660 signal app_rdy : std_logic := '0';
661 signal app_rdyp : std_logic := '0';
662 signal app_wdf_rdy : std_logic := '0';
663 signal app_wdf_rdyp : std_logic := '0';
664 signal app_wdf_mask : std_logic_vector(31 downto 0) := (others => '0');
665 signal app_rd_data_valid : std_logic := '0';
666 signal clk : std_logic := '0';
667 signal phy_init_done : std_logic := '0';
668 signal app_rd_data : std_logic_vector(255 downto 0) := (others => '0');
669 signal app_wdf_data : std_logic_vector(255 downto 0) := (others => '0');
670 signal test_block_sent : std_logic := '0';
671 signal test_pause : std_logic := '0';
672 signal app_rrqst : std_logic := '0';
673 signal app_rack : std_logic := '0';
674 signal app_ren : std_logic := '0';
675 signal app_wen : std_logic_vector(3 downto 0) := (others => '1');
676 signal w_data_we : std_logic_vector(3 downto 0) := (others => '0');
677 signal w_rqst : std_logic_vector(3 downto 0) := (others => '0');
678 signal w_ack : std_logic_vector(3 downto 0) := (others => '0');
679 signal InitDoneSyncRegs : std_logic_vector(2 downto 0) := (others => '0');
680 signal resetSyncRegsMem : std_logic_vector(2 downto 0) := (others => '0');
681 signal resetSyncRegsTCP : std_logic_vector(2 downto 0) := (others => '0');
682 signal sysCntr : std_logic_vector(19 downto 0) := (others => '0');
683 signal MemCntr : std_logic_vector(20 downto 0) := (others => '0');
684 signal sysCntrSyncRegs : std_logic_vector(2 downto 0) := (others => '0');
685 --signal TCP_dout_i : std_logic_vector(31 downto 0) := (others => '0');
686 signal fifo_rst : std_logic := '1';
687 signal fifo_en : std_logic := '1';
688 signal reset_dl : std_logic := '1';
689 signal debug : std_logic_vector(255 downto 0) := (others => '0');
690 signal rport_cs : std_logic_vector(511 downto 0) := (others => '0');
691 type array3X512 is array(0 to 2) of std_logic_vector(511 downto 0);
692 signal wportA_cs : array3x512 := (others => (others => '0'));
693 COMPONENT chipscope1
694  generic (N : integer := 5);
695  PORT(
696  clk : IN std_logic;
697  Din : IN std_logic_vector(303 downto 0)
698  );
699 END COMPONENT;
700 signal cs_in : std_logic_vector(303 downto 0) := (others => '0');
701 COMPONENT chipscope
702  generic (N : integer := 5);
703  PORT(
704  clka : IN std_logic;
705  clkb : IN std_logic;
706  ina : IN std_logic_vector(135 downto 0);
707  inb : IN std_logic_vector(135 downto 0)
708  );
709 END COMPONENT;
710 signal cs_ina : std_logic_vector(135 downto 0) := (others => '0');
711 signal cs_inb : std_logic_vector(135 downto 0) := (others => '0');
712 
713 begin
714 --i_chipscope: chipscope generic map(N => 7) PORT MAP(
715 -- clka => sysclk,
716 -- clkb => clk,
717 -- ina => cs_ina,
718 -- inb => cs_inb
719 -- );
720 --cs_ina(135 downto 128) <= cs_inb(135 downto 128);
721 --cs_inb(135 downto 132) <= wportA_cs(0)(18 downto 15);
722 --cs_inb(131) <= wportA_cs(0)(13);
723 --cs_inb(130 downto 128) <= wportA_cs(0)(42 downto 40);
724 --cs_ina(16 downto 0) <= wportA_cs(0)(37 downto 21);
725 --cs_inb(23 downto 21) <= wportA_cs(0)(42 downto 40);
726 --cs_inb(20 downto 0) <= wportA_cs(0)(20 downto 0);
727 --cs_out(165 downto 104) <= rport_cs(165 downto 104);
728 --cs_out(103 downto 89) <= wportA_cs(0)(14 downto 0);
729 --cs_out(88) <= app_wdf_wren;
730 --cs_out(87) <= app_wdf_rdy;
731 --cs_out(86) <= app_rdy;
732 --cs_out(85) <= app_en;
733 --cs_out(84 downto 81) <= app_wen;
734 --cs_out(80 downto 77) <= w_ack;
735 --cs_out(76 downto 73) <= w_rqst;
736 --cs_out(72 downto 0) <= rport_cs(72 downto 0);
737 --i_chipscope1: chipscope1 generic map(N => 2) PORT MAP(
738 -- clk => clk,
739 -- din => cs_in
740 -- );
741 --cs_in(288) <= w_rqst(3);
742 --cs_in(289) <= test_stat(31);
743 --cs_in(287) <= w_data_we(3);
744 --g_cs: for i in 0 to 7 generate
745 -- cs_in(i*26+103 downto i*26+78) <= w_data(3)(i*32+25 downto i*32);
746 --end generate;
747 --cs_in(77 downto 70) <= w_mask;
748 --cs_in(69 downto 46) <= w_addr(3);
749 --cs_in(45 downto 18) <= app_addr;
750 --cs_in(17 downto 14) <= w_ack;
751 --cs_in(13 downto 10) <= w_rqst;
752 --cs_in(9) <= app_rack;
753 --cs_in(8) <= app_ren;
754 --cs_in(7) <= app_rrqst;
755 --cs_in(6) <= app_wdf_rdyp;
756 --cs_in(5) <= app_wdf_wren;
757 --cs_in(4) <= app_wdf_rdy;
758 --cs_in(3) <= app_rdyp;
759 --cs_in(2) <= app_rdy;
760 --cs_in(1) <= app_en;
761 --cs_in(0) <= app_wen(3);
762 --TCP_dout <= TCP_dout_i;
763 process(sysclk)
764 begin
765  if(sysclk'event and sysclk = '1')then
766  SysCntr <= SysCntr + 1;
767  end if;
768 end process;
769 ipb_ack <= ipb_rack or ipb_wack;
770 i_ddr_rport: ddr_rport PORT MAP (
771  memclk => clk,
772  sysclk => TCPclk,
773  reset => reset,
774  resetSys => resetSyncRegsTCP(2),
775  resetMem => resetSyncRegsMem(2),
776  run => run,
777  test => mem_test,
778  test_block_sent => test_block_sent,
779  test_pause => test_pause,
780  test_status => test_stat,
781  TCP_dout => TCP_dout,
782  TCP_dout_type => TCP_dout_type,
783  TCP_addr => TCP_raddr,
784  TCP_length => TCP_length,
785  TCP_dout_valid => TCP_dout_valid ,
786  TCP_rqst => TCP_rrqst,
787  TCP_lastword => TCP_lastword,
788  TCP_ack => TCP_rack,
789  cs_out => rport_cs,
790  ipb_clk => ipb_clk,
791  ipb_write => ipb_write,
792  ipb_strobe => ipb_strobe,
793  ipb_addr => ipb_addr,
794  ipb_rdata => ipb_rdata,
795  ipb_ack => ipb_rack,
796  page_addr => page_addr,
797  app_rqst => app_rrqst,
798  app_ack => app_rack,
799  app_en => app_ren,
800  app_rdy => app_rdyp,
801  app_rd_data_valid => app_rd_data_valid,
802  app_rd_data => app_rd_data,
803  app_addr => app_raddr
804  );
805 i_FIFO_RESET_7S: FIFO_RESET_7S PORT MAP(
806  reset => resetSys,
807  clk => sysclk ,
808  fifo_rst => fifo_rst,
809  fifo_en => fifo_en
810  );
811 g_ddr_wportA : for i in 0 to 2 generate
812  i_ddr_wportA: ddr_wportA PORT MAP(
813  sysclk => sysclk,
814  memclk => clk,
815  fifo_rst => fifo_rst,
816  fifo_en => fifo_en,
817  resetSys => resetSys,
818  resetMem => resetSyncRegsMem(2),
819  run => run,
820  din => EventData(i)(65 downto 0),
821  din_we => EventData_we(i),
822  port_rdy => wport_rdy(i),
823  WrtMonBlkDone => WrtMonBlkDone(i),
824  WrtMonEvtDone => WrtMonEvtDone(i),
825  KiloByte_toggle => KiloByte_toggle(i),
826  EoB_toggle => EoB_toggle(i),
827  buf_full => EventFIFOfull(i),
828  event_addr => EventBufAddr(i),
829  addr_we => EventBufAddr_we(i),
830  rqst => w_rqst (i),
831  ack => w_ack(i),
832  app_rdy => app_rdyp,
833  app_en => app_wen(i),
834  app_wdf_rdy => app_wdf_rdyp,
835  app_wdf_wren => w_data_we(i),
836  app_addr => w_addr(i),
837  dout => w_data (i),
838  cs_out => wportA_cs(i),
839  debug => debug(64*i+63 downto 64*i)
840  );
841 end generate;
842 i_ddr_wportB: ddr_wportB PORT MAP(
843  memclk => clk,
844  sysclk => TCPclk,
845  reset => reset,
846  resetSys => resetSyncRegsTCP(2),
847  resetMem => resetSyncRegsMem(2),
848  run => run,
849  test => mem_test,
850  test_block_sent => test_block_sent,
851  test_pause => test_pause,
852  TCP_din => TCP_din,
853  TCP_channel => TCP_channel,
854  TCP_we => TCP_we ,
855  TCP_wcount => TCP_wcount,
856  ipb_clk => ipb_clk,
857  ipb_write => ipb_write,
858  ipb_strobe => ipb_strobe,
859  ipb_addr => ipb_addr,
860  ipb_wdata => ipb_wdata,
861  ipb_ack => ipb_wack,
862  app_rqst => w_rqst(3),
863  app_ack => w_ack(3),
864  app_en => app_wen(3),
865  app_rdy => app_rdyp,
866  app_wdf_rdy => app_wdf_rdyp,
867  app_wdf_wren => w_data_we(3),
868  app_wdf_mask => w_mask,
869  app_addr => w_addr(3),
870  dout => w_data (3),
871  debug_out => debug(255 downto 192)
872  );
873 app_rdyp <= app_rdy or not app_en;
874 app_wdf_rdyp <= app_wdf_rdy or not app_wdf_wren;
875 process(TCPclk,reset)
876 begin
877  if(reset = '1')then
878  resetSyncRegsTCP <= (others => '1');
879  elsif(TCPclk'event and TCPclk = '1')then
880  resetSyncRegsTCP <= resetSyncRegsTCP(1 downto 0) & '0';
881  end if;
882 end process;
883 process(clk,reset)
884 begin
885  if(reset = '1')then
886  resetSyncRegsMem <= (others => '1');
887  elsif(clk'event and clk = '1')then
888  resetSyncRegsMem <= resetSyncRegsMem(1 downto 0) & '0';
889  end if;
890 end process;
891 process(clk,phy_init_done)
892 begin
893  if(phy_init_done = '0')then
894  InitDoneSyncRegs <= (others => '0');
895  elsif(clk'event and clk = '1')then
896  InitDoneSyncRegs <= InitDoneSyncRegs(1 downto 0) & '1';
897  end if;
898 end process;
899 process(clk, w_ack)
900 variable w_sel : std_logic_vector(1 downto 0);
901 begin
902  w_sel(1) := w_ack(3) or w_ack(2);
903  w_sel(0) := w_ack(3) or w_ack(1);
904  if(clk'event and clk = '1')then
905  if(InitDoneSyncRegs(2) = '0')then
906  app_rack <= '0';
907  w_ack <= (others => '0');
908  elsif(or_reduce(w_ack and w_rqst) = '0' and (app_rrqst = '0' or app_rack = '0'))then
909  app_rack <= '0';
910  w_ack <= (others => '0');
911  if(w_rqst(3) = '1')then
912  w_ack(3) <= '1';
913  elsif(app_rrqst = '1')then
914  app_rack <= '1';
915  elsif(w_rqst(0) = '1')then
916  w_ack(0) <= '1';
917  elsif(w_rqst(1) = '1')then
918  w_ack(1) <= '1';
919  elsif(w_rqst(2) = '1')then
920  w_ack(2) <= '1';
921  end if;
922  end if;
923  if(app_en = '0' or app_rdy = '1')then
924  if(app_rack = '1')then
925  app_cmd(0) <= '1';
926  app_addr(26 downto 3) <= app_raddr(26 downto 3);
927  else
928  app_cmd(0) <= '0';
929  app_addr(26 downto 3) <= w_addr(conv_integer(w_sel));
930  end if;
931  end if;
932  if(resetSyncRegsMem(2) = '1')then
933  app_en <= '0';
934  elsif(or_reduce(app_wen) = '1' or app_ren = '1')then
935  app_en <= '1';
936  elsif(app_rdy = '1')then
937  app_en <= '0';
938  end if;
939  if(resetSyncRegsMem(2) = '1')then
940  app_wdf_wren <= '0';
941  elsif(or_reduce(w_data_we) = '1')then
942  app_wdf_wren <= '1';
943  elsif(app_wdf_rdy = '1')then
944  app_wdf_wren <= '0';
945  end if;
946  if(app_wdf_rdy = '1' or app_wdf_wren = '0')then
947  if(w_ack(3) = '1')then
948  for i in 0 to 31 loop
949  app_wdf_mask(i) <= w_mask(i/4);
950  end loop;
951  else
952  app_wdf_mask <= (others => '0');
953  end if;
954  case w_sel is
955  when "00" => app_wdf_data <= w_data(0);
956  when "01" => app_wdf_data <= w_data(1);
957  when "10" => app_wdf_data <= w_data(2);
958  when others => app_wdf_data <= w_data(3);
959  end case;
960  end if;
961  end if;
962 end process;
963 app_addr(27) <= '0';
964 app_addr(2 downto 0) <= "000";
965 i_ddr3 : ddr3_1_9a
966  port map(
967  ddr3_dq => ddr3_dq,
968  ddr3_dqs_n => ddr3_dqs_n,
969  ddr3_dqs_p => ddr3_dqs_p,
970  ddr3_addr => ddr3_addr,
971  ddr3_ba => ddr3_ba,
972  ddr3_ras_n => ddr3_ras_n,
973  ddr3_cas_n => ddr3_cas_n,
974  ddr3_we_n => ddr3_we_n,
975  ddr3_reset_n => ddr3_reset_n,
976  ddr3_ck_p => ddr3_ck_p,
977  ddr3_ck_n => ddr3_ck_n,
978  ddr3_cke => ddr3_cke,
979  ddr3_dm => ddr3_dm,
980  ddr3_odt => ddr3_odt,
981  sys_clk_p => mem_clk_p,
982  sys_clk_n => mem_clk_n,
983  clk_ref_i => clk_ref,
984  app_addr => app_addr,
985  app_cmd => app_cmd,
986  app_en => app_en,
987  app_wdf_data => app_wdf_data,
988  app_wdf_end => app_wdf_wren,
989  app_wdf_mask => app_wdf_mask,
990  app_wdf_wren => app_wdf_wren,
991  app_rd_data => app_rd_data,
992  app_rd_data_end => open,
993  app_rd_data_valid => app_rd_data_valid,
994  app_rdy => app_rdy,
995  app_wdf_rdy => app_wdf_rdy,
996  app_sr_req => '0',
997  app_sr_active => open,
998  app_ref_req => '0',
999  app_ref_ack => open,
1000  app_zq_req => '0',
1001  app_zq_ack => open,
1002  ui_clk => clk,
1003  ui_clk_sync_rst => open ,
1004  init_calib_complete => phy_init_done,
1005  device_temp_i => device_temp,
1006  sys_rst => mem_rst
1007  );
1008 --process(phy_init_done,test_stat,ipb_addr,app_rrqst, app_rack, app_ren, app_wen, w_data_we, w_rqst, w_ack, app_en_accept, test_block_sent, test_pause, app_wdf_wren, app_en, app_cmd, app_rdy, app_wdf_rdy, app_wdf_rdyp, app_rd_data_valid, w_mask, w_addr, app_cmd, app_addr, app_raddr)
1009 --begin
1010 -- case ipb_addr(18 downto 16) is
1011 -- when "000" => mem_stat <= not phy_init_done & test_stat(32) & x"0" & app_rrqst & app_rack & app_ren & test_block_sent & test_pause & app_en_accept & app_wen & w_data_we & w_rqst & w_ack & test_stat(31 downto 0);
1012 -- when "001" => mem_stat <= "00" & app_wdf_wren & app_en & app_rdy & app_wdf_rdy & app_wdf_rdyp & app_rd_data_valid & w_addr(0) & w_mask & w_addr(1);
1013 -- when "010" => mem_stat <= "00000" & app_cmd & w_addr(3) & "00" & test_stat(63 downto 58) & w_addr(2);
1014 -- when "011" => mem_stat <= x"0" & app_addr & x"0" & app_raddr;
1015 -- when "100" => mem_stat <= debug(63 downto 0);
1016 -- when "101" => mem_stat <= debug(127 downto 64);
1017 -- when "110" => mem_stat <= debug(191 downto 128);
1018 ---- when others => mem_stat <= debug(255 downto 192);
1019 -- when others => mem_stat <= test_stat(63 downto 32) & debug(223 downto 192);
1020 -- end case;
1021 --end process;
1022 mem_stat(63) <= not phy_init_done;
1023 mem_stat(62) <= debug(192);
1024 mem_stat(61) <= debug(128);
1025 mem_stat(60) <= debug(64);
1026 mem_stat(31 downto 0) <= test_stat(31 downto 0);
1027 --mem_stat(62) <= test_stat(32);
1028 mem_stat(59 downto 32) <= (others => '0');
1029 --mem_stat(40 downto 32) <= debug(8 downto 0);
1030 --mem_stat(31 downto 0) <= test_stat(31 downto 0);
1031 --mem_stat(31 downto 21) <= SysCntr(10 downto 0);
1032 --mem_stat(20 downto 0) <= MemCntr;
1033 --mem_stat(55 downto 53) <= SysCntrSync;
1034 --mem_stat(0) <= overflowErr;
1035 --mem_stat(1) <= testErr;
1036 --mem_stat(2) <= mem_ready;
1037 --mem_stat(17) <= rd_rqst;
1038 --mem_stat(18) <= not wfifo_empty;
1039 --mem_stat(19) <= wfifo_full;
1040 --mem_stat(20) <= test;
1041 --mem_stat(21) <= EOF;
1042 --mem_stat(60 downto 56) <= SysCntr(15 downto 11);
1043 --mem_stat(26) <= not fifo_en;
1044 --mem_stat(27) <= app_cmd(0);
1045 --mem_stat(28) <= app_en;
1046 --mem_stat(29) <= not app_rdy;
1047 --mem_stat(30) <= not app_wdf_rdy;
1048 --mem_stat(31) <= not phy_init_done;
1049 end Behavioral;
1050 
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