amc13_pack Package Reference

List of all members.

Package Body >> amc13_pack

Use Clauses
amc13_version_package	Package <amc13_version_package>

Constants
device_ID	std_logic_vector ( 15 downto 0 ) := device_ID
	from amc13_version_package
T2_version	std_logic_vector ( 15 downto 0 ) := T2_version
	from amc13_version_package
K7version	std_logic_vector ( 15 downto 0 ) := K7version
	from amc13_version_package
V6version	std_logic_vector ( 15 downto 0 ) := V6version
	from amc13_version_package
CTRversion	std_logic_vector ( 7 downto 0 ) := CTRversion
	from amc13_version_package
key	std_logic_vector ( 31 downto 0 ) := key
	from amc13_version_package
flavor	string := flavor
	from amc13_version_package
lsc_speed	integer := lsc_speed
	from amc13_version_package
ID_addr	std_logic_vector ( 15 downto 0 ) := x " 0000 "
CRC_vme_addr	std_logic_vector ( 15 downto 0 ) := x " 0004 "
CRC_DCC_addr	std_logic_vector ( 15 downto 0 ) := x " 0008 "
CRC_LRB_addr	std_logic_vector ( 15 downto 0 ) := x " 000c "
VME_csr_addr	std_logic_vector ( 15 downto 0 ) := x " 0010 "
F_cmd_addr	std_logic_vector ( 15 downto 0 ) := x " 0100 "
key_addr	std_logic_vector ( 15 downto 0 ) := x " 0294 "
F_wbuf_addr	std_logic_vector ( 15 downto 0 ) := x " 0800 "
F_rbuf_addr	std_logic_vector ( 15 downto 0 ) := x " 0a00 "
CSR_addr	std_logic_vector ( 15 downto 0 ) := x " 0000 "
CFG_addr	std_logic_vector ( 15 downto 0 ) := x " 0001 "
MON_ctrl_addr	std_logic_vector ( 15 downto 0 ) := x " 0002 "
HTR_EN_addr	std_logic_vector ( 15 downto 0 ) := x " 0003 "
SFP_CSR_addr	std_logic_vector ( 15 downto 0 ) := x " 0004 "
HTR_test_addr	std_logic_vector ( 15 downto 0 ) := x " 0005 "
BC0_delay_addr	std_logic_vector ( 15 downto 0 ) := x " 0006 "
SRC_id_addr	std_logic_vector ( 15 downto 0 ) := x " 0007 "
TTC_bcnt_addr	std_logic_vector ( 15 downto 0 ) := x " 0008 "
TTC_cal_addr	std_logic_vector ( 15 downto 0 ) := x " 0009 "
mem_status_addr	std_logic_vector ( 15 downto 0 ) := x " 000a "
test_ctrl_addr	std_logic_vector ( 15 downto 0 ) := x " 000b "
PAGE_addr	std_logic_vector ( 15 downto 0 ) := x " 000c "
MON_wc_addr	std_logic_vector ( 15 downto 0 ) := x " 000d "
evn_pntr_addr	std_logic_vector ( 15 downto 0 ) := x " 000e "
SL_pntr_addr	std_logic_vector ( 15 downto 0 ) := x " 000f "
SRC_id1_addr	std_logic_vector ( 15 downto 0 ) := x " 0011 "
SRC_id2_addr	std_logic_vector ( 15 downto 0 ) := x " 0011 "
fake_length_addr	std_logic_vector ( 15 downto 0 ) := x " 0018 "
TTS_pattern_addr	std_logic_vector ( 15 downto 0 ) := x " 0019 "
status_cntr_addr	std_logic_vector ( 15 downto 0 ) := x " 0020 "
sysmon_addr	std_logic_vector ( 15 downto 0 ) := x " 0030 "
misc_cntr_addr	std_logic_vector ( 15 downto 0 ) := x " 0040 "
LSC_addr	std_logic_vector ( 15 downto 0 ) := x " 0080 "
I2C_addr	std_logic_vector ( 15 downto 0 ) := x " 0100 "
L1A_buf_addr	std_logic_vector ( 15 downto 0 ) := x " 0200 "
AMC_reg_addr	std_logic_vector ( 15 downto 0 ) := x " 0800 "
SFP_reg_addr	std_logic_vector ( 15 downto 0 ) := x " 1000 "
HTR0_base_addr	std_logic_vector ( 15 downto 0 ) := x " 1000 "
HTR1_base_addr	std_logic_vector ( 15 downto 0 ) := x " 1080 "
HTR2_base_addr	std_logic_vector ( 15 downto 0 ) := x " 1100 "
HTR3_base_addr	std_logic_vector ( 15 downto 0 ) := x " 1180 "
HTR4_base_addr	std_logic_vector ( 15 downto 0 ) := x " 1200 "
HTR5_base_addr	std_logic_vector ( 15 downto 0 ) := x " 1280 "
HTR6_base_addr	std_logic_vector ( 15 downto 0 ) := x " 1300 "
HTR7_base_addr	std_logic_vector ( 15 downto 0 ) := x " 1380 "
HTR8_base_addr	std_logic_vector ( 15 downto 0 ) := x " 1400 "
HTR9_base_addr	std_logic_vector ( 15 downto 0 ) := x " 1480 "
HTR10_base_addr	std_logic_vector ( 15 downto 0 ) := x " 1500 "
HTR11_base_addr	std_logic_vector ( 15 downto 0 ) := x " 1580 "
HTR_status	std_logic_vector ( 11 downto 0 ) := x " 008 "
CH0_wc	std_logic_vector ( 11 downto 0 ) := x " 400 "
CH0_cerr	std_logic_vector ( 11 downto 0 ) := x " 408 "
CH0_uerr	std_logic_vector ( 11 downto 0 ) := x " 410 "
CH0_event_cnt	std_logic_vector ( 11 downto 0 ) := x " 418 "
CH0_evt_cerr	std_logic_vector ( 11 downto 0 ) := x " 420 "
CH0_evt_uerr	std_logic_vector ( 11 downto 0 ) := x " 428 "
CH0_evt_trunc	std_logic_vector ( 11 downto 0 ) := x " 430 "
CH0_evt_badid	std_logic_vector ( 11 downto 0 ) := x " 438 "
CH0_evt_crc	std_logic_vector ( 11 downto 0 ) := x " 440 "

Types
array2X2	array ( 0 to 1 ) of std_logic_vector ( 1 downto 0 )
array2X3	array ( 0 to 1 ) of std_logic_vector ( 2 downto 0 )
array2X4	array ( 0 to 1 ) of std_logic_vector ( 3 downto 0 )
array2X7	array ( 0 to 1 ) of std_logic_vector ( 6 downto 0 )
array2X8	array ( 0 to 1 ) of std_logic_vector ( 7 downto 0 )
array2X9	array ( 0 to 1 ) of std_logic_vector ( 8 downto 0 )
array2X16	array ( 0 to 1 ) of std_logic_vector ( 15 downto 0 )
array2X32	array ( 0 to 1 ) of std_logic_vector ( 31 downto 0 )
array2X64	array ( 0 to 1 ) of std_logic_vector ( 63 downto 0 )
array2X65	array ( 0 to 1 ) of std_logic_vector ( 64 downto 0 )
array3X2	array ( 0 to 2 ) of std_logic_vector ( 1 downto 0 )
array3X3	array ( 0 to 2 ) of std_logic_vector ( 2 downto 0 )
array3X4	array ( 0 to 2 ) of std_logic_vector ( 3 downto 0 )
array3X5	array ( 0 to 2 ) of std_logic_vector ( 4 downto 0 )
array3X7	array ( 0 to 2 ) of std_logic_vector ( 6 downto 0 )
array3X8	array ( 0 to 2 ) of std_logic_vector ( 7 downto 0 )
array3X9	array ( 0 to 2 ) of std_logic_vector ( 8 downto 0 )
array3X10	array ( 0 to 2 ) of std_logic_vector ( 9 downto 0 )
array3X11	array ( 0 to 2 ) of std_logic_vector ( 10 downto 0 )
array3X12	array ( 0 to 2 ) of std_logic_vector ( 11 downto 0 )
array3X13	array ( 0 to 2 ) of std_logic_vector ( 12 downto 0 )
array3X14	array ( 0 to 2 ) of std_logic_vector ( 13 downto 0 )
array3X16	array ( 0 to 2 ) of std_logic_vector ( 15 downto 0 )
array3X17	array ( 0 to 2 ) of std_logic_vector ( 16 downto 0 )
array3X18	array ( 0 to 2 ) of std_logic_vector ( 17 downto 0 )
array3X19	array ( 0 to 2 ) of std_logic_vector ( 18 downto 0 )
array3X20	array ( 0 to 2 ) of std_logic_vector ( 19 downto 0 )
array3X21	array ( 0 to 2 ) of std_logic_vector ( 20 downto 0 )
array3X24	array ( 0 to 2 ) of std_logic_vector ( 23 downto 0 )
array3X26	array ( 0 to 2 ) of std_logic_vector ( 25 downto 0 )
array3X28	array ( 0 to 2 ) of std_logic_vector ( 27 downto 0 )
array3X32	array ( 0 to 2 ) of std_logic_vector ( 31 downto 0 )
array3X48	array ( 0 to 2 ) of std_logic_vector ( 47 downto 0 )
array3X56	array ( 0 to 2 ) of std_logic_vector ( 55 downto 0 )
array3X64	array ( 0 to 2 ) of std_logic_vector ( 63 downto 0 )
array3X65	array ( 0 to 2 ) of std_logic_vector ( 64 downto 0 )
array3X66	array ( 0 to 2 ) of std_logic_vector ( 65 downto 0 )
array3X67	array ( 0 to 2 ) of std_logic_vector ( 66 downto 0 )
array4X9	array ( 0 to 3 ) of std_logic_vector ( 8 downto 0 )
array4X10	array ( 0 to 3 ) of std_logic_vector ( 9 downto 0 )
array4X11	array ( 0 to 3 ) of std_logic_vector ( 10 downto 0 )
array4X12	array ( 0 to 3 ) of std_logic_vector ( 11 downto 0 )
array4X13	array ( 0 to 4 ) of std_logic_vector ( 12 downto 0 )
array4X64	array ( 0 to 3 ) of std_logic_vector ( 63 downto 0 )
array5X11	array ( 0 to 4 ) of std_logic_vector ( 10 downto 0 )
array5X13	array ( 0 to 4 ) of std_logic_vector ( 12 downto 0 )
array6X64	array ( 0 to 5 ) of std_logic_vector ( 63 downto 0 )
array8X4	array ( 0 to 7 ) of std_logic_vector ( 3 downto 0 )
array8X12	array ( 0 to 7 ) of std_logic_vector ( 11 downto 0 )
array12X2	array ( 0 to 11 ) of std_logic_vector ( 1 downto 0 )
array12X3	array ( 0 to 11 ) of std_logic_vector ( 2 downto 0 )
array12X4	array ( 0 to 11 ) of std_logic_vector ( 3 downto 0 )
array12X6	array ( 0 to 11 ) of std_logic_vector ( 5 downto 0 )
array12X8	array ( 0 to 11 ) of std_logic_vector ( 7 downto 0 )
array12X13	array ( 0 to 11 ) of std_logic_vector ( 12 downto 0 )
array12X16	array ( 0 to 11 ) of std_logic_vector ( 15 downto 0 )
array12X20	array ( 0 to 11 ) of std_logic_vector ( 19 downto 0 )
array12X21	array ( 0 to 11 ) of std_logic_vector ( 20 downto 0 )
array12X32	array ( 0 to 11 ) of std_logic_vector ( 31 downto 0 )
array12X64	array ( 0 to 11 ) of std_logic_vector ( 63 downto 0 )
array32X32	array ( 0 to 31 ) of std_logic_vector ( 31 downto 0 )
array16X4	array ( 0 to 15 ) of std_logic_vector ( 3 downto 0 )
array24X32	array ( 0 to 23 ) of std_logic_vector ( 31 downto 0 )
array2X3x5	array ( 0 to 1 ) of array3x5
array2X3x12	array ( 0 to 1 ) of array3x12
bitarray9x64	array ( 0 to 8 ) of bit_vector ( 63 downto 0 )

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Detailed Description

Definition at line 11 of file amc13_pack.vhd.

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The documentation for this class was generated from the following file:

• src/common/amc13_pack.vhd