Behavioral Architecture Reference

List of all members.

Processes
PROCESS_802	( sysclk )
PROCESS_803	( TCPclk ,reset )
PROCESS_804	( clk ,reset )
PROCESS_805	( clk ,phy_init_done )
PROCESS_806	( clk ,w_ack )

Components
ddr3_1_9a	<Entity ddr3_1_9a>
ddr_rport	<Entity ddr_rport>
ddr_wportA	<Entity ddr_wportA>
ddr_wportB	<Entity ddr_wportB>
FIFO_RESET_7S	<Entity FIFO_RESET_7S>
chipscope1
chipscope

Types
array4X256	array ( 0 to 3 ) of std_logic_vector ( 255 downto 0 )
array4X24	array ( 0 to 3 ) of std_logic_vector ( 23 downto 0 )
array3X512	array ( 0 to 2 ) of std_logic_vector ( 511 downto 0 )

Signals
ipb_wack	std_logic := ' 0 '
ipb_rack	std_logic := ' 0 '
w_data	array4X256 := ( others = > ( others = > ' 0 ' ) )
w_addr	array4X24 := ( others = > ( others = > ' 0 ' ) )
test_stat	std_logic_vector ( 63 downto 0 ) := ( others = > ' 0 ' )
w_mask	std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
app_wdf_wren	std_logic := ' 0 '
app_en	std_logic := ' 0 '
app_cmd	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
app_addr	std_logic_vector ( 27 downto 0 ) := ( others = > ' 0 ' )
app_raddr	std_logic_vector ( 27 downto 0 ) := ( others = > ' 0 ' )
app_rdy	std_logic := ' 0 '
app_rdyp	std_logic := ' 0 '
app_wdf_rdy	std_logic := ' 0 '
app_wdf_rdyp	std_logic := ' 0 '
app_wdf_mask	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
app_rd_data_valid	std_logic := ' 0 '
clk	std_logic := ' 0 '
phy_init_done	std_logic := ' 0 '
app_rd_data	std_logic_vector ( 255 downto 0 ) := ( others = > ' 0 ' )
app_wdf_data	std_logic_vector ( 255 downto 0 ) := ( others = > ' 0 ' )
test_block_sent	std_logic := ' 0 '
test_pause	std_logic := ' 0 '
app_rrqst	std_logic := ' 0 '
app_rack	std_logic := ' 0 '
app_ren	std_logic := ' 0 '
app_wen	std_logic_vector ( 3 downto 0 ) := ( others = > ' 1 ' )
w_data_we	std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
w_rqst	std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
w_ack	std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
InitDoneSyncRegs	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
resetSyncRegsMem	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
resetSyncRegsTCP	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
sysCntr	std_logic_vector ( 19 downto 0 ) := ( others = > ' 0 ' )
MemCntr	std_logic_vector ( 20 downto 0 ) := ( others = > ' 0 ' )
sysCntrSyncRegs	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
fifo_rst	std_logic := ' 1 '
fifo_en	std_logic := ' 1 '
reset_dl	std_logic := ' 1 '
debug	std_logic_vector ( 255 downto 0 ) := ( others = > ' 0 ' )
rport_cs	std_logic_vector ( 511 downto 0 ) := ( others = > ' 0 ' )
wportA_cs	array3x512 := ( others = > ( others = > ' 0 ' ) )
cs_in	std_logic_vector ( 303 downto 0 ) := ( others = > ' 0 ' )
cs_ina	std_logic_vector ( 135 downto 0 ) := ( others = > ' 0 ' )
cs_inb	std_logic_vector ( 135 downto 0 ) := ( others = > ' 0 ' )

Instantiations
i_ddr_rport	ddr_rport <Entity ddr_rport>
i_FIFO_RESET_7S	FIFO_RESET_7S <Entity FIFO_RESET_7S>
i_ddr_wportA	ddr_wportA <Entity ddr_wportA>
i_ddr_wportB	ddr_wportB <Entity ddr_wportB>
i_ddr3	ddr3_1_9a <Entity ddr3_1_9a>

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Detailed Description

Definition at line 101 of file ddr_if.vhd.

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The documentation for this class was generated from the following files:

• src/common/DDR/ddr_if.vhd