behavioral Architecture Reference

List of all members.

Processes
PROCESS_126	( RST_PCIClk ,PCIe_clk )
PROCESS_127	( RST_LowClk ,low_clk )
PROCESS_246	( RST_PCIClk ,PCIe_clk )
PROCESS_247	( RST_LowClk ,low_clk )

Components
fifo_generator_0
	!!!!!!!!!!!!!!!!!!! XILINX Vivado VERSION !!!!!!!!!!!!!!!!!!!!!
resync	<Entity resync>
lpm_fifo	<Entity lpm_fifo>
	!!!!!!!!!!!!!!!!!!! XILINX VERSION !!!!!!!!!!!!!!!!!!!!!

Signals
data_mux	std_logic_vector ( 31 downto 0 )
wen_mux	std_logic
low_wen_sync	std_logic
end_evt_sync	std_logic
fifo_dto	std_logic_vector ( 31 downto 0 )
timer	std_logic_vector ( 15 downto 0 )
timer_cnt	std_logic
trig	std_logic
soft_reset	std_logic

Instantiations
wen_resync	resync <Entity resync>
End_evt_resync	resync <Entity resync>
wen_resync	resync <Entity resync>
fifo_rnd	lpm_fifo <Entity lpm_fifo>
	!!!!!!!!!!!!!!!!!!! XILINX VERSION !!!!!!!!!!!!!!!!!
End_evt_resync	resync <Entity resync>

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Detailed Description

Definition at line 49 of file memory_rnd.vhd.

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The documentation for this class was generated from the following files:

• src/CMS_DAQ_if/10Gb/slink/memory_rnd.vhd
• src/CMS_DAQ_if/5Gb/slink/memory_rnd.vhd