behavioral Architecture Reference

List of all members.

Processes
PROCESS_85	( Rst_Evtclk ,evt_clk )
PROCESS_86	( Rst_PCIclk ,PCIe_clk )
PROCESS_87	( Rst_Evtclk ,evt_clk )
PROCESS_88	( Rst_Evtclk ,evt_clk )
PROCESS_89	( Rst_PCIclk ,PCIe_clk )
PROCESS_90	( Rst_Evtclk ,evt_clk )
PROCESS_91	( pseudo_reset ( 0 ) ,evt_clk )
PROCESS_92	( Rst_Evtclk ,evt_clk )
PROCESS_93	( evt_run ( 0 ) ,evt_clk )
PROCESS_94	( Rst_Evtclk ,evt_clk )
PROCESS_95	( Rst_Evtclk ,evt_clk )
PROCESS_96	( trigger ,evt_clk )
PROCESS_97	( Rst_Evtclk ,evt_clk )
PROCESS_98	( Rst_Evtclk ,evt_clk )
PROCESS_205	( Rst_Evtclk ,evt_clk )
PROCESS_206	( Rst_PCIclk ,PCIe_clk )
PROCESS_207	( Rst_Evtclk ,evt_clk )
PROCESS_208	( Rst_Evtclk ,evt_clk )
PROCESS_209	( Rst_PCIclk ,PCIe_clk )
PROCESS_210	( Rst_Evtclk ,evt_clk )
PROCESS_211	( pseudo_reset ( 0 ) ,evt_clk )
PROCESS_212	( Rst_Evtclk ,evt_clk )
PROCESS_213	( evt_run ( 0 ) ,evt_clk )
PROCESS_214	( Rst_Evtclk ,evt_clk )
PROCESS_215	( Rst_Evtclk ,evt_clk )
PROCESS_216	( trigger ,evt_clk )
PROCESS_217	( Rst_Evtclk ,evt_clk )
PROCESS_218	( Rst_Evtclk ,evt_clk )

Components
resync	<Entity resync>
trigger_gen	<Entity trigger_gen>
CRC_generator
memory_rnd	<Entity memory_rnd>
generate_3	<Entity generate_3>
reset_resync	<Entity reset_resync>

Signals
rnd_dt_O	std_logic_vector ( 63 downto 0 )
rnd_dt_L	std_logic_vector ( 63 downto 0 )
ena_rnd_dt	std_logic
LFF_D	std_logic
BX	std_logic_vector ( 11 downto 0 )
SOURCE	std_logic_vector ( 11 downto 0 )
evt_lenght	std_logic_vector ( 23 downto 0 )
crc_error	std_logic_vector ( 2 downto 0 )
bit_error	std_logic_vector ( 2 downto 0 )
hd_error	std_logic_vector ( 2 downto 0 )
tr_error	std_logic_vector ( 2 downto 0 )
HD_ena	std_logic
TR_ena	std_logic_vector ( 3 downto 0 )
PL_ena	std_logic_vector ( 1 downto 0 )
HD_dt	std_logic_vector ( 63 downto 0 )
TR_dt	std_logic_vector ( 63 downto 0 )
PL_dt	std_logic_vector ( 63 downto 0 )
evt_run	std_logic_vector ( 3 downto 0 )
pre_TR	std_logic_vector ( 63 downto 0 )
WC_size	std_logic_vector ( 20 downto 0 )
end_WC	std_logic_vector ( 1 downto 0 )
run_mode	std_logic
ena_PCIe	std_logic
trig_nb	std_logic_vector ( 23 downto 0 )
trigger	std_logic
end_evt	std_logic
soft_rst	std_logic
wc_rnd	std_logic_vector ( 15 downto 0 )
trigger_rnd	std_logic
pseudo_reset	std_logic_vector ( 0 downto 0 )
CRC_OUT	std_logic_vector ( 15 downto 0 )
CRC_val	std_logic_vector ( 15 downto 0 )
CRC_cmp	std_logic
CRC_reg	std_logic_vector ( 63 downto 0 )
wen_reg	std_logic
data_reg	std_logic_vector ( 63 downto 0 )
uctrl_reg	std_logic
PCIe_dto_trg	std_logic_vector ( 31 downto 0 )
PCIe_dto_local	std_logic_vector ( 31 downto 0 )
Byte_rnd	std_logic_vector ( 7 downto 0 )
Rst_PCIclk	std_logic
Rst_Evtclk	std_logic
Rst_lowclk	std_logic

Instantiations
rst_pci_i1	reset_resync <Entity reset_resync>
rst_evt_i1	reset_resync <Entity reset_resync>
rst_low_i1	reset_resync <Entity reset_resync>
i3	generate_3 <Entity generate_3>
crc_err_resync	resync <Entity resync>
bit_err_resync	resync <Entity resync>
hd_err_resync	resync <Entity resync>
tr_err_resync	resync <Entity resync>
trig	trigger_gen <Entity trigger_gen>
rnd_mem_trig	memory_rnd <Entity memory_rnd>
rst_pci_i1	reset_resync <Entity reset_resync>
rst_evt_i1	reset_resync <Entity reset_resync>
rst_low_i1	reset_resync <Entity reset_resync>
i3	generate_3 <Entity generate_3>
crc_err_resync	resync <Entity resync>
bit_err_resync	resync <Entity resync>
hd_err_resync	resync <Entity resync>
tr_err_resync	resync <Entity resync>
trig	trigger_gen <Entity trigger_gen>
rnd_mem_trig	memory_rnd <Entity memory_rnd>

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Detailed Description

Definition at line 59 of file event_generator.vhd.

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The documentation for this class was generated from the following files:

• src/CMS_DAQ_if/10Gb/slink/event_generator.vhd
• src/CMS_DAQ_if/5Gb/slink/event_generator.vhd