Behavioral Architecture Reference

List of all members.

Processes
PROCESS_1005	( sysclk ,reset ,ClientClk_lock )
PROCESS_1006	( ClientClk2X ,SFP_TX_FSM_RESET_DONE ,SFP_RX_FSM_RESET_DONE )
PROCESS_1007	( ClientClk2X ,reset ,ClientClk_lock )
PROCESS_1008	( ClientClk ,TCPreset ,ClientClk_lock )
PROCESS_1009	( ClientClk )
PROCESS_1010	( ClientClk2X )
PROCESS_1011	( txusrclk )
PROCESS_1012	( TXUSRCLK ,TCPreset )
PROCESS_1013	( TXUSRCLK ,SFP_TX_FSM_RESET_DONE ( 0 ) )
PROCESS_1014	( TXUSRCLK ,SFP_TX_FSM_RESET_DONE ( 1 ) )
PROCESS_1015	( TXUSRCLK ,SFP_TX_FSM_RESET_DONE ( 2 ) )
PROCESS_1016	( sysclk )
PROCESS_1017	( sysclk )
PROCESS_1018	( ClientClk2X )
PROCESS_1019	( sysclk ,rstCntr )
PROCESS_1020	( sysclk ,rstCntr )
PROCESS_1021	( sysclk )
PROCESS_1022	( ClientClk2X )
PROCESS_1023	( ClientClk2X )
PROCESS_1024	( ClientClk2X ,TCP_w_sel ,RETX_ddr_wrqst )
PROCESS_1025	( ClientClk2X )
PROCESS_1026	( DRPclk )
PROCESS_1027	( SFP_TXD ,SFP_RXD ,SFP_RXD_inv )
PROCESS_1028	( ipb_clk )
PROCESS_1029	( ipb_addr )
PROCESS_1030	( ipb_clk )

Components
TCPIP	<Entity TCPIP>
XGbEPCS32	<Entity XGbEPCS32>
FIFO_RESET_7S	<Entity FIFO_RESET_7S>
SFP3_v2_7_init	<Entity SFP3_v2_7_init>
RETXdata_chksum	<Entity RETXdata_chksum>
check_event	<Entity check_event>
RAM32x6D	<Entity RAM32x6D>
RAM32x6Db	<Entity RAM32x6Db>
cmsCRC64	<Entity cmsCRC64>
chipscope
chipscope1
chipscope1b
icon1
ila36x1024

Types
array3x512	array ( 0 to 2 ) of std_logic_vector ( 511 downto 0 )

Signals
resetSyncRegs	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
ClientClk2XresetSyncRegs	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
refclk	std_logic := ' 0 '
REFCLK2XPLLRST	std_logic := ' 0 '
refclk2x_in	std_logic := ' 0 '
ClientClk2x_dcm	std_logic := ' 0 '
ClientClk2x	std_logic := ' 0 '
ClientClk_dcm	std_logic := ' 0 '
ClientClk	std_logic := ' 0 '
ClientClk_lock	std_logic := ' 0 '
ClientClkToggle	std_logic := ' 0 '
ClientClkToggle_q	std_logic := ' 0 '
FIFO_rst	std_logic := ' 0 '
FIFO_en	std_logic := ' 0 '
TX_high	std_logic := ' 0 '
us_cntr	std_logic_vector ( 9 downto 0 ) := ( others = > ' 0 ' )
ms_cntr	std_logic_vector ( 10 downto 0 ) := ( others = > ' 0 ' )
strobe_us	std_logic := ' 0 '
strobe_ms	std_logic := ' 0 '
TSclock	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
evt_FIFO_full	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
evt_FIFO_empty	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
evt_FIFO_we	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
evt_FIFO_re	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
evt_FIFO_rep	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
evt_FIFO_data_avl	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
evt_FIFO_di	array3X67 := ( others = > ( others = > ' 0 ' ) )
evt_FIFO_do	array3X67 := ( others = > ( others = > ' 0 ' ) )
evt_FIFO_RDCOUNT	array3X9 := ( others = > ( others = > ' 0 ' ) )
evt_FIFO_WRCOUNT	array3X9 := ( others = > ( others = > ' 0 ' ) )
EVENTdata_avl	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
EVENTdata_addr	array3X13 := ( others = > ( others = > ' 0 ' ) )
re_RETX_ddr_wq	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
RETX_ddr_data_we	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
RETX_ddr_wrqst	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
RETX_ddr_rrqst	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
RETX_ddr_out	array3X32 := ( others = > ( others = > ' 0 ' ) )
RETX_ddr_LEN_max	array3X5 := ( others = > ( others = > ' 0 ' ) )
RETX_ddr_LEN	array3X5 := ( others = > ( others = > ' 0 ' ) )
RETXdata_we	array3X2 := ( others = > ( others = > ' 0 ' ) )
DDR2TCPdata	std_logic_vector ( 32 downto 0 ) := ( others = > ' 0 ' )
rst_RETXdata_chksum	std_logic := ' 0 '
RETXdata_chksum_out	std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
RETXdata_checksum	array3x16 := ( others = > ( others = > ' 0 ' ) )
RETXdataLEN	array3X13 := ( others = > ( others = > ' 0 ' ) )
RETXdataAddr	array3X26 := ( others = > ( others = > ' 0 ' ) )
RETXdata_space	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
RETXdataRqst	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
RETXdataACK	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
ReleaseLen	array3X11 := ( others = > ( others = > ' 0 ' ) )
Release_space	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
ReleaseBuffer	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
Release_rqst	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
rrqstMask	std_logic_vector ( 5 downto 0 ) := ( others = > ' 0 ' )
TCP_rrqst_i	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
odd	std_logic := ' 0 '
rst_odd	std_logic := ' 0 '
TCP_rFIFO_do_vld	std_logic := ' 0 '
ld_RETXdata_chksum	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
ld_RETXdata_chksum_r	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
ld_RETXdata_chksum_r2	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
TCP_rFIFO_wa0SyncRegs	std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
TCP_rFIFO_wa1SyncRegs	std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
TCP_rFIFO_wa2SyncRegs	std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
TCP_rFIFO_di	std_logic_vector ( 35 downto 0 ) := ( others = > ' 0 ' )
TCP_rFIFO_do	std_logic_vector ( 35 downto 0 ) := ( others = > ' 0 ' )
TCP_rFIFO_wa	std_logic_vector ( 4 downto 0 ) := ( others = > ' 0 ' )
TCP_rFIFO_ra	std_logic_vector ( 4 downto 0 ) := ( others = > ' 0 ' )
RETX_ddr_rp_rst	std_logic := ' 0 '
RETX_ddr_rp_we	std_logic := ' 0 '
RETX_ddr_rp_di	std_logic_vector ( 17 downto 0 ) := ( others = > ' 0 ' )
RETX_ddr_rp_do	std_logic_vector ( 17 downto 0 ) := ( others = > ' 0 ' )
RETX_ddr_rp_a	std_logic_vector ( 4 downto 0 ) := ( others = > ' 0 ' )
TCP_length_i	std_logic_vector ( 20 downto 0 ) := ( others = > ' 0 ' )
TCP_raddr_i	std_logic_vector ( 28 downto 0 ) := ( others = > ' 0 ' )
TCP_rlength	std_logic_vector ( 12 downto 0 ) := ( others = > ' 0 ' )
TCP_wFIFO_re	std_logic := ' 0 '
TCP_w_busy	std_logic := ' 0 '
TCP_wFIFO_we	std_logic := ' 0 '
TCP_w_sel	std_logic_vector ( 1 downto 0 ) := ( others = > ' 0 ' )
TCP_w_wc	std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
TCP_wFIFO_DI	std_logic_vector ( 33 downto 0 ) := ( others = > ' 0 ' )
TCP_wFIFO_DO	std_logic_vector ( 33 downto 0 ) := ( others = > ' 0 ' )
TCP_wFIFO_RDCOUNT	std_logic_vector ( 8 downto 0 ) := ( others = > ' 0 ' )
TCP_wFIFO_WRCOUNT	std_logic_vector ( 8 downto 0 ) := ( others = > ' 0 ' )
inh_TX	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
inh_TX_q	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
reset_TXSyncRegs	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
SFP_TXOUTCLK	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
txusrclk	std_logic := ' 0 '
qplllock	std_logic := ' 0 '
qpllreset	std_logic := ' 0 '
GTX_TX_READ	std_logic := ' 0 '
LINK_down	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
EnTCPIP	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
SFP_rxoutclk	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
SFP_rxusrclk	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
SFP_txuserrdy	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
SFP_rxresetdone	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
SFP_rxuserrdy	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
SFP_drprdy	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
SFP_drpen	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
SFP_drpwe	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
SFP_rxdfeagchold	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
SFP_adapt_done	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
SFP_rxmonitor	array3X7 := ( others = > ( others = > ' 0 ' ) )
SFP_drpdo	array3X16 := ( others = > ( others = > ' 0 ' ) )
SFP_rxmonitorsel	array3X2 := ( others = > ( others = > ' 0 ' ) )
SFP_drpaddr	array3X9 := ( others = > ( others = > ' 0 ' ) )
SFP_drpdi	array3X16 := ( others = > ( others = > ' 0 ' ) )
SFP_RX_FSM_RESET_DONE	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
SFP_TX_FSM_RESET_DONE	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
SFP_RXDVLD	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
SFP_RXHEADERVLD	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
SFP_RXGEARBOXSLIP	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
SFP_RXGOOD	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
SFP_TXD	array3X32 := ( others = > ( others = > ' 0 ' ) )
SFP_TXD_inv	array3X32 := ( others = > ( others = > ' 0 ' ) )
SFP_TXHEADER	array3X2 := ( others = > ( others = > ' 0 ' ) )
SFP_RXD	array3X32 := ( others = > ( others = > ' 0 ' ) )
SFP_RXD_inv	array3X32 := ( others = > ( others = > ' 0 ' ) )
SFP_RXHEADER	array3X2 := ( others = > ( others = > ' 0 ' ) )
SFP_EmacPhyTxD	array3X32 := ( others = > ( others = > ' 0 ' ) )
SFP_EmacPhyTxC	array3X4 := ( others = > ( others = > ' 0 ' ) )
SFP_PhyEmacRxD	array3X32 := ( others = > ( others = > ' 0 ' ) )
SFP_PhyEmacRxC	array3X4 := ( others = > ( others = > ' 0 ' ) )
EmacPhyTxD	array3X32 := ( others = > ( others = > ' 0 ' ) )
EmacPhyTxC	array3X4 := ( others = > ( others = > ' 0 ' ) )
PhyEmacRxD	array3X32 := ( others = > ( others = > ' 0 ' ) )
PhyEmacRxC	array3X4 := ( others = > ( others = > ' 0 ' ) )
TCPIP2SFP_sel	array3X2 := ( others = > ( others = > ' 0 ' ) )
SFP2TCPIP	array3X2 := ( others = > ( others = > ' 0 ' ) )
IPADDR	array3X32 := ( others = > ( others = > ' 0 ' ) )
SFP_IPADDR	array3X32 := ( x " c0a80120 " , x " c0a80121 " , x " c0a80122 " )
RTOmin	std_logic_vector ( 15 downto 0 ) := x " 0008 "
MACADDR	array3X48 := ( others = > ( others = > ' 0 ' ) )
GTX_TX_PAUSE	std_logic := ' 0 '
TXSEQ_cntr	std_logic_vector ( 6 downto 0 ) := ( others = > ' 0 ' )
SFP_TXSEQUENCE	array3X7 := ( others = > ( others = > ' 0 ' ) )
SFP_LOOPBACK_IN	array3X3 := ( others = > ( others = > ' 0 ' ) )
SFP_RXPRBSERR_OUT	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
SFP_RXPRBSSEL_IN	array3X3 := ( others = > ( others = > ' 0 ' ) )
SFP_TXPRBSSEL_IN	array3X3 := ( others = > ( others = > ' 0 ' ) )
SFP_EYESCANDATAERROR_OUT	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
got_eofToggle	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
EventBufAddr_we_i	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
EventData_re_i	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
EventBufAddr_i	array3X14 := ( others = > ( others = > ' 0 ' ) )
ReadBusy	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
UNA_MonBufMatch	std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
UNA_TCPBufMatch	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
UNA_MonBufSyncRegs	std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
UNA_TCPBufSyncRegs	std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
inc_ddr_paSyncRegs	std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
sysDIV2	std_logic := ' 0 '
evt_FIFO_sel	std_logic := ' 0 '
ReleaseMonBuf	std_logic := ' 0 '
ReleaseTCPBuf	std_logic := ' 0 '
WrtMonBufAllDone_i	std_logic := ' 0 '
NXT_TCPBuf	array3X12 := ( others = > ( others = > ' 0 ' ) )
UNA_MonBuf	array5X11 := ( others = > ( others = > ' 0 ' ) )
UNA_TCPBuf	array4X11 := ( others = > ( others = > ' 0 ' ) )
AddrOffset	array3X10 := ( others = > ( others = > ' 0 ' ) )
SFPresetSyncRegs	array3X3 := ( others = > ( others = > ' 0 ' ) )
TCPresetSyncRegs	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
got_eofToggle0SyncRegs	std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
reset_TCPIP	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
got_eofToggle1SyncRegs	std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
got_eofToggle2SyncRegs	std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
TCPIP_rdata	array3X32 := ( others = > ( others = > ' 0 ' ) )
AddrBuf_full	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
mon_evt_cnt_i	std_logic_vector ( 10 downto 0 ) := ( others = > ' 0 ' )
MonBufUsed	std_logic_vector ( 9 downto 0 ) := ( others = > ' 0 ' )
MonBuf_full	std_logic := ' 0 '
chk_MonBuf_avl	std_logic := ' 0 '
FirstBlkAddrDo	array2x3x12 := ( others = > ( others = > ( others = > ' 0 ' ) ) )
FirstBlkAddr_ra	array2x3x5 := ( others = > ( others = > ( others = > ' 0 ' ) ) )
FirstBlkAddr_re	array2X3 := ( others = > ( others = > ' 0 ' ) )
WrtMonEvtDone_l	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
MonEvtQueued	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
FirstBlkAddrDoValid	array2X3 := ( others = > ( others = > ' 0 ' ) )
FirstBlkAddr_wa	std_logic_vector ( 4 downto 0 ) := ( others = > ' 0 ' )
FirstBlkAddrDi	std_logic_vector ( 11 downto 0 ) := ( others = > ' 0 ' )
FirstBlkAddr_we	std_logic := ' 0 '
MonBuf_wa	std_logic_vector ( 10 downto 0 ) := ( others = > ' 0 ' )
MonBuf_ra	std_logic_vector ( 10 downto 0 ) := ( others = > ' 0 ' )
NXT_MonBuf	array3X11 := ( others = > ( others = > ' 0 ' ) )
Written_MonBuf	array4X11 := ( others = > ( others = > ' 0 ' ) )
Written_MonBufMatch	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
SFP_pd	array3X2 := ( others = > ( others = > ' 0 ' ) )
EventData_reCntr	array3X32 := ( others = > ( others = > ' 0 ' ) )
EventData_weCntr	array3X32 := ( others = > ( others = > ' 0 ' ) )
EventBufAddr_weCntr	array3X32 := ( others = > ( others = > ' 0 ' ) )
cmsCRC_initp	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
cmsCRC_init	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
cmsCRC_ce	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
cmsCRC_err	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
cmsCRC_errCntr	array3X32 := ( others = > ( others = > ' 0 ' ) )
SFP_we	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
EoB	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
EoE	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
SFP_evt_cntr	array3X32 := ( others = > ( others = > ' 0 ' ) )
SFP_blk_cntr	array3X32 := ( others = > ( others = > ' 0 ' ) )
SFP_word_cntr	array3X32 := ( others = > ( others = > ' 0 ' ) )
TotalEvtLengthCntr24q	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
EvtLengthCntr	array3X24 := ( others = > ( others = > ' 0 ' ) )
EvtLength_errCntr	array3X32 := ( others = > ( others = > ' 0 ' ) )
AMClength_errCntr	array3X32 := ( others = > ( others = > ' 0 ' ) )
AMCvalid_errCntr	array3X32 := ( others = > ( others = > ' 0 ' ) )
AMCcrc_errCntr	array3X32 := ( others = > ( others = > ' 0 ' ) )
TotalEvtLengthCntr	array3X56 := ( others = > ( others = > ' 0 ' ) )
SFP_down_i	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
StopOverWrite	std_logic := ' 0 '
StopOnCMScrc_err	std_logic := ' 0 '
en_stop	std_logic_vector ( 4 downto 0 ) := ( others = > ' 1 ' )
stop	std_logic := ' 0 '
inc_err	array3x5 := ( others = > ( others = > ' 0 ' ) )
reset_cntr	std_logic_vector ( 20 downto 0 ) := ( others = > ' 0 ' )
SFP_pd_q	array3X4 := ( others = > ( others = > ' 0 ' ) )
soft_reset	std_logic := ' 0 '
reset_cntr20_q	std_logic := ' 0 '
SFP_rate_limit	array3x8 := ( others = >x " 7f " )
rate_limit	array3x8 := ( others = >x " 7f " )
TCPIP_cs	array3x512
cs_din	std_logic_vector ( 303 downto 0 ) := ( others = > ' 0 ' )
waitcntr	std_logic_vector ( 11 downto 0 ) := ( others = > ' 0 ' )
CONTROL0	std_logic_vector ( 35 downto 0 ) := ( others = > ' 0 ' )

Instantiations
i_check_event	check_event <Entity check_event>
i_FIFO_RESET_7S	FIFO_RESET_7S <Entity FIFO_RESET_7S>
i_cmsCRC	cmsCRC64 <Entity cmsCRC64>
i_TCPIP	TCPIP <Entity TCPIP>
i_RETXdata_chksum	RETXdata_chksum <Entity RETXdata_chksum>
i_RETX_ddr_rp	RAM32x6Db <Entity RAM32x6Db>
i_XGbEPCS	XGbEPCS32 <Entity XGbEPCS32>
i_SFP3_init	SFP3_v2_7_init <Entity SFP3_v2_7_init>

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Detailed Description

Definition at line 117 of file TCPIP_if.vhd.

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The documentation for this class was generated from the following files:

• src/TCPIP_if/TCPIP_if.vhd