RAM32x6D Entity Reference

Inheritance diagram for RAM32x6D:

List of all members.

Entities
Behavioral	architecture

Libraries
UNISIM

Use Clauses
VComponents

Ports
wclk	in STD_LOGIC
rclk	in STD_LOGIC
di	in STD_LOGIC_VECTOR ( 5 downto 0 )
we	in STD_LOGIC
wa	in STD_LOGIC_VECTOR ( 4 downto 0 )
ra	in STD_LOGIC_VECTOR ( 4 downto 0 )
ceReg	in STD_LOGIC
do	out STD_LOGIC_VECTOR ( 5 downto 0 )

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Detailed Description

Definition at line 32 of file RAM32x6D.vhd.

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The documentation for this class was generated from the following files:

• src/common/RAM/RAM32x6D.vhd
• src/TCPIP_if/RAM32x6D.vhd