AMC13
Firmwares for the different applications of the AMC13 uTCA board made at Boston University
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TCPIP_if.vhd
1 ----------------------------------------------------------------------------------
2 -- Company:
3 -- Engineer:
4 --
5 -- Create Date: 14:07:47 10/07/2013
6 -- Design Name:
7 -- Module Name: TCPIP_if - Behavioral
8 -- Project Name:
9 -- Target Devices:
10 -- Tool versions:
11 -- Description:
12 --
13 -- Dependencies:
14 --
15 -- Revision:
16 -- Revision 0.01 - File Created
17 -- Additional Comments:
18 --
19 ----------------------------------------------------------------------------------
20 library IEEE;
21 use IEEE.STD_LOGIC_1164.ALL;
22 use IEEE.STD_LOGIC_ARITH.ALL;
23 use IEEE.STD_LOGIC_UNSIGNED.ALL;
24 use IEEE.std_logic_misc.all;
25 use IEEE.numeric_std.all;
26 use work.amc13_pack.all;
27 
28 -- Uncomment the following library declaration if using
29 -- arithmetic functions with Signed or Unsigned values
30 --use IEEE.NUMERIC_STD.ALL;
31 
32 -- Uncomment the following library declaration if instantiating
33 -- any Xilinx primitives in this code.
34 library UNISIM;
35 use UNISIM.VComponents.all;
36 Library UNIMACRO;
37 use UNIMACRO.vcomponents.all;
38 
39 entity TCPIP_if is
40  generic (simulation : boolean := false; en_KEEPALIVE : std_logic := '0');
41  Port ( sysclk : in STD_LOGIC;
42  DRPclk : in STD_LOGIC;
43  reset : in STD_LOGIC;
44  TCPreset : in STD_LOGIC;
45  rstCntr : in STD_LOGIC;
46  test : in STD_LOGIC;
47  SN : IN std_logic_vector(8 downto 0);
48  Dis_pd : in STD_LOGIC;
49  enSFP : IN std_logic_vector(3 downto 0);
50  SFP_down : OUT std_logic_vector(2 downto 0);
51  inc_ddr_pa : in STD_LOGIC;
52 -- event data in
53  evt_data_rdy : in std_logic_vector(2 downto 0);
54  EventData_in : in array3X67;
55  EventData_we : in std_logic_VECTOR(2 downto 0);
56  EventData_re : out std_logic_VECTOR(2 downto 0); --
57  evt_buf_full : out std_logic_vector(2 downto 0);
58  buf_rqst : in std_logic_vector(3 downto 0);
59  WaitMonBuf : IN std_logic;
60  MonBufOverWrite : in STD_LOGIC;
61  TCPBuf_avl : out STD_LOGIC;
62  MonBuf_avl : out STD_LOGIC;
63  MonBuf_empty : out STD_LOGIC;
64  MonBufOvfl : out STD_LOGIC;
65  mon_evt_cnt : out std_logic_vector(31 downto 0);
66  WrtMonBlkDone : in STD_LOGIC_VECTOR(2 downto 0);
67  WrtMonEvtDone : in STD_LOGIC_VECTOR(2 downto 0);
68  KiloByte_toggle : in STD_LOGIC_VECTOR(2 downto 0);
69  EoB_toggle : in STD_LOGIC_VECTOR(2 downto 0);
70 -- ddr wportA status
71  wport_rdy : in std_logic_vector(2 downto 0);
72  wport_FIFO_full : in std_logic_vector(2 downto 0);
73 -- signal to ddr_if, AMC_if to start moving data
74  EventBufAddr_we : out std_logic_VECTOR(2 downto 0);
75  EventBufAddr : out array3X14;
76 -- ddr wportB signals in sysclk domain
77  TCPclk : out STD_LOGIC;
78  TCP_dout : out std_logic_vector(31 downto 0); -- TCP data are written in unit of 32-bit words
79  TCP_channel : out std_logic_vector(1 downto 0); -- Each entry has four 32bit words, each address saves two entries. Addresses are kept in ddr_wportB
80  TCP_we : out STD_LOGIC;
81  TCP_wcount : in STD_LOGIC_VECTOR (2 downto 0);
82 -- ddr rport signals
83  TCP_raddr : out STD_LOGIC_VECTOR(28 downto 0); -- 28-26 encoded request source 25-0 address in 64 bit word
84  TCP_length : out STD_LOGIC_VECTOR(12 downto 0); -- in 64 bit word, actual length - 1
85  TCP_rrqst : out STD_LOGIC;
86  TCP_rack : in STD_LOGIC;
87  TCP_din_type : in STD_LOGIC_VECTOR(2 downto 0); -- TCP data destination
88  TCP_din : in STD_LOGIC_VECTOR(31 downto 0); -- TCP data are written in unit of 32-bit words
89  TCP_din_valid : in STD_LOGIC;
90  TCP_lastword : in STD_LOGIC;
91 -- SFP ports
92  SFP0_RXN : in STD_LOGIC;
93  SFP0_RXP : in STD_LOGIC;
94  SFP1_RXN : in STD_LOGIC;
95  SFP1_RXP : in STD_LOGIC;
96  SFP2_RXN : in STD_LOGIC;
97  SFP2_RXP : in STD_LOGIC;
98  SFP0_TXN : out STD_LOGIC;
99  SFP0_TXP : out STD_LOGIC;
100  SFP1_TXN : out STD_LOGIC;
101  SFP1_TXP : out STD_LOGIC;
102  SFP2_TXN : out STD_LOGIC;
103  SFP2_TXP : out STD_LOGIC;
104  SFP_REFCLK_N : in STD_LOGIC;
105  SFP_REFCLK_P : in STD_LOGIC;
106  cs_out : out std_logic_vector(511 downto 0);
107 -- ipbus signals
108  ipb_clk : in STD_LOGIC;
109  ipb_write : in STD_LOGIC;
110  ipb_strobe : in STD_LOGIC;
111  ipb_addr : in STD_LOGIC_VECTOR(31 downto 0);
112  ipb_wdata : in STD_LOGIC_VECTOR(31 downto 0);
113  ipb_rdata : out STD_LOGIC_VECTOR(31 downto 0)
114  );
115 end TCPIP_if;
116 
117 architecture Behavioral of TCPIP_if is
118 COMPONENT TCPIP
119  generic (simulation : boolean := false; en_KEEPALIVE : std_logic := '0');
120  PORT(
121  reset : IN std_logic;
122  rstCntr : in STD_LOGIC;
123  sysclk : IN std_logic;
124  clk2x : IN std_logic;
125  clk : IN std_logic;
126  strobe_us : IN std_logic;
127  strobe_ms : IN std_logic;
128  en_LINK : IN std_logic;
129  MY_PORT : IN std_logic_vector(15 downto 0);
130  MY_IP : IN std_logic_vector(31 downto 0);
131  MY_ETH : IN std_logic_vector(47 downto 0);
132 -- CWND_max : IN std_logic_vector(31 downto 0);
133  RTOmin : IN std_logic_vector(15 downto 0);
134  rate_limit : IN std_logic_vector(7 downto 0);
135  TSclock : IN std_logic_vector(31 downto 0);
136  EVENTdata : IN std_logic_vector(66 downto 0);
137  EventBufAddr : IN std_logic_vector(13 downto 0);
138  EventBufAddr_we : IN std_logic;
139  AddrBuf_full : OUT std_logic;
140  EVENTdata_avl : IN std_logic;
141  DDR2TCPdata : IN std_logic_vector(32 downto 0);
142  RETXdata_we : IN std_logic_vector(1 downto 0);
143  RETXdata_chksum : IN std_logic_vector(15 downto 0);
144  re_RETX_ddr_wq : IN std_logic;
145  RETX_ddr_data_we : IN std_logic;
146  RETXdataACK : IN std_logic;
147  KiloByte_toggle : in STD_LOGIC;
148  EoB_toggle : in STD_LOGIC;
149  TCP_wcount : in STD_LOGIC;
150  PhyEmacRxC : IN std_logic_vector(3 downto 0);
151  PhyEmacRxD : IN std_logic_vector(31 downto 0);
152  LINK_down : OUT std_logic;
153  EVENTdata_re : OUT std_logic;
154  RETX_ddr_out : OUT std_logic_vector(31 downto 0);
155  RETX_ddr_wrqst : OUT std_logic;
156  RETX_ddr_LEN_max : IN std_logic_vector(4 downto 0);
157  RETX_ddr_LEN : OUT std_logic_vector(4 downto 0);
158  RETX_ddr_rrqst : OUT std_logic;
159  RETXdataRqst : OUT std_logic;
160  RETXdataAddr : OUT std_logic_vector(25 downto 0);
161  RETXdataLEN : OUT std_logic_vector(12 downto 0);
162  UNA_MonBuf : OUT std_logic_vector(10 downto 0);
163  UNA_TCPBuf : OUT std_logic_vector(10 downto 0);
164  EmacPhyTxC : OUT std_logic_vector(3 downto 0);
165  EmacPhyTxD : OUT std_logic_vector(31 downto 0);
166  ipb_addr : in STD_LOGIC_VECTOR(31 downto 0);
167  ipb_rdata : out STD_LOGIC_VECTOR(31 downto 0);
168  cs_out : OUT std_logic_vector(511 downto 0)
169  );
170 END COMPONENT;
171 COMPONENT XGbEPCS32
172  PORT(
173  reset : IN std_logic;
174  clk2x : IN std_logic;
175  clk : IN std_logic;
176  TXUSRCLK : IN std_logic;
177  TX_high : IN std_logic;
178  RXUSRCLK : IN std_logic;
179  RXRESETDONE : IN std_logic;
180  inh_TX : IN std_logic;
181  RESET_TXSync : IN std_logic;
182  GTX_TXD : OUT std_logic_vector(31 downto 0);
183  GTX_TXHEADER : OUT std_logic_vector(1 downto 0);
184  GTX_TX_PAUSE : IN std_logic;
185  GTX_RXD : IN std_logic_vector(31 downto 0);
186  GTX_RXDVLD : IN std_logic;
187  GTX_RXHEADER : IN std_logic_vector(1 downto 0);
188  GTX_RXHEADERVLD : IN std_logic;
189  GTX_RXGOOD : OUT std_logic;
190  GTX_RXGEARBOXSLIP_OUT : OUT std_logic;
191  EmacPhyTxC : IN std_logic_vector(3 downto 0);
192  EmacPhyTxD : IN std_logic_vector(31 downto 0);
193  PhyEmacRxC : OUT std_logic_vector(3 downto 0);
194  PhyEmacRxD : OUT std_logic_vector(31 downto 0)
195  );
196 END COMPONENT;
197 COMPONENT FIFO_RESET_7S
198  PORT(
199  reset : IN std_logic;
200  clk : IN std_logic;
201  fifo_rst : OUT std_logic;
202  fifo_en : OUT std_logic
203  );
204 END COMPONENT;
205 component SFP3_v2_7_init
206 generic
207 (
208  EXAMPLE_SIM_GTRESET_SPEEDUP : string := "TRUE"; -- simulation setting for GT SecureIP model
209  EXAMPLE_SIMULATION : integer := 0; -- Set to 1 for simulation
210  STABLE_CLOCK_PERIOD : integer := 20; --Period of the stable clock driving this state-machine, unit is [ns]
211  EXAMPLE_USE_CHIPSCOPE : integer := 0 -- Set to 1 to use Chipscope to drive resets
212 
213 );
214 port
215 (
216  SYSCLK_IN : in std_logic;
217  SOFT_RESET_IN : in std_logic;
218  DONT_RESET_ON_DATA_ERROR_IN : in std_logic;
219  GT0_TX_FSM_RESET_DONE_OUT : out std_logic;
220  GT0_RX_FSM_RESET_DONE_OUT : out std_logic;
221  GT0_DATA_VALID_IN : in std_logic;
222  GT1_TX_FSM_RESET_DONE_OUT : out std_logic;
223  GT1_RX_FSM_RESET_DONE_OUT : out std_logic;
224  GT1_DATA_VALID_IN : in std_logic;
225  GT2_TX_FSM_RESET_DONE_OUT : out std_logic;
226  GT2_RX_FSM_RESET_DONE_OUT : out std_logic;
227  GT2_DATA_VALID_IN : in std_logic;
228 
229  --_________________________________________________________________________
230  --GT0 (X1Y12)
231  --____________________________CHANNEL PORTS________________________________
232  ---------------------------- Channel - DRP Ports --------------------------
233  GT0_DRPADDR_IN : in std_logic_vector(8 downto 0);
234  GT0_DRPCLK_IN : in std_logic;
235  GT0_DRPDI_IN : in std_logic_vector(15 downto 0);
236  GT0_DRPDO_OUT : out std_logic_vector(15 downto 0);
237  GT0_DRPEN_IN : in std_logic;
238  GT0_DRPRDY_OUT : out std_logic;
239  GT0_DRPWE_IN : in std_logic;
240  ------------------------------- Loopback Ports -----------------------------
241  GT0_LOOPBACK_IN : in std_logic_vector(2 downto 0);
242  ------------------------------ Power-Down Ports ----------------------------
243  GT0_RXPD_IN : in std_logic_vector(1 downto 0);
244  GT0_TXPD_IN : in std_logic_vector(1 downto 0);
245  --------------------- RX Initialization and Reset Ports --------------------
246  GT0_RXUSERRDY_IN : in std_logic;
247  -------------------------- RX Margin Analysis Ports ------------------------
248  GT0_EYESCANDATAERROR_OUT : out std_logic;
249  ------------------------- Receive Ports - CDR Ports ------------------------
250  GT0_RXCDRLOCK_OUT : out std_logic;
251  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
252  GT0_RXUSRCLK_IN : in std_logic;
253  GT0_RXUSRCLK2_IN : in std_logic;
254  ------------------ Receive Ports - FPGA RX interface Ports -----------------
255  GT0_RXDATA_OUT : out std_logic_vector(31 downto 0);
256  ------------------- Receive Ports - Pattern Checker Ports ------------------
257  GT0_RXPRBSERR_OUT : out std_logic;
258  GT0_RXPRBSSEL_IN : in std_logic_vector(2 downto 0);
259  ------------------- Receive Ports - Pattern Checker ports ------------------
260  GT0_RXPRBSCNTRESET_IN : in std_logic;
261  --------------------------- Receive Ports - RX AFE -------------------------
262  GT0_GTXRXP_IN : in std_logic;
263  ------------------------ Receive Ports - RX AFE Ports ----------------------
264  GT0_GTXRXN_IN : in std_logic;
265  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
266  GT0_RXBUFRESET_IN : in std_logic;
267  GT0_RXBUFSTATUS_OUT : out std_logic_vector(2 downto 0);
268  --------------- Receive Ports - RX Fabric Output Control Ports -------------
269  GT0_RXOUTCLK_OUT : out std_logic;
270  ---------------------- Receive Ports - RX Gearbox Ports --------------------
271  GT0_RXDATAVALID_OUT : out std_logic;
272  GT0_RXHEADER_OUT : out std_logic_vector(1 downto 0);
273  GT0_RXHEADERVALID_OUT : out std_logic;
274  --------------------- Receive Ports - RX Gearbox Ports --------------------
275  GT0_RXGEARBOXSLIP_IN : in std_logic;
276  ------------- Receive Ports - RX Initialization and Reset Ports ------------
277  GT0_GTRXRESET_IN : in std_logic;
278  GT0_RXPMARESET_IN : in std_logic;
279  ------------------ Receive Ports - RX Margin Analysis ports ----------------
280  GT0_RXLPMEN_IN : in std_logic;
281  -------------- Receive Ports -RX Initialization and Reset Ports ------------
282  GT0_RXRESETDONE_OUT : out std_logic;
283  --------------------- TX Initialization and Reset Ports --------------------
284  GT0_GTTXRESET_IN : in std_logic;
285  GT0_TXUSERRDY_IN : in std_logic;
286  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
287  GT0_TXUSRCLK_IN : in std_logic;
288  GT0_TXUSRCLK2_IN : in std_logic;
289  --------------- Transmit Ports - TX Configurable Driver Ports --------------
290  GT0_TXDIFFCTRL_IN : in std_logic_vector(3 downto 0);
291  GT0_TXINHIBIT_IN : in std_logic;
292  GT0_TXMAINCURSOR_IN : in std_logic_vector(6 downto 0);
293  ------------------ Transmit Ports - TX Data Path interface -----------------
294  GT0_TXDATA_IN : in std_logic_vector(31 downto 0);
295  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
296  GT0_GTXTXN_OUT : out std_logic;
297  GT0_GTXTXP_OUT : out std_logic;
298  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
299  GT0_TXOUTCLK_OUT : out std_logic;
300  GT0_TXOUTCLKFABRIC_OUT : out std_logic;
301  GT0_TXOUTCLKPCS_OUT : out std_logic;
302  --------------------- Transmit Ports - TX Gearbox Ports --------------------
303  GT0_TXHEADER_IN : in std_logic_vector(1 downto 0);
304  GT0_TXSEQUENCE_IN : in std_logic_vector(6 downto 0);
305  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
306  GT0_TXRESETDONE_OUT : out std_logic;
307  ------------------ Transmit Ports - pattern Generator Ports ----------------
308  GT0_TXPRBSSEL_IN : in std_logic_vector(2 downto 0);
309 
310  --GT1 (X1Y13)
311  --____________________________CHANNEL PORTS________________________________
312  ---------------------------- Channel - DRP Ports --------------------------
313  GT1_DRPADDR_IN : in std_logic_vector(8 downto 0);
314  GT1_DRPCLK_IN : in std_logic;
315  GT1_DRPDI_IN : in std_logic_vector(15 downto 0);
316  GT1_DRPDO_OUT : out std_logic_vector(15 downto 0);
317  GT1_DRPEN_IN : in std_logic;
318  GT1_DRPRDY_OUT : out std_logic;
319  GT1_DRPWE_IN : in std_logic;
320  ------------------------------- Loopback Ports -----------------------------
321  GT1_LOOPBACK_IN : in std_logic_vector(2 downto 0);
322  ------------------------------ Power-Down Ports ----------------------------
323  GT1_RXPD_IN : in std_logic_vector(1 downto 0);
324  GT1_TXPD_IN : in std_logic_vector(1 downto 0);
325  --------------------- RX Initialization and Reset Ports --------------------
326  GT1_RXUSERRDY_IN : in std_logic;
327  -------------------------- RX Margin Analysis Ports ------------------------
328  GT1_EYESCANDATAERROR_OUT : out std_logic;
329  ------------------------- Receive Ports - CDR Ports ------------------------
330  GT1_RXCDRLOCK_OUT : out std_logic;
331  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
332  GT1_RXUSRCLK_IN : in std_logic;
333  GT1_RXUSRCLK2_IN : in std_logic;
334  ------------------ Receive Ports - FPGA RX interface Ports -----------------
335  GT1_RXDATA_OUT : out std_logic_vector(31 downto 0);
336  ------------------- Receive Ports - Pattern Checker Ports ------------------
337  GT1_RXPRBSERR_OUT : out std_logic;
338  GT1_RXPRBSSEL_IN : in std_logic_vector(2 downto 0);
339  ------------------- Receive Ports - Pattern Checker ports ------------------
340  GT1_RXPRBSCNTRESET_IN : in std_logic;
341  --------------------------- Receive Ports - RX AFE -------------------------
342  GT1_GTXRXP_IN : in std_logic;
343  ------------------------ Receive Ports - RX AFE Ports ----------------------
344  GT1_GTXRXN_IN : in std_logic;
345  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
346  GT1_RXBUFRESET_IN : in std_logic;
347  GT1_RXBUFSTATUS_OUT : out std_logic_vector(2 downto 0);
348  --------------- Receive Ports - RX Fabric Output Control Ports -------------
349  GT1_RXOUTCLK_OUT : out std_logic;
350  ---------------------- Receive Ports - RX Gearbox Ports --------------------
351  GT1_RXDATAVALID_OUT : out std_logic;
352  GT1_RXHEADER_OUT : out std_logic_vector(1 downto 0);
353  GT1_RXHEADERVALID_OUT : out std_logic;
354  --------------------- Receive Ports - RX Gearbox Ports --------------------
355  GT1_RXGEARBOXSLIP_IN : in std_logic;
356  ------------- Receive Ports - RX Initialization and Reset Ports ------------
357  GT1_GTRXRESET_IN : in std_logic;
358  GT1_RXPMARESET_IN : in std_logic;
359  ------------------ Receive Ports - RX Margin Analysis ports ----------------
360  GT1_RXLPMEN_IN : in std_logic;
361  -------------- Receive Ports -RX Initialization and Reset Ports ------------
362  GT1_RXRESETDONE_OUT : out std_logic;
363  --------------------- TX Initialization and Reset Ports --------------------
364  GT1_GTTXRESET_IN : in std_logic;
365  GT1_TXUSERRDY_IN : in std_logic;
366  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
367  GT1_TXUSRCLK_IN : in std_logic;
368  GT1_TXUSRCLK2_IN : in std_logic;
369  --------------- Transmit Ports - TX Configurable Driver Ports --------------
370  GT1_TXDIFFCTRL_IN : in std_logic_vector(3 downto 0);
371  GT1_TXINHIBIT_IN : in std_logic;
372  GT1_TXMAINCURSOR_IN : in std_logic_vector(6 downto 0);
373  ------------------ Transmit Ports - TX Data Path interface -----------------
374  GT1_TXDATA_IN : in std_logic_vector(31 downto 0);
375  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
376  GT1_GTXTXN_OUT : out std_logic;
377  GT1_GTXTXP_OUT : out std_logic;
378  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
379  GT1_TXOUTCLK_OUT : out std_logic;
380  GT1_TXOUTCLKFABRIC_OUT : out std_logic;
381  GT1_TXOUTCLKPCS_OUT : out std_logic;
382  --------------------- Transmit Ports - TX Gearbox Ports --------------------
383  GT1_TXHEADER_IN : in std_logic_vector(1 downto 0);
384  GT1_TXSEQUENCE_IN : in std_logic_vector(6 downto 0);
385  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
386  GT1_TXRESETDONE_OUT : out std_logic;
387  ------------------ Transmit Ports - pattern Generator Ports ----------------
388  GT1_TXPRBSSEL_IN : in std_logic_vector(2 downto 0);
389 
390  --GT2 (X1Y14)
391  --____________________________CHANNEL PORTS________________________________
392  ---------------------------- Channel - DRP Ports --------------------------
393  GT2_DRPADDR_IN : in std_logic_vector(8 downto 0);
394  GT2_DRPCLK_IN : in std_logic;
395  GT2_DRPDI_IN : in std_logic_vector(15 downto 0);
396  GT2_DRPDO_OUT : out std_logic_vector(15 downto 0);
397  GT2_DRPEN_IN : in std_logic;
398  GT2_DRPRDY_OUT : out std_logic;
399  GT2_DRPWE_IN : in std_logic;
400  ------------------------------- Loopback Ports -----------------------------
401  GT2_LOOPBACK_IN : in std_logic_vector(2 downto 0);
402  ------------------------------ Power-Down Ports ----------------------------
403  GT2_RXPD_IN : in std_logic_vector(1 downto 0);
404  GT2_TXPD_IN : in std_logic_vector(1 downto 0);
405  --------------------- RX Initialization and Reset Ports --------------------
406  GT2_RXUSERRDY_IN : in std_logic;
407  -------------------------- RX Margin Analysis Ports ------------------------
408  GT2_EYESCANDATAERROR_OUT : out std_logic;
409  ------------------------- Receive Ports - CDR Ports ------------------------
410  GT2_RXCDRLOCK_OUT : out std_logic;
411  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
412  GT2_RXUSRCLK_IN : in std_logic;
413  GT2_RXUSRCLK2_IN : in std_logic;
414  ------------------ Receive Ports - FPGA RX interface Ports -----------------
415  GT2_RXDATA_OUT : out std_logic_vector(31 downto 0);
416  ------------------- Receive Ports - Pattern Checker Ports ------------------
417  GT2_RXPRBSERR_OUT : out std_logic;
418  GT2_RXPRBSSEL_IN : in std_logic_vector(2 downto 0);
419  ------------------- Receive Ports - Pattern Checker ports ------------------
420  GT2_RXPRBSCNTRESET_IN : in std_logic;
421  --------------------------- Receive Ports - RX AFE -------------------------
422  GT2_GTXRXP_IN : in std_logic;
423  ------------------------ Receive Ports - RX AFE Ports ----------------------
424  GT2_GTXRXN_IN : in std_logic;
425  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
426  GT2_RXBUFRESET_IN : in std_logic;
427  GT2_RXBUFSTATUS_OUT : out std_logic_vector(2 downto 0);
428  --------------- Receive Ports - RX Fabric Output Control Ports -------------
429  GT2_RXOUTCLK_OUT : out std_logic;
430  ---------------------- Receive Ports - RX Gearbox Ports --------------------
431  GT2_RXDATAVALID_OUT : out std_logic;
432  GT2_RXHEADER_OUT : out std_logic_vector(1 downto 0);
433  GT2_RXHEADERVALID_OUT : out std_logic;
434  --------------------- Receive Ports - RX Gearbox Ports --------------------
435  GT2_RXGEARBOXSLIP_IN : in std_logic;
436  ------------- Receive Ports - RX Initialization and Reset Ports ------------
437  GT2_GTRXRESET_IN : in std_logic;
438  GT2_RXPMARESET_IN : in std_logic;
439  ------------------ Receive Ports - RX Margin Analysis ports ----------------
440  GT2_RXLPMEN_IN : in std_logic;
441  -------------- Receive Ports -RX Initialization and Reset Ports ------------
442  GT2_RXRESETDONE_OUT : out std_logic;
443  --------------------- TX Initialization and Reset Ports --------------------
444  GT2_GTTXRESET_IN : in std_logic;
445  GT2_TXUSERRDY_IN : in std_logic;
446  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
447  GT2_TXUSRCLK_IN : in std_logic;
448  GT2_TXUSRCLK2_IN : in std_logic;
449  --------------- Transmit Ports - TX Configurable Driver Ports --------------
450  GT2_TXDIFFCTRL_IN : in std_logic_vector(3 downto 0);
451  GT2_TXINHIBIT_IN : in std_logic;
452  GT2_TXMAINCURSOR_IN : in std_logic_vector(6 downto 0);
453  ------------------ Transmit Ports - TX Data Path interface -----------------
454  GT2_TXDATA_IN : in std_logic_vector(31 downto 0);
455  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
456  GT2_GTXTXN_OUT : out std_logic;
457  GT2_GTXTXP_OUT : out std_logic;
458  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
459  GT2_TXOUTCLK_OUT : out std_logic;
460  GT2_TXOUTCLKFABRIC_OUT : out std_logic;
461  GT2_TXOUTCLKPCS_OUT : out std_logic;
462  --------------------- Transmit Ports - TX Gearbox Ports --------------------
463  GT2_TXHEADER_IN : in std_logic_vector(1 downto 0);
464  GT2_TXSEQUENCE_IN : in std_logic_vector(6 downto 0);
465  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
466  GT2_TXRESETDONE_OUT : out std_logic;
467  ------------------ Transmit Ports - pattern Generator Ports ----------------
468  GT2_TXPRBSSEL_IN : in std_logic_vector(2 downto 0);
469 
470 
471  --____________________________COMMON PORTS________________________________
472  ---------------------- Common Block - Ref Clock Ports ---------------------
473  GT0_GTREFCLK0_COMMON_IN : in std_logic;
474  ------------------------- Common Block - QPLL Ports ------------------------
475  GT0_QPLLLOCK_OUT : out std_logic;
476  GT0_QPLLLOCKDETCLK_IN : in std_logic;
477  GT0_QPLLRESET_IN : in std_logic
478 
479 
480 );
481 end component;
482 COMPONENT RETXdata_chksum
483  PORT(
484  c : IN std_logic;
485  r : IN std_logic;
486  ce : IN std_logic;
487  d : IN std_logic_vector(31 downto 0);
488  s : OUT std_logic_vector(15 downto 0)
489  );
490 END COMPONENT;
491 COMPONENT check_event
492  PORT(
493  clk : IN std_logic;
494  reset : IN std_logic;
495  en_stop : IN std_logic_vector(4 downto 0);
496  cmsCRC_err : IN std_logic_vector(2 downto 0);
497  EventData_in : IN array3X67;
498  EventData_we : IN std_logic_vector(2 downto 0);
499  inc_err : OUT array3X5;
500  stop : OUT std_logic
501  );
502 END COMPONENT;
503 COMPONENT RAM32x6D
504  PORT(
505  wclk : IN std_logic;
506  rclk : IN std_logic;
507  di : IN std_logic_vector(5 downto 0);
508  we : IN std_logic;
509  wa : IN std_logic_vector(4 downto 0);
510  ra : IN std_logic_vector(4 downto 0);
511  ceReg : IN std_logic;
512  do : OUT std_logic_vector(5 downto 0)
513  );
514 END COMPONENT;
515 COMPONENT RAM32x6Db
516  PORT(
517  wclk : IN std_logic;
518  di : IN std_logic_vector(5 downto 0);
519  we : IN std_logic;
520  wa : IN std_logic_vector(4 downto 0);
521  ra : IN std_logic_vector(4 downto 0);
522  do : OUT std_logic_vector(5 downto 0)
523  );
524 END COMPONENT;
525 COMPONENT cmsCRC64
526  PORT(
527  clk : IN std_logic;
528  reset : IN std_logic;
529  crc_init : IN std_logic;
530  trailer : IN std_logic;
531  crc_d : IN std_logic_vector(63 downto 0);
532  crc_ce : IN std_logic;
533  crc : OUT std_logic_vector(15 downto 0);
534  crc_err : OUT std_logic;
535  dout : OUT std_logic_vector(63 downto 0);
536  dout_vld : OUT std_logic
537  );
538 END COMPONENT;
539 signal resetSyncRegs : std_logic_vector(2 downto 0) := (others => '0');
540 signal ClientClk2XresetSyncRegs : std_logic_vector(2 downto 0) := (others => '0');
541 signal refclk : std_logic := '0';
542 signal REFCLK2XPLLRST : std_logic := '0';
543 signal refclk2x_in : std_logic := '0';
544 signal ClientClk2x_dcm : std_logic := '0';
545 signal ClientClk2x : std_logic := '0';
546 signal ClientClk_dcm : std_logic := '0';
547 signal ClientClk : std_logic := '0';
548 signal ClientClk_lock : std_logic := '0';
549 signal ClientClkToggle : std_logic := '0';
550 signal ClientClkToggle_q : std_logic := '0';
551 signal FIFO_rst : std_logic := '0';
552 signal FIFO_en : std_logic := '0';
553 signal TX_high : std_logic := '0';
554 signal us_cntr : std_logic_vector(9 downto 0) := (others => '0');
555 signal ms_cntr : std_logic_vector(10 downto 0) := (others => '0');
556 signal strobe_us : std_logic := '0';
557 signal strobe_ms : std_logic := '0';
558 signal TSclock : std_logic_vector(31 downto 0) := (others => '0');
559 signal evt_FIFO_full : std_logic_vector(2 downto 0) := (others => '0');
560 signal evt_FIFO_empty : std_logic_vector(2 downto 0) := (others => '0');
561 signal evt_FIFO_we : std_logic_vector(2 downto 0) := (others => '0');
562 signal evt_FIFO_re : std_logic_vector(2 downto 0) := (others => '0');
563 signal evt_FIFO_rep : std_logic_vector(2 downto 0) := (others => '0');
564 signal evt_FIFO_data_avl : std_logic_vector(2 downto 0) := (others => '0');
565 signal evt_FIFO_di : array3X67 := (others => (others => '0'));
566 signal evt_FIFO_do : array3X67 := (others => (others => '0'));
567 signal evt_FIFO_RDCOUNT : array3X9 := (others => (others => '0'));
568 signal evt_FIFO_WRCOUNT : array3X9 := (others => (others => '0'));
569 signal EVENTdata_avl : std_logic_vector(2 downto 0) := (others => '0');
570 signal EVENTdata_addr : array3X13 := (others => (others => '0'));
571 signal re_RETX_ddr_wq : std_logic_vector(2 downto 0) := (others => '0');
572 signal RETX_ddr_data_we : std_logic_vector(2 downto 0) := (others => '0');
573 signal RETX_ddr_wrqst : std_logic_vector(2 downto 0) := (others => '0');
574 signal RETX_ddr_rrqst : std_logic_vector(2 downto 0) := (others => '0');
575 signal RETX_ddr_out : array3X32 := (others => (others => '0'));
576 signal RETX_ddr_LEN_max : array3X5 := (others => (others => '0'));
577 signal RETX_ddr_LEN : array3X5 := (others => (others => '0'));
578 signal RETXdata_we : array3X2 := (others => (others => '0'));
579 signal DDR2TCPdata : std_logic_vector(32 downto 0) := (others => '0');
580 signal rst_RETXdata_chksum : std_logic := '0';
581 signal RETXdata_chksum_out : std_logic_vector(15 downto 0) := (others => '0');
582 signal RETXdata_checksum : array3x16 := (others => (others => '0'));
583 signal RETXdataLEN : array3X13 := (others => (others => '0'));
584 signal RETXdataAddr : array3X26 := (others => (others => '0'));
585 signal RETXdata_space : std_logic_vector(2 downto 0) := (others => '0');
586 signal RETXdataRqst : std_logic_vector(2 downto 0) := (others => '0');
587 signal RETXdataACK : std_logic_vector(2 downto 0) := (others => '0');
588 signal ReleaseLen : array3X11 := (others => (others => '0'));
589 signal Release_space : std_logic_vector(2 downto 0) := (others => '0');
590 signal ReleaseBuffer : std_logic_vector(2 downto 0) := (others => '0');
591 signal Release_rqst: std_logic_vector(2 downto 0) := (others => '0');
592 signal rrqstMask : std_logic_vector(5 downto 0) := (others => '0');
593 signal TCP_rrqst_i : std_logic_vector(2 downto 0) := (others => '0');
594 signal odd : std_logic := '0';
595 signal rst_odd : std_logic := '0';
596 --signal DDR2TCPdata_vld : std_logic := '0';
597 signal TCP_rFIFO_do_vld : std_logic := '0';
598 signal ld_RETXdata_chksum : std_logic_vector(2 downto 0) := (others => '0');
599 signal ld_RETXdata_chksum_r : std_logic_vector(2 downto 0) := (others => '0');
600 signal ld_RETXdata_chksum_r2 : std_logic_vector(2 downto 0) := (others => '0');
601 signal TCP_rFIFO_wa0SyncRegs : std_logic_vector(3 downto 0) := (others => '0');
602 signal TCP_rFIFO_wa1SyncRegs : std_logic_vector(3 downto 0) := (others => '0');
603 signal TCP_rFIFO_wa2SyncRegs : std_logic_vector(3 downto 0) := (others => '0');
604 signal TCP_rFIFO_di : std_logic_vector(35 downto 0) := (others => '0');
605 signal TCP_rFIFO_do : std_logic_vector(35 downto 0) := (others => '0');
606 signal TCP_rFIFO_wa : std_logic_vector(4 downto 0) := (others => '0');
607 signal TCP_rFIFO_ra : std_logic_vector(4 downto 0) := (others => '0');
608 signal RETX_ddr_rp_rst : std_logic := '0';
609 signal RETX_ddr_rp_we : std_logic := '0';
610 signal RETX_ddr_rp_di : std_logic_vector(17 downto 0) := (others => '0');
611 signal RETX_ddr_rp_do : std_logic_vector(17 downto 0) := (others => '0');
612 signal RETX_ddr_rp_a : std_logic_vector(4 downto 0) := (others => '0');
613 signal TCP_length_i : std_logic_vector(20 downto 0) := (others => '0');
614 signal TCP_raddr_i : std_logic_vector(28 downto 0) := (others => '0');
615 signal TCP_rlength : std_logic_vector(12 downto 0) := (others => '0');
616 --signal rdDDRqueue_we : std_logic := '0';
617 --signal rdDDRqueue_re : std_logic := '0';
618 --signal rdDDRqueue_a : std_logic_vector(2 downto 0) := (others => '0');
619 --signal rdDDRqueue_di : std_logic_vector(2 downto 0) := (others => '0');
620 --signal rdDDRqueue_do : std_logic_vector(2 downto 0) := (others => '0');
621 --signal rdDDRqueue_dout : std_logic_vector(2 downto 0) := (others => '0');
622 --signal rdDDRqueue_dout_vld : std_logic := '0';
623 signal TCP_wFIFO_re : std_logic := '0';
624 signal TCP_w_busy : std_logic := '0';
625 signal TCP_wFIFO_we : std_logic := '0';
626 signal TCP_w_sel : std_logic_vector(1 downto 0) := (others => '0');
627 signal TCP_w_wc : std_logic_vector(3 downto 0) := (others => '0');
628 signal TCP_wFIFO_DI : std_logic_vector(33 downto 0) := (others => '0');
629 signal TCP_wFIFO_DO : std_logic_vector(33 downto 0) := (others => '0');
630 signal TCP_wFIFO_RDCOUNT : std_logic_vector(8 downto 0) := (others => '0');
631 signal TCP_wFIFO_WRCOUNT : std_logic_vector(8 downto 0) := (others => '0');
632 signal inh_TX : std_logic_vector(2 downto 0) := (others => '0');
633 signal inh_TX_q : std_logic_vector(2 downto 0) := (others => '0');
634 signal reset_TXSyncRegs : std_logic_vector(2 downto 0) := (others => '0');
635 signal SFP_TXOUTCLK : std_logic_vector(2 downto 0) := (others => '0');
636 signal txusrclk : std_logic := '0';
637 signal qplllock : std_logic := '0';
638 signal qpllreset : std_logic := '0';
639 signal GTX_TX_READ : std_logic := '0';
640 signal LINK_down : std_logic_vector(2 downto 0) := (others => '0');
641 signal EnTCPIP : std_logic_vector(2 downto 0) := (others => '0');
642 signal SFP_rxoutclk : std_logic_vector(2 downto 0) := (others => '0');
643 signal SFP_rxusrclk : std_logic_vector(2 downto 0) := (others => '0');
644 signal SFP_txuserrdy : std_logic_vector(2 downto 0) := (others => '0');
645 signal SFP_rxresetdone : std_logic_vector(2 downto 0) := (others => '0');
646 signal SFP_rxuserrdy : std_logic_vector(2 downto 0) := (others => '0');
647 signal SFP_drprdy : std_logic_vector(2 downto 0) := (others => '0');
648 signal SFP_drpen : std_logic_vector(2 downto 0) := (others => '0');
649 signal SFP_drpwe : std_logic_vector(2 downto 0) := (others => '0');
650 signal SFP_rxdfeagchold : std_logic_vector(2 downto 0) := (others => '0');
651 signal SFP_adapt_done : std_logic_vector(2 downto 0) := (others => '0');
652 signal SFP_rxmonitor : array3X7 := (others => (others => '0'));
653 signal SFP_drpdo : array3X16 := (others => (others => '0'));
654 signal SFP_rxmonitorsel : array3X2 := (others => (others => '0'));
655 signal SFP_drpaddr : array3X9 := (others => (others => '0'));
656 signal SFP_drpdi : array3X16 := (others => (others => '0'));
657 signal SFP_RX_FSM_RESET_DONE : std_logic_vector(2 downto 0) := (others => '0');
658 signal SFP_TX_FSM_RESET_DONE : std_logic_vector(2 downto 0) := (others => '0');
659 signal SFP_RXDVLD : std_logic_vector(2 downto 0) := (others => '0');
660 signal SFP_RXHEADERVLD : std_logic_vector(2 downto 0) := (others => '0');
661 signal SFP_RXGEARBOXSLIP : std_logic_vector(2 downto 0) := (others => '0');
662 signal SFP_RXGOOD : std_logic_vector(2 downto 0) := (others => '0');
663 signal SFP_TXD : array3X32 := (others => (others => '0'));
664 signal SFP_TXD_inv : array3X32 := (others => (others => '0'));
665 signal SFP_TXHEADER : array3X2 := (others => (others => '0'));
666 signal SFP_RXD : array3X32 := (others => (others => '0'));
667 signal SFP_RXD_inv : array3X32 := (others => (others => '0'));
668 signal SFP_RXHEADER : array3X2 := (others => (others => '0'));
669 signal SFP_EmacPhyTxD : array3X32 := (others => (others => '0'));
670 signal SFP_EmacPhyTxC : array3X4 := (others => (others => '0'));
671 signal SFP_PhyEmacRxD : array3X32 := (others => (others => '0'));
672 signal SFP_PhyEmacRxC : array3X4 := (others => (others => '0'));
673 --signal PCS_status : array3X32 := (others => (others => '0'));
674 signal EmacPhyTxD : array3X32 := (others => (others => '0'));
675 signal EmacPhyTxC : array3X4 := (others => (others => '0'));
676 signal PhyEmacRxD : array3X32 := (others => (others => '0'));
677 signal PhyEmacRxC : array3X4 := (others => (others => '0'));
678 signal TCPIP2SFP_sel : array3X2 := (others => (others => '0'));
679 signal SFP2TCPIP : array3X2 := (others => (others => '0'));
680 signal IPADDR : array3X32 := (others => (others => '0'));
681 signal SFP_IPADDR : array3X32 := (x"c0a80120",x"c0a80121",x"c0a80122");
682 --signal CWND_max : std_logic_vector(31 downto 0) := x"0fffffff";
683 signal RTOmin : std_logic_vector(15 downto 0) := x"0008";
684 signal MACADDR : array3X48 := (others => (others => '0'));
685 signal GTX_TX_PAUSE : std_logic := '0';
686 signal TXSEQ_cntr : std_logic_vector(6 downto 0) := (others => '0');
687 signal SFP_TXSEQUENCE : array3X7 := (others => (others => '0'));
688 signal SFP_LOOPBACK_IN : array3X3 := (others => (others => '0'));
689 signal SFP_RXPRBSERR_OUT : std_logic_vector(2 downto 0) := (others => '0');
690 signal SFP_RXPRBSSEL_IN : array3X3 := (others => (others => '0'));
691 signal SFP_TXPRBSSEL_IN : array3X3 := (others => (others => '0'));
692 signal SFP_EYESCANDATAERROR_OUT : std_logic_vector(2 downto 0) := (others => '0');
693 signal got_eofToggle : std_logic_vector(2 downto 0) := (others => '0');
694 signal EventBufAddr_we_i : std_logic_vector(2 downto 0) := (others => '0');
695 signal EventData_re_i : std_logic_vector(2 downto 0) := (others => '0');
696 signal EventBufAddr_i : array3X14 := (others => (others => '0'));
697 signal ReadBusy : std_logic_vector(2 downto 0) := (others => '0');
698 signal UNA_MonBufMatch : std_logic_vector(3 downto 0) := (others => '0');
699 signal UNA_TCPBufMatch : std_logic_vector(2 downto 0) := (others => '0');
700 signal UNA_MonBufSyncRegs : std_logic_vector(3 downto 0) := (others => '0');
701 signal UNA_TCPBufSyncRegs : std_logic_vector(3 downto 0) := (others => '0');
702 signal inc_ddr_paSyncRegs : std_logic_vector(3 downto 0) := (others => '0');
703 signal sysDIV2 : std_logic := '0';
704 signal evt_FIFO_sel : std_logic := '0';
705 signal ReleaseMonBuf : std_logic := '0';
706 signal ReleaseTCPBuf : std_logic := '0';
707 signal WrtMonBufAllDone_i : std_logic := '0';
708 --signal TCPBufCnt : std_logic_vector(12 downto 0) := (others => '0');
709 --signal MonBufCnt : std_logic_vector(12 downto 0) := (others => '0');
710 signal NXT_TCPBuf : array3X12 := (others => (others => '0'));
711 signal UNA_MonBuf : array5X11 := (others => (others => '0'));
712 signal UNA_TCPBuf : array4X11 := (others => (others => '0'));
713 signal AddrOffset : array3X10 := (others => (others => '0'));
714 signal SFPresetSyncRegs : array3X3 := (others => (others => '0'));
715 --signal TCPresetSyncRegs : array3X3 := (others => (others => '0'));
716 signal TCPresetSyncRegs : std_logic_vector(2 downto 0) := (others => '0');
717 signal got_eofToggle0SyncRegs : std_logic_vector(3 downto 0) := (others => '0');
718 signal reset_TCPIP : std_logic_vector(2 downto 0) := (others => '0');
719 signal got_eofToggle1SyncRegs : std_logic_vector(3 downto 0) := (others => '0');
720 signal got_eofToggle2SyncRegs : std_logic_vector(3 downto 0) := (others => '0');
721 signal TCPIP_rdata : array3X32 := (others => (others => '0'));
722 signal AddrBuf_full : std_logic_vector(2 downto 0) := (others => '0');
723 signal mon_evt_cnt_i : std_logic_vector(10 downto 0) := (others => '0');
724 signal MonBufUsed : std_logic_vector(9 downto 0) := (others => '0');
725 signal MonBuf_full : std_logic := '0';
726 signal chk_MonBuf_avl : std_logic := '0';
727 signal FirstBlkAddrDo : array2x3x12 := (others => (others => (others => '0')));
728 signal FirstBlkAddr_ra : array2x3x5 := (others => (others => (others => '0')));
729 signal FirstBlkAddr_re : array2X3 := (others => (others => '0'));
730 signal WrtMonEvtDone_l : std_logic_vector(2 downto 0) := (others => '0');
731 signal MonEvtQueued : std_logic_vector(2 downto 0) := (others => '0');
732 signal FirstBlkAddrDoValid : array2X3 := (others => (others => '0'));
733 signal FirstBlkAddr_wa : std_logic_vector(4 downto 0) := (others => '0');
734 signal FirstBlkAddrDi : std_logic_vector(11 downto 0) := (others => '0');
735 signal FirstBlkAddr_we : std_logic := '0';
736 signal MonBuf_wa : std_logic_vector(10 downto 0) := (others => '0');
737 signal MonBuf_ra : std_logic_vector(10 downto 0) := (others => '0');
738 signal NXT_MonBuf : array3X11 := (others => (others => '0'));
739 signal Written_MonBuf : array4X11 := (others => (others => '0'));
740 signal Written_MonBufMatch : std_logic_vector(2 downto 0) := (others => '0');
741 signal SFP_pd : array3X2 := (others => (others => '0'));
742 signal EventData_reCntr : array3X32 := (others => (others => '0'));
743 signal EventData_weCntr : array3X32 := (others => (others => '0'));
744 signal EventBufAddr_weCntr : array3X32 := (others => (others => '0'));
745 signal cmsCRC_initp : std_logic_vector(2 downto 0) := (others => '0');
746 signal cmsCRC_init : std_logic_vector(2 downto 0) := (others => '0');
747 signal cmsCRC_ce : std_logic_vector(2 downto 0) := (others => '0');
748 signal cmsCRC_err : std_logic_vector(2 downto 0) := (others => '0');
749 signal cmsCRC_errCntr : array3X32 := (others => (others => '0'));
750 signal SFP_we : std_logic_vector(2 downto 0) := (others => '0');
751 signal EoB : std_logic_vector(2 downto 0) := (others => '0');
752 signal EoE : std_logic_vector(2 downto 0) := (others => '0');
753 signal SFP_evt_cntr : array3X32 := (others => (others => '0'));
754 signal SFP_blk_cntr : array3X32 := (others => (others => '0'));
755 signal SFP_word_cntr : array3X32 := (others => (others => '0'));
756 --signal EvtLength_err : std_logic_vector(2 downto 0) := (others => '0');
757 signal TotalEvtLengthCntr24q : std_logic_vector(2 downto 0) := (others => '0');
758 signal EvtLengthCntr : array3X24 := (others => (others => '0'));
759 signal EvtLength_errCntr : array3X32 := (others => (others => '0'));
760 signal AMClength_errCntr : array3X32 := (others => (others => '0'));
761 signal AMCvalid_errCntr : array3X32 := (others => (others => '0'));
762 signal AMCcrc_errCntr : array3X32 := (others => (others => '0'));
763 signal TotalEvtLengthCntr : array3X56 := (others => (others => '0'));
764 signal SFP_down_i : std_logic_vector(2 downto 0) := (others => '0');
765 signal StopOverWrite : std_logic := '0';
766 signal StopOnCMScrc_err : std_logic := '0';
767 signal en_stop : std_logic_vector(4 downto 0) := (others => '1');
768 signal stop : std_logic := '0';
769 signal inc_err : array3x5 := (others => (others => '0'));
770 signal reset_cntr : std_logic_vector(20 downto 0) := (others => '0');
771 --signal Rx_start_cntr : std_logic_vector(31 downto 0) := (others => '0');
772 signal SFP_pd_q : array3X4 := (others => (others => '0'));
773 signal soft_reset : std_logic := '0';
774 signal reset_cntr20_q : std_logic := '0';
775 signal SFP_rate_limit : array3x8 := (others => x"7f");
776 signal rate_limit : array3x8 := (others => x"7f");
777 COMPONENT chipscope
778  generic (N : integer := 5);
779  PORT(
780  clka : IN std_logic;
781  clkb : IN std_logic;
782  ina : IN std_logic_vector(135 downto 0);
783  inb : IN std_logic_vector(135 downto 0)
784  );
785 END COMPONENT;
786 COMPONENT chipscope1
787  generic (N : integer := 5);
788  PORT(
789  clk : IN std_logic;
790  Din : IN std_logic_vector(303 downto 0)
791  );
792 END COMPONENT;
793 COMPONENT chipscope1b
794  generic (USER2 : boolean := false);
795  PORT(
796  clk : IN std_logic;
797  Din : IN std_logic_vector(303 downto 0)
798  );
799 END COMPONENT;
800 component icon1
801  PORT (
802  CONTROL0 : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0));
803 
804 end component;
805 component ila36x1024
806  PORT (
807  CONTROL : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0);
808  CLK : IN STD_LOGIC;
809  DATA : IN STD_LOGIC_VECTOR(35 DOWNTO 0);
810  TRIG0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0));
811 
812 end component;
813 
814 type array3x512 is array(0 to 2) of std_logic_vector(511 downto 0);
815 signal TCPIP_cs : array3x512;
816 signal cs_din : std_logic_vector(303 downto 0) := (others => '0');
817 signal waitcntr : std_logic_vector(11 downto 0) := (others => '0');
818 signal CONTROL0 : std_logic_vector(35 downto 0) := (others => '0');
819 begin
820 --i_icon1 : icon1
821 -- port map (
822 -- CONTROL0 => CONTROL0);
823 --i_ila36x1024 : ila36x1024
824 -- port map (
825 -- CONTROL => CONTROL0,
826 -- CLK => ClientClk2X,
827 -- DATA => TCPIP_cs(0)(35 downto 0),
828 -- TRIG0 => TCPIP_cs(0)(28 downto 21));
829 SFP_down(2) <= SFP_down_i(2) and not enSFP(3) and enSFP(2);
830 SFP_down(1) <= SFP_down_i(1) and not enSFP(3) and enSFP(1);
831 SFP_down(0) <= SFP_down_i(0) and not enSFP(3) and enSFP(0);
832 TCPclk <= ClientClk2X;
833 --MonBuf_avl <= MonBuf_avl_i;
834 MonBufOvfl <= '0';
835 EventBufAddr_we <= EventBufAddr_we_i;
836 EventData_re <= EventData_re_i;
837 mon_evt_cnt(31 downto 11) <= (others => '0');
838 mon_evt_cnt(10 downto 0) <= mon_evt_cnt_i;
839 EventBufAddr <= EventBufAddr_i;
840 TCP_rrqst <= TCP_rrqst_i(2);
841 TCP_raddr <= TCP_raddr_i;
842 --TCP_length <= TCP_rlength(9 downto 0);
843 TCP_length <= TCP_rlength;
844 process(sysclk,reset,ClientClk_lock)
845 begin
846  if(reset = '1' or ClientClk_lock = '0')then
847  resetSyncRegs <= (others => '1');
848  elsif(sysclk'event and sysclk = '1')then
849  resetSyncRegs <= resetSyncRegs(1 downto 0) & '0';
850  end if;
851 end process;
852 process(ClientClk2X,SFP_TX_FSM_RESET_DONE,SFP_RX_FSM_RESET_DONE)
853 begin
854  for i in 0 to 2 loop
855  if(SFP_TX_FSM_RESET_DONE(i) = '0' or SFP_RX_FSM_RESET_DONE(i) = '0')then
856  SFPresetSyncRegs(i) <= (others => '1');
857  elsif(ClientClk2X'event and ClientClk2X = '1')then
858  SFPresetSyncRegs(i) <= SFPresetSyncRegs(i)(1 downto 0) & '0';
859  end if;
860  end loop;
861 end process;
862 process(ClientClk2X,reset,ClientClk_lock)
863 begin
864  if(reset = '1' or ClientClk_lock = '0')then
865  ClientClk2XresetSyncRegs <= (others => '1');
866  elsif(ClientClk2X'event and ClientClk2X = '1')then
867  ClientClk2XresetSyncRegs <= ClientClk2XresetSyncRegs(1 downto 0) & '0';
868  end if;
869 end process;
870 --process(ClientClk,SFP_TX_FSM_RESET_DONE,ClientClk_lock)
871 --begin
872 -- for i in 0 to 2 loop
873 -- if(SFP_TX_FSM_RESET_DONE(i) = '0' or ClientClk_lock = '0')then
874 --process(ClientClk,TCPreset,ClientClk_lock)
875 --begin
876 -- for i in 0 to 2 loop
877 -- if(TCPreset = '1' or ClientClk_lock = '0')then
878 -- TCPresetSyncRegs(i) <= (others => '1');
879 -- elsif(ClientClk2X'event and ClientClk2X = '1')then
880 -- TCPresetSyncRegs(i) <= TCPresetSyncRegs(i)(1 downto 0) & '0';
881 -- end if;
882 -- end loop;
883 --end process;
884 process(ClientClk,TCPreset,ClientClk_lock)
885 begin
886  if(TCPreset = '1' or ClientClk_lock = '0')then
887  TCPresetSyncRegs <= (others => '1');
888  elsif(ClientClk'event and ClientClk = '1')then
889  TCPresetSyncRegs <= TCPresetSyncRegs(1 downto 0) & '0';
890  end if;
891 end process;
892 process(ClientClk)
893 begin
894  if(ClientClk'event and ClientClk = '1')then
895  ClientClkToggle <= not ClientClkToggle;
896 -- for i in 0 to 2 loop
897 -- if(TCPresetSyncRegs(2) = '1' or SFP_pd(i)(0) = '1')then
898 -- PCS_reset(i) <= '1';
899 -- elsif(SFP_TX_FSM_RESET_DONE(i) = '1')then
900 -- PCS_reset(i) <= '0';
901 -- end if;
902 -- end loop;
903  end if;
904 end process;
905 process(ClientClk2X)
906 begin
907  if(ClientClk2X'event and ClientClk2X = '1')then
908  ClientClkToggle_q <= ClientClkToggle;
909  TX_high <= ClientClkToggle_q xnor ClientClkToggle;
910  if(us_cntr(9) = '1')then
911  us_cntr <= "00" & x"c9";
912  TSclock <= TSclock + 1;
913  else
914  us_cntr <= us_cntr + 1;
915  end if;
916  if(us_cntr(9) = '1')then
917  if(ms_cntr(10) = '1')then
918  ms_cntr <= x"03" & "000";
919  else
920  ms_cntr <= ms_cntr + 1;
921  end if;
922  end if;
923  strobe_ms <= us_cntr(9) and ms_cntr(10);
924  end if;
925 end process;
926 strobe_us <= us_cntr(9);
927 process(txusrclk)
928 begin
929  if(txusrclk'event and txusrclk = '1')then
930  if(TXSEQ_cntr = "1000001")then
931  TXSEQ_cntr <= (others => '0');
932  else
933  TXSEQ_cntr <= TXSEQ_cntr + 1;
934  end if;
935  if(TXSEQ_cntr(0) = '1')then
936  GTX_TX_PAUSE <= and_reduce(TXSEQ_cntr(5 downto 1));
937  end if;
938  if(inh_TX(0) = '1')then
939  SFP_TXSEQUENCE(0) <= (others => '0');
940  elsif(TXSEQ_cntr(0) = '1')then
941  SFP_TXSEQUENCE(0) <= '0' & TXSEQ_cntr(6 downto 1);
942  end if;
943  if(inh_TX(1) = '1')then
944  SFP_TXSEQUENCE(1) <= (others => '0');
945  elsif(TXSEQ_cntr(0) = '1')then
946  SFP_TXSEQUENCE(1) <= '0' & TXSEQ_cntr(6 downto 1);
947  end if;
948  if(inh_TX(2) = '1')then
949  SFP_TXSEQUENCE(2) <= (others => '0');
950  elsif(TXSEQ_cntr(0) = '1')then
951  SFP_TXSEQUENCE(2) <= '0' & TXSEQ_cntr(6 downto 1);
952  end if;
953  end if;
954 end process;
955 process(TXUSRCLK,TCPreset)
956 begin
957  if(TCPreset = '1')then
958  reset_TXSyncRegs <= (others => '1');
959  elsif(TXUSRCLK'event and TXUSRCLK = '1')then
960  reset_TXSyncRegs <= reset_TXSyncRegs(1 downto 0) & '0';
961  end if;
962 end process;
963 process(TXUSRCLK,SFP_TX_FSM_RESET_DONE(0))
964 begin
965  if(SFP_TX_FSM_RESET_DONE(0) = '0')then
966  inh_TX(0) <= '1';
967  inh_TX_q(0) <= '1';
968  elsif(TXUSRCLK'event and TXUSRCLK = '1')then
969  if(TXSEQ_cntr(0) = '1' and TXSEQ_cntr(6) = '1')then
970  inh_TX(0) <= '0';
971  end if;
972  inh_TX_q(0) <= inh_TX(0);
973  end if;
974 end process;
975 process(TXUSRCLK,SFP_TX_FSM_RESET_DONE(1))
976 begin
977  if(SFP_TX_FSM_RESET_DONE(1) = '0')then
978  inh_TX(1) <= '1';
979  inh_TX_q(1) <= '1';
980  elsif(TXUSRCLK'event and TXUSRCLK = '1')then
981  if(TXSEQ_cntr(0) = '1' and TXSEQ_cntr(6) = '1')then
982  inh_TX(1) <= '0';
983  end if;
984  inh_TX_q(1) <= inh_TX(1);
985  end if;
986 end process;
987 process(TXUSRCLK,SFP_TX_FSM_RESET_DONE(2))
988 begin
989  if(SFP_TX_FSM_RESET_DONE(2) = '0')then
990  inh_TX(2) <= '1';
991  inh_TX_q(2) <= '1';
992  elsif(TXUSRCLK'event and TXUSRCLK = '1')then
993  if(TXSEQ_cntr(0) = '1' and TXSEQ_cntr(6) = '1')then
994  inh_TX(2) <= '0';
995  end if;
996  inh_TX_q(2) <= inh_TX(2);
997  end if;
998 end process;
999 process(sysclk)
1000 begin
1001  if(sysclk'event and sysclk = '1')then
1002  TCPBuf_avl <= not or_reduce(enTCPIP);
1003  evt_buf_full <= evt_FIFO_full or wport_FIFO_full;
1004  end if;
1005 end process;
1006 g_FirstBlkAddr: for j in 0 to 1 generate
1007  g1_FirstBlkAddr: for i in 0 to 5 generate
1008  i_FirstBlkAddr : RAM32M
1009  port map (
1010  DOA => FirstBlkAddrDo (j)(0)(i*2+1 downto i*2), -- Read port A 2-bit output
1011  DOB => FirstBlkAddrDo (j)(1)(i*2+1 downto i*2), -- Read port B 2-bit output
1012  DOC => FirstBlkAddrDo (j)(2)(i*2+1 downto i*2), -- Read port C 2-bit output
1013  DOD => open, -- Read/Write port D 2-bit output
1014  ADDRA => FirstBlkAddr_ra(j)(0), -- Read port A 5-bit address input
1015  ADDRB => FirstBlkAddr_ra(j)(1), -- Read port B 5-bit address input
1016  ADDRC => FirstBlkAddr_ra(j)(2), -- Read port C 5-bit address input
1017  ADDRD => FirstBlkAddr_wa, -- Read/Write port D 5-bit address input
1018  DIA => FirstBlkAddrDi (i*2+1 downto i*2), -- RAM 2-bit data write input addressed by ADDRD,
1019  -- read addressed by ADDRA
1020  DIB => FirstBlkAddrDi (i*2+1 downto i*2), -- RAM 2-bit data write input addressed by ADDRD,
1021  -- read addressed by ADDRB
1022  DIC => FirstBlkAddrDi (i*2+1 downto i*2), -- RAM 2-bit data write input addressed by ADDRD,
1023  -- read addressed by ADDRC
1024  DID => "00", -- RAM 2-bit data write input addressed by ADDRD,
1025  -- read addressed by ADDRD
1026  WCLK => sysclk , -- Write clock input
1027  WE => FirstBlkAddr_we -- Write enable input
1028  );
1029  end generate;
1030 end generate;
1031 FirstBlkAddrDi <= '0' & MonBuf_wa;
1032 process(sysclk)
1033 begin
1034  if(sysclk'event and sysclk = '1')then
1035  sysDIV2 <= not sysDIV2;
1036  if(resetSyncRegs(2) = '1')then
1037  chk_MonBuf_avl <= '1';
1038  elsif(buf_rqst(0) = '1')then
1039  chk_MonBuf_avl <= buf_rqst(3);
1040  end if;
1041  if(resetSyncRegs(2) = '1')then
1042  MonBuf_avl <= '1';
1043  elsif(MonBufOverWrite = '1')then
1044  MonBuf_avl <= not StopOverWrite;
1045  elsif(WaitMonBuf = '1' or enTCPIP /= "000")then
1046  if((MonBuf_wa(10) /= MonBuf_ra(10) and MonBuf_wa(9 downto 0) = MonBuf_ra(9 downto 0)))then
1047  MonBuf_avl <= '0';
1048  else
1049  MonBuf_avl <= '1';
1050  end if;
1051  elsif(chk_MonBuf_avl = '1')then
1052  if(MonBufUsed(9 downto 8) = "11")then
1053  MonBuf_avl <= '0';
1054  else
1055  MonBuf_avl <= '1';
1056  end if;
1057  end if;
1058  if(enTCPIP /= "000")then
1059  mon_evt_cnt_i <= (others => '0');
1060  elsif(MonBufOverWrite = '1')then
1061  mon_evt_cnt_i <= MonBuf_full & Written_MonBuf(3)(9 downto 0);
1062  else
1063  mon_evt_cnt_i <= Written_MonBuf(3) - MonBuf_ra;
1064  end if;
1065  if(enTCPIP /= "000")then
1066  MonBuf_empty <= '1';
1067  elsif(MonBufOverWrite = '0')then
1068  MonBuf_empty <= not or_reduce(mon_evt_cnt_i);
1069  elsif(Written_MonBuf(3) /= MonBuf_ra or MonBuf_full = '1')then
1070  MonBuf_empty <= '0';
1071  else
1072  MonBuf_empty <= '1';
1073  end if;
1074  if(EnSFP(2 downto 1) = "00")then
1075  SFP_we(0) <= EventData_we(0);
1076  EoB(0) <= EventData_in(0)(64);
1077  EoE(0) <= EventData_in(0)(65);
1078  else
1079  SFP_we(0) <= EventData_we(1) and EnSFP(0);
1080  EoB(0) <= EventData_in(1)(64);
1081  EoE(0) <= EventData_in(1)(65);
1082  end if;
1083  if(EnSFP(2 downto 0) = "110")then
1084  SFP_we(1) <= EventData_we(1);
1085  EoB(1) <= EventData_in(1)(64);
1086  EoE(1) <= EventData_in(1)(65);
1087  else
1088  SFP_we(1) <= EventData_we(0) and EnSFP(1);
1089  EoB(1) <= EventData_in(0)(64);
1090  EoE(1) <= EventData_in(0)(65);
1091  end if;
1092  if(EnSFP(2 downto 0) = "111")then
1093  SFP_we(2) <= EventData_we(2);
1094  EoB(2) <= EventData_in(2)(64);
1095  EoE(2) <= EventData_in(2)(65);
1096  else
1097  SFP_we(2) <= EventData_we(0) and EnSFP(2);
1098  EoB(2) <= EventData_in(0)(64);
1099  EoE(2) <= EventData_in(0)(65);
1100  end if;
1101  if(resetSyncRegs(2) = '1')then
1102  ReadBusy <= (others => '0');
1103  EventData_re_i <= (others => '0');
1104  EventBufAddr_we_i <= (others => '0');
1105  UNA_MonBufSyncRegs <= (others => '0');
1106  UNA_TCPBufSyncRegs <= (others => '0');
1107  ReleaseMonBuf <= '0';
1108  ReleaseTCPBuf <= '0';
1109  MonBuf_wa <= (others => '0');
1110  MonBuf_ra <= (others => '0');
1111  Written_MonBufMatch <= (others => '1');
1112  Written_MonBuf <= (others => (others => '0'));
1113  NXT_MonBuf <= (others => (others => '0'));
1114  NXT_TCPBuf <= (others => (others => '0'));
1115  FirstBlkAddr_we <= '0';
1116  FirstBlkAddr_re <= (others => (others => '0'));
1117  FirstBlkAddrDoValid <= (others => (others => '0'));
1118  WrtMonEvtDone_l <= (others => '0');
1119  MonEvtQueued <= (others => '0');
1120  FirstBlkAddr_wa <= (others => '0');
1121  FirstBlkAddr_ra <= (others => (others => (others => '0')));
1122  MonBuf_full <= '0';
1123  EventData_reCntr <= (others => (others => '0'));
1124  EventData_weCntr <= (others => (others => '0'));
1125  EventBufAddr_weCntr <= (others => (others => '0'));
1126  EvtLengthCntr <= (others => x"000001");
1127  TotalEvtLengthCntr <= (others => (others => '0'));
1128  TotalEvtLengthCntr24q <= "000";
1129  SFP_blk_cntr <= (others => (others => '0'));
1130  SFP_evt_cntr <= (others => (others => '0'));
1131  SFP_word_cntr <= (others => (others => '0'));
1132  else
1133  for i in 0 to 2 loop
1134  if(EVENTdata_in(i)(64) = '1' and EVENTdata_we(i) = '1')then
1135  ReadBusy(i) <= '0';
1136  elsif(evt_data_rdy(i) = '1' and wport_rdy(i) = '1' and AddrBuf_full(i) = '0')then
1137  ReadBusy(i) <= '1';
1138  end if;
1139  EventData_re_i(i) <= evt_data_rdy(i) and wport_rdy(i) and not ReadBusy(i) and not AddrBuf_full(i);
1140  if(EventData_re_i(i) = '1')then
1141  EventData_reCntr(i) <= EventData_reCntr(i) + 1;
1142  end if;
1143  if(EventData_we(i) = '1')then
1144  EventData_weCntr(i) <= EventData_weCntr(i) + 1;
1145  end if;
1146  if(EventData_in(i)(66) = '0')then
1147  EventBufAddr_we_i(i) <= evt_data_rdy(i) and wport_rdy(i) and not ReadBusy(i) and not AddrBuf_full(i);
1148  else
1149  EventBufAddr_we_i(i) <= '0';
1150  end if;
1151  if(EventBufAddr_we_i(i) = '1')then
1152  EventBufAddr_weCntr(i) <= EventBufAddr_weCntr(i) + 1;
1153  end if;
1154  if(EventData_we(i) = '1')then
1155  if(EventData_in(i)(65) = '1')then
1156  EvtLengthCntr(i) <= x"000001";
1157  TotalEvtLengthCntr(i)(24 downto 0) <= TotalEvtLengthCntr(i)(24 downto 0) + ('0' & EventData_in(i)(55 downto 32));
1158  else
1159  EvtLengthCntr(i) <= EvtLengthCntr(i) + 1;
1160  end if;
1161  end if;
1162  TotalEvtLengthCntr24q(i) <= TotalEvtLengthCntr(i)(24);
1163  if(TotalEvtLengthCntr24q(i) = '1' and TotalEvtLengthCntr(i)(24) = '0')then
1164  TotalEvtLengthCntr(i)(55 downto 25) <= TotalEvtLengthCntr(i)(55 downto 25) + 1;
1165  end if;
1166  end loop;
1167  if(MonBufOverWrite = '1' and Written_MonBuf(3)(10) = '1')then
1168  MonBuf_full <= '1';
1169  end if;
1170  for j in 0 to 1 loop
1171  for i in 0 to 2 loop
1172  if(FirstBlkAddr_re(j)(i) = '1')then
1173  FirstBlkAddr_ra(j)(i) <= FirstBlkAddr_ra(j)(i) + 1;
1174  end if;
1175  if(FirstBlkAddr_ra(j)(i) = FirstBlkAddr_wa)then
1176  FirstBlkAddrDoValid(j)(i) <= '0';
1177  else
1178  FirstBlkAddrDoValid(j)(i) <= '1';
1179  end if;
1180  end loop;
1181  end loop;
1182  if(FirstBlkAddr_we = '1')then
1183  FirstBlkAddr_wa <= FirstBlkAddr_wa + 1;
1184  end if;
1185  for i in 0 to 2 loop
1186  if(WrtMonEvtDone(i) = '1' and enTCPIP = "000")then
1187  WrtMonEvtDone_l(i) <= '1';
1188  elsif(FirstBlkAddrDoValid(0)(i) = '1')then
1189  WrtMonEvtDone_l(i) <= '0';
1190  end if;
1191  FirstBlkAddr_re(0)(i) <= FirstBlkAddrDoValid(0)(i) and WrtMonEvtDone_l(i);
1192  if(EventData_we(i) = '1' and EventData_in(i)(66 downto 65) = "01" and enTCPIP = "000")then
1193  MonEvtQueued(i) <= '1';
1194  elsif(FirstBlkAddrDoValid(1)(i) = '1')then
1195  MonEvtQueued(i) <= '0';
1196  end if;
1197  FirstBlkAddr_re(1)(i) <= FirstBlkAddrDoValid(1)(i) and MonEvtQueued(i);
1198  end loop;
1199  FirstBlkAddr_we <= buf_rqst(3) and buf_rqst(0) and not or_reduce(enTCPIP);
1200  if(buf_rqst(0) = '1')then
1201  MonBuf_wa <= MonBuf_wa + 1;
1202  end if;
1203  MonBufUsed <= MonBuf_wa(9 downto 0) - MonBuf_ra(9 downto 0);
1204  if(ReleaseMonBuf = '1' or (MonBufOverWrite = '1' and StopOverWrite = '0' and and_reduce(MonBufUsed) = '1' and buf_rqst(0) = '1'))then
1205  MonBuf_ra <= MonBuf_ra + 1;
1206  end if;
1207  if(Written_MonBuf(0) = Written_MonBuf(3) and WrtMonEvtDone_l(0) = '0')then
1208  Written_MonBufMatch(0) <= '1';
1209  else
1210  Written_MonBufMatch(0) <= '0';
1211  end if;
1212  if((EnSFP(2 downto 0) = "111" or EnSFP(2 downto 0) = "011" or EnSFP(2 downto 0) = "110" or EnSFP(2 downto 0) = "101") and Written_MonBuf(1) = Written_MonBuf(3) and WrtMonEvtDone_l(1) = '0')then
1213  Written_MonBufMatch(1) <= '1';
1214  else
1215  Written_MonBufMatch(1) <= '0';
1216  end if;
1217  if(EnSFP(2 downto 0) = "111" and Written_MonBuf(2) = Written_MonBuf(3) and WrtMonEvtDone_l(2) = '0')then
1218  Written_MonBufMatch(2) <= '1';
1219  else
1220  Written_MonBufMatch(2) <= '0';
1221  end if;
1222  if(Written_MonBufMatch = "000" and sysDIV2 = '0')then
1223  Written_MonBuf(3) <= Written_MonBuf(3) + 1;
1224  end if;
1225  UNA_MonBufSyncRegs <= UNA_MonBufSyncRegs(2 downto 0) & UNA_MonBuf(4)(0);
1226  UNA_TCPBufSyncRegs <= UNA_TCPBufSyncRegs(2 downto 0) & UNA_TCPBuf(3)(0);
1227  ReleaseMonBuf <= UNA_MonBufSyncRegs(3) xor UNA_MonBufSyncRegs(2);
1228  ReleaseTCPBuf <= UNA_TCPBufSyncRegs(3) xor UNA_TCPBufSyncRegs(2);
1229  for i in 0 to 2 loop
1230  if(FirstBlkAddr_re(0)(i) = '1')then
1231  Written_MonBuf(i) <= FirstBlkAddrDo(0)(i)(10 downto 0);
1232  elsif(WrtMonBlkDone(i) = '1')then
1233  Written_MonBuf(i) <= Written_MonBuf(i) + 1;
1234  end if;
1235  if(FirstBlkAddr_re(1)(i) = '1')then
1236  NXT_MonBuf(i) <= FirstBlkAddrDo(1)(i)(10 downto 0);
1237  elsif(EventBufAddr_we_i(i) = '1' and EventData_in(i)(66) = '0')then
1238  NXT_MonBuf(i) <= NXT_MonBuf(i) + 1;
1239  end if;
1240  if(EventBufAddr_we_i(i) = '1' and EventData_in(i)(66) = '1')then
1241  NXT_TCPBuf(i) <= NXT_TCPBuf(i) + 1;
1242  end if;
1243  if(SFP_we(i) = '1' and EoB(i) = '1')then
1244  SFP_blk_cntr(i) <= SFP_blk_cntr(i) + 1;
1245  end if;
1246  if(SFP_we(i) = '1' and EoE(i) = '1')then
1247  SFP_evt_cntr(i) <= SFP_evt_cntr(i) + 1;
1248  end if;
1249  if(SFP_we(i) = '1')then
1250  SFP_word_cntr(i) <= SFP_word_cntr(i) + 1;
1251  end if;
1252  end loop;
1253  end if;
1254  for i in 0 to 2 loop
1255  if(EventData_in(i)(66) = '0')then
1256  EventBufAddr_i(i) <= NXT_MonBuf(i)(9 downto 0) & AddrOffset(i)(9 downto 6);
1257  else
1258  EventBufAddr_i(i) <= NXT_TCPBuf(i)(9 downto 0) & AddrOffset(i)(9 downto 6);
1259  end if;
1260  end loop;
1261  end if;
1262 end process;
1263 process(ClientClk2X)
1264 begin
1265  if(ClientClk2X'event and ClientClk2X = '1')then
1266  if(ClientClk2XresetSyncRegs(2) = '1')then
1267  inc_ddr_paSyncRegs <= (others => '0');
1268  UNA_MonBufMatch <= (others => '1');
1269  UNA_TCPBufMatch <= (others => '1');
1270  UNA_MonBuf(4) <= (others => '0');
1271  UNA_MonBuf(3) <= (others => '0');
1272  UNA_TCPBuf(3) <= (others => '0');
1273  else
1274  inc_ddr_paSyncRegs <= inc_ddr_paSyncRegs(2 downto 0) & inc_ddr_pa;
1275  if(inc_ddr_paSyncRegs(3 downto 2) = "10")then
1276  UNA_MonBuf(3) <= UNA_MonBuf(3) + 1;
1277  end if;
1278  for i in 0 to 2 loop
1279  if(enTCPIP(i) = '1' and UNA_MonBuf(i) = UNA_MonBuf(4))then
1280  UNA_MonBufMatch(i) <= '1';
1281  else
1282  UNA_MonBufMatch(i) <= '0';
1283  end if;
1284  if(enTCPIP(i) = '1' and UNA_TCPBuf(i) = UNA_TCPBuf(3))then
1285  UNA_TCPBufMatch(i) <= '1';
1286  else
1287  UNA_TCPBufMatch(i) <= '0';
1288  end if;
1289  end loop;
1290  if(EnTCPIP = "000" and UNA_MonBuf(3) = UNA_MonBuf(4))then
1291  UNA_MonBufMatch(3) <= '1';
1292  else
1293  UNA_MonBufMatch(3) <= '0';
1294  end if;
1295  if(UNA_MonBufMatch = x"0" and us_cntr(0) = '1')then
1296  UNA_MonBuf(4) <= UNA_MonBuf(4) + 1;
1297  end if;
1298  if(UNA_TCPBufMatch = "000" and enSFP(2 downto 0) /= "000" and us_cntr(0) = '1')then
1299  UNA_TCPBuf(3) <= UNA_TCPBuf(3) + 1;
1300  end if;
1301  end if;
1302  case EnSFP(2 downto 0) is
1303  when "011" | "101" | "110" => AddrOffset(0)(9 downto 6) <= x"8";
1304  when "111" => AddrOffset(0)(9 downto 6) <= x"5";
1305  when others => AddrOffset(0)(9 downto 6) <= x"0";
1306  end case;
1307  AddrOffset(1)(9 downto 6) <= x"0";
1308  AddrOffset(2)(9 downto 6) <= x"a";
1309  if(EnSFP(3) = '0' and or_reduce(EnSFP(2 downto 0)) = '1')then
1310  EnTCPIP(0) <= '1';
1311  else
1312  EnTCPIP(0) <= '0';
1313  end if;
1314  if(EnSFP(3) = '0' and (EnSFP(2 downto 0) = "011" or EnSFP(2 downto 0) = "101" or EnSFP(2 downto 0) = "110" or EnSFP(2 downto 0) = "111"))then
1315  EnTCPIP(1) <= '1';
1316  else
1317  EnTCPIP(1) <= '0';
1318  end if;
1319  if(EnSFP = x"7")then
1320  EnTCPIP(2) <= '1';
1321  else
1322  EnTCPIP(2) <= '0';
1323  end if;
1324  end if;
1325 end process;
1326 process(sysclk,rstCntr)
1327 begin
1328  if(rstCntr = '1')then
1329  EvtLength_errCntr <= (others => (others => '0'));
1330  AMCLength_errCntr <= (others => (others => '0'));
1331  AMCvalid_errCntr <= (others => (others => '0'));
1332  AMCcrc_errCntr <= (others => (others => '0'));
1333  elsif(sysclk'event and sysclk = '1')then
1334  for i in 0 to 2 loop
1335  if(inc_err(i)(1) = '1')then
1336  EvtLength_errCntr(i) <= EvtLength_errCntr(i) + 1;
1337  end if;
1338  if(inc_err(i)(2) = '1')then
1339  AMClength_errCntr(i) <= AMClength_errCntr(i) + 1;
1340  end if;
1341  if(inc_err(i)(3) = '1')then
1342  AMCvalid_errCntr(i) <= AMCvalid_errCntr(i) + 1;
1343  end if;
1344  if(inc_err(i)(4) = '1')then
1345  AMCcrc_errCntr(i) <= AMCcrc_errCntr(i) + 1;
1346  end if;
1347  end loop;
1348  end if;
1349 end process;
1350 i_check_event: check_event PORT MAP(
1351  clk => sysclk ,
1352  reset => resetSyncRegs(2),
1353  en_stop => en_stop,
1354  cmsCRC_err => "000",
1355  EventData_in => EventData_in,
1356  EventData_we => EventData_we,
1357  inc_err => inc_err,
1358  stop => stop
1359  );
1360 process(sysclk,rstCntr)
1361 begin
1362  if(rstCntr = '1')then
1363  StopOverWrite <= '0';
1364  elsif(StopOnCMScrc_err = '1')then
1365  StopOverWrite <= '1';
1366  elsif(sysclk'event and sysclk = '1')then
1367  if(stop = '1')then
1368  StopOverWrite <= '1';
1369  end if;
1370  end if;
1371 end process;
1372 i_FIFO_RESET_7S: FIFO_RESET_7S PORT MAP(
1373  reset => resetSyncRegs(2),
1374  clk => sysclk ,
1375  fifo_rst => fifo_rst,
1376  fifo_en => fifo_en
1377  );
1378 process(sysclk)
1379 begin
1380  if(sysclk'event and sysclk = '1')then
1381  for i in 0 to 2 loop
1382  if(resetSyncRegs(2) = '1' or EventBufAddr_we_i(i) = '1')then
1383  evt_FIFO_di(i)(65) <= '1';
1384  elsif(evt_FIFO_we(i) = '1')then
1385  evt_FIFO_di(i)(65) <= '0';
1386  end if;
1387  end loop;
1388  end if;
1389 end process;
1390 g_evt_FIFO: for i in 0 to 2 generate
1391  i_evt_fifo : FIFO_DUALCLOCK_MACRO
1392  generic map (
1393  DEVICE => "7SERIES", -- Target Device: "VIRTEX5", "VIRTEX6", "7SERIES"
1394  ALMOST_FULL_OFFSET => X"0004", -- Sets almost full threshold
1395  ALMOST_EMPTY_OFFSET => X"0080", -- Sets the almost empty threshold
1396  DATA_WIDTH => 67, -- Valid values are 1-72 (37-72 only valid when FIFO_SIZE="36Kb")
1397  FIFO_SIZE => "36Kb", -- Target BRAM, "18Kb" or "36Kb"
1398  FIRST_WORD_FALL_THROUGH => TRUE) -- Sets the FIFO FWFT to TRUE or FALSE
1399  port map (
1400  ALMOSTEMPTY => open, -- 1-bit output almost empty
1401  ALMOSTFULL => evt_FIFO_full(i), -- 1-bit output almost full
1402  DO => evt_FIFO_do(i), -- Output data, width defined by DATA_WIDTH parameter
1403  EMPTY => evt_FIFO_empty(i), -- 1-bit output empty
1404  FULL => open, -- 1-bit output full
1405  RDCOUNT => evt_FIFO_RDCOUNT(i), -- Output read count, width determined by FIFO depth
1406  RDERR => open, -- 1-bit output read error
1407  WRCOUNT => evt_FIFO_WRCOUNT(i), -- Output write count, width determined by FIFO depth
1408  WRERR => open, -- 1-bit output write error
1409  DI => evt_FIFO_di(i), -- Input data, width defined by DATA_WIDTH parameter
1410  RDCLK => ClientClk2X, -- 1-bit input read clock
1411  RDEN => evt_FIFO_re(i), -- 1-bit input read enable
1412  RST => fifo_rst, -- 1-bit input reset
1413  WRCLK => sysclk, -- 1-bit input write clock
1414  WREN => evt_FIFO_we(i) -- 1-bit input write enable
1415  );
1416 end generate;
1417 evt_FIFO_di(0)(64 downto 0) <= EVENTdata_in(0)(64 downto 0);
1418 evt_FIFO_di(1)(64 downto 0) <= EVENTdata_in(1)(64 downto 0);
1419 evt_FIFO_di(2)(64 downto 0) <= EVENTdata_in(2)(64 downto 0);
1420 evt_FIFO_di(0)(66) <= EVENTdata_in(0)(65);
1421 evt_FIFO_di(1)(66) <= EVENTdata_in(1)(65);
1422 evt_FIFO_di(2)(66) <= EVENTdata_in(2)(65);
1423 evt_FIFO_we <= "000" when EnSFP(3) = '1' or fifo_en = '0' else EVENTdata_we;
1424 evt_FIFO_re <= "000" when fifo_en = '0' else evt_FIFO_rep;
1425 EVENTdata_avl <= not evt_FIFO_empty;
1426 g_cmsCRC : for i in 0 to 2 generate
1427  i_cmsCRC: cmsCRC64 PORT MAP(
1428  clk => ClientClk2X,
1429  reset => '0',
1430  crc_init => cmsCRC_init(i),
1431  trailer => evt_FIFO_do(i)(66),
1432  crc_d => evt_FIFO_do(i)(63 downto 0),
1433  crc_ce => cmsCRC_ce(i),
1434  crc => open,
1435  crc_err => cmsCRC_err(i),
1436  dout => open,
1437  dout_vld => open
1438  );
1439 end generate;
1440 cmsCRC_ce <= evt_FIFO_rep and EVENTdata_avl;
1441 process(ClientClk2X)
1442 begin
1443  if(ClientClk2X'event and ClientClk2X = '1')then
1444  if(ClientClk2XresetSyncRegs(2) = '1')then
1445  cmsCRC_initp <= "000";
1446  cmsCRC_init <= "111";
1447  cmsCRC_errCntr <= (others => (others => '0'));
1448  StopOnCMScrc_err <= '0';
1449  else
1450  for i in 0 to 2 loop
1451  cmsCRC_initp(i) <= evt_FIFO_do(i)(66) and cmsCRC_ce(i);
1452  if(cmsCRC_err(i) = '1' and cmsCRC_init(i) = '1')then
1453  cmsCRC_errCntr(i) <= cmsCRC_errCntr(i) + 1;
1454  end if;
1455  end loop;
1456  cmsCRC_init <= cmsCRC_initp;
1457  if(en_stop(0) = '1' and or_reduce(cmsCRC_err and cmsCRC_init) = '1')then
1458  StopOnCMScrc_err <= '1';
1459  else
1460  StopOnCMScrc_err <= '0';
1461  end if;
1462  end if;
1463  end if;
1464 end process;
1465 g_TCPIP: for i in 0 to 2 generate
1466  i_TCPIP: TCPIP PORT MAP(
1467  reset => reset_TCPIP(i),
1468  rstCntr => rstCntr,
1469  sysclk => sysclk,
1470  clk2x => ClientClk2X,
1471  clk => ClientClk,
1472  strobe_us => strobe_us,
1473  strobe_ms => strobe_ms,
1474  en_LINK => enTCPIP(i),
1475  LINK_down => LINK_down(i),
1476  MY_PORT => x"1234",
1477  MY_IP => IPADDR(i),
1478  MY_ETH => MACADDR(i),
1479  TSclock => TSclock,
1480 -- CWND_max => CWND_max,
1481  RTOmin => RTOmin,
1482  rate_limit => rate_limit(i),
1483  EVENTdata => evt_FIFO_do(i),
1484  EVENTdata_avl => EVENTdata_avl(i),
1485  EVENTdata_re => evt_FIFO_rep(i),
1486  DDR2TCPdata => DDR2TCPdata,
1487  RETXdata_chksum => RETXdata_checksum(i),
1488  RETXdata_we => RETXdata_we(i),
1489  RETX_ddr_out => RETX_ddr_out(i),
1490  re_RETX_ddr_wq => re_RETX_ddr_wq (i),
1491  RETX_ddr_wrqst => RETX_ddr_wrqst (i),
1492  RETX_ddr_data_we => RETX_ddr_data_we(i),
1493  RETX_ddr_rrqst => RETX_ddr_rrqst (i),
1494  RETX_ddr_LEN_max => RETX_ddr_LEN_max(i),
1495  RETX_ddr_LEN => RETX_ddr_LEN(i),
1496  RETXdataACK => RETXdataACK(i),
1497  RETXdataRqst => RETXdataRqst(i),
1498  RETXdataAddr => RETXdataAddr(i),
1499  RETXdataLEN => RETXdataLEN(i),
1500  KiloByte_toggle => KiloByte_toggle(i),
1501  EoB_toggle => EoB_toggle(i),
1502  TCP_wcount => TCP_wcount(i),
1503  EventBufAddr => EventBufAddr_i (i),
1504  EventBufAddr_we => EventBufAddr_we_i(i),
1505  AddrBuf_full => AddrBuf_full(i),
1506  UNA_MonBuf => UNA_MonBuf(i),
1507  UNA_TCPBuf => UNA_TCPBuf(i),
1508  EmacPhyTxC => EmacPhyTxc(i),
1509  EmacPhyTxD => EmacPhyTxd(i),
1510  PhyEmacRxC => PhyEmacRxC(i),
1511  PhyEmacRxD => PhyEmacRxD(i),
1512  ipb_addr => ipb_addr,
1513  ipb_rdata => TCPIP_rdata(i),
1514  cs_out => TCPIP_cs(i)
1515  );
1516 end generate;
1517 i_RETXdata_chksum: RETXdata_chksum PORT MAP(
1518  c => ClientClk2X,
1519  r => rst_RETXdata_chksum,
1520  ce => TCP_din_valid,
1521  d => TCP_din,
1522  s => RETXdata_chksum_out
1523  );
1524 process(ClientClk2X)
1525 begin
1526  if(ClientClk2X'event and ClientClk2X = '1')then
1527  if(TCP_lastword = '1' and TCP_din_valid = '1' and TCP_din_type = "100")then
1528  ld_RETXdata_chksum(0) <= '1';
1529  else
1530  ld_RETXdata_chksum(0) <= '0';
1531  end if;
1532  if(TCP_lastword = '1' and TCP_din_valid = '1' and TCP_din_type = "101")then
1533  ld_RETXdata_chksum(1) <= '1';
1534  else
1535  ld_RETXdata_chksum(1) <= '0';
1536  end if;
1537  if(TCP_lastword = '1' and TCP_din_valid = '1' and TCP_din_type = "110")then
1538  ld_RETXdata_chksum(2) <= '1';
1539  else
1540  ld_RETXdata_chksum(2) <= '0';
1541  end if;
1542  ld_RETXdata_chksum_r <= ld_RETXdata_chksum;
1543  ld_RETXdata_chksum_r2 <= ld_RETXdata_chksum_r;
1544  if(ld_RETXdata_chksum_r2(0) = '1')then
1545  RETXdata_checksum(0) <= RETXdata_chksum_out;
1546  end if;
1547  if(ld_RETXdata_chksum_r2(1) = '1')then
1548  RETXdata_checksum(1) <= RETXdata_chksum_out;
1549  end if;
1550  if(ld_RETXdata_chksum_r2(2) = '1')then
1551  RETXdata_checksum(2) <= RETXdata_chksum_out;
1552  end if;
1553  if(ClientClk2XresetSyncRegs(2) = '1')then
1554  rst_RETXdata_chksum <= '1';
1555  else
1556  rst_RETXdata_chksum <= TCP_lastword and TCP_din_valid;
1557  end if;
1558  DDR2TCPdata <= TCP_lastword & TCP_din;
1559  if(FIFO_en = '1' and TCP_din_valid = '1' and TCP_din_type = "000")then
1560  RETX_ddr_data_we(0) <= '1';
1561  else
1562  RETX_ddr_data_we(0) <= '0';
1563  end if;
1564  if(FIFO_en = '1' and TCP_din_valid = '1' and TCP_din_type = "001")then
1565  RETX_ddr_data_we(1) <= '1';
1566  else
1567  RETX_ddr_data_we(1) <= '0';
1568  end if;
1569  if(FIFO_en = '1' and TCP_din_valid = '1' and TCP_din_type = "010")then
1570  RETX_ddr_data_we(2) <= '1';
1571  else
1572  RETX_ddr_data_we(2) <= '0';
1573  end if;
1574  rst_odd <= TCP_lastword and TCP_din_valid;
1575  if(ClientClk2XresetSyncRegs(2) = '1' or rst_odd = '1')then
1576  odd <= '0';
1577  elsif(TCP_din_valid = '1')then
1578  odd <= not odd;
1579  end if;
1580  if(TCP_din_valid = '1' and TCP_din_type = "100")then
1581  RETXdata_we(0) <= odd & not odd;
1582  else
1583  RETXdata_we(0) <= "00";
1584  end if;
1585  if(TCP_din_valid = '1' and TCP_din_type = "101")then
1586  RETXdata_we(1) <= odd & not odd;
1587  else
1588  RETXdata_we(1) <= "00";
1589  end if;
1590  if(TCP_din_valid = '1' and TCP_din_type = "110")then
1591  RETXdata_we(2) <= odd & not odd;
1592  else
1593  RETXdata_we(2) <= "00";
1594  end if;
1595  if(RETX_ddr_rp_rst = '1')then
1596  RETX_ddr_rp_di <= (others => '0');
1597  RETX_ddr_rp_we <= '1';
1598  else
1599  RETX_ddr_rp_di(16 downto 0) <= RETX_ddr_rp_do(16 downto 0) + TCP_length_i(20 downto 4);
1600  RETX_ddr_rp_we <= TCP_rack and not TCP_raddr_i(28);
1601  end if;
1602  if(ClientClk2XresetSyncRegs(2) = '1')then
1603  ReTx_ddr_LEN_max <= (others => "10000");
1604  elsif(RETX_ddr_rp_we = '1')then
1605  if(and_reduce(RETX_ddr_rp_di(8 downto 4)) = '0')then -- ReTx_ddr_LEN_max insures the readout does not go into event data area
1606  ReTx_ddr_LEN_max(conv_integer(RETX_ddr_rp_a)) <= "10000";
1607  else
1608  ReTx_ddr_LEN_max(conv_integer(RETX_ddr_rp_a)) <= "10000" - ('0' & RETX_ddr_rp_di(3 downto 0));
1609  end if;
1610  end if;
1611  if(ClientClk2XresetSyncRegs(2) = '1')then
1612  RETX_ddr_rp_rst <= '1';
1613  RETX_ddr_rp_a <= (others => '0');
1614  TCP_rrqst_i <= "000";
1615  rrqstMask <= (others => '1');
1616  else
1617  if(RETX_ddr_rp_a(1) = '1')then
1618  RETX_ddr_rp_rst <= '0';
1619  end if;
1620  if(RETX_ddr_rp_rst = '1')then
1621  RETX_ddr_rp_a(1 downto 0) <= RETX_ddr_rp_a(1 downto 0) + 1;
1622  elsif(TCP_rrqst_i(0) = '0')then
1623  if(or_reduce(rrqstMask(5 downto 3) and RETXdataRqst) = '1')then
1624  RETX_ddr_rp_a(1 downto 0) <= "11";
1625  elsif(rrqstMask(0) = '1' and RETX_ddr_rrqst(0) = '1')then
1626  RETX_ddr_rp_a(1 downto 0) <= "00";
1627  elsif(rrqstMask(1) = '1' and RETX_ddr_rrqst(1) = '1')then
1628  RETX_ddr_rp_a(1 downto 0) <= "01";
1629  else
1630  RETX_ddr_rp_a(1 downto 0) <= "10";
1631  end if;
1632  end if;
1633  if(TCP_rack = '1')then
1634  TCP_rrqst_i <= "000";
1635  else
1636  if(or_reduce(rrqstMask(2 downto 0) and RETX_ddr_rrqst) = '1' or or_reduce(rrqstMask(5 downto 3) and RETXdataRqst) = '1')then
1637  TCP_rrqst_i(0) <= '1';
1638  end if;
1639  TCP_rrqst_i(2 downto 1) <= TCP_rrqst_i(1 downto 0);
1640  end if;
1641  for i in 0 to 2 loop
1642  if(TCP_rrqst_i(0) = '1' and TCP_raddr_i(28) = '0' and i = conv_integer(TCP_raddr_i(27 downto 26)))then
1643  rrqstMask(i) <= '0';
1644  elsif(rst_RETXdata_chksum = '1' and TCP_din_type(2) = '0' and i = conv_integer(TCP_din_type(1 downto 0)))then
1645  rrqstMask(i) <= '1';
1646  end if;
1647  if(TCP_rrqst_i(0) = '1' and TCP_raddr_i(28) = '1' and i = conv_integer(TCP_raddr_i(27 downto 26)))then
1648  rrqstMask(i+3) <= '0';
1649  elsif(rst_RETXdata_chksum = '1' and TCP_din_type(2) = '1' and i = conv_integer(TCP_din_type(1 downto 0)))then
1650  rrqstMask(i+3) <= '1';
1651  end if;
1652  end loop;
1653  end if;
1654  if(TCP_rrqst_i(0) = '0')then
1655  RETXdataAck <= (others => '0');
1656  elsif(TCP_raddr_i(28) = '1')then
1657  case TCP_raddr_i(27 downto 26) is
1658  when "00" => RETXdataAck <= "001";
1659  when "01" => RETXdataAck <= "010";
1660  when "10" => RETXdataAck <= "100";
1661  when others => RETXdataAck <= "000";
1662  end case;
1663  end if;
1664  if(TCP_rrqst_i(0) = '0')then
1665  if(or_reduce(rrqstMask(5 downto 3) and RETXdataRqst) = '1')then
1666  TCP_raddr_i(28) <= '1';
1667  if(rrqstMask(3) = '1' and RETXdataRqst(0) = '1')then
1668  TCP_raddr_i(27 downto 26) <= "00";
1669  elsif(rrqstMask(4) = '1' and RETXdataRqst(1) = '1')then
1670  TCP_raddr_i(27 downto 26) <= "01";
1671  else
1672  TCP_raddr_i(27 downto 26) <= "10";
1673  end if;
1674  else
1675  TCP_raddr_i(28) <= '0';
1676  if(rrqstMask(0) = '1' and RETX_ddr_rrqst(0) = '1')then
1677  TCP_raddr_i(27 downto 26) <= "00";
1678  elsif(rrqstMask(1) = '1' and RETX_ddr_rrqst(1) = '1')then
1679  TCP_raddr_i(27 downto 26) <= "01";
1680  else
1681  TCP_raddr_i(27 downto 26) <= "10";
1682  end if;
1683  end if;
1684  end if;
1685  case TCP_raddr_i(28 downto 26) is
1686  when "100" => TCP_raddr_i(25 downto 0) <= RETXdataAddr(0);
1687  when "101" => TCP_raddr_i(25 downto 0) <= RETXdataAddr(1);
1688  when "110" => TCP_raddr_i(25 downto 0) <= RETXdataAddr(2);
1689  when others => TCP_raddr_i(25 downto 0) <= TCP_raddr_i(27 downto 26)(1 downto 0) & RETX_ddr_rp_do(16 downto 9) & x"f" & RETX_ddr_rp_do(8 downto 0) & "000";
1690  end case;
1691  TCP_rlength <= TCP_length_i(13 downto 1) - 1;
1692  case TCP_raddr_i(28 downto 26) is
1693  when "000" => TCP_length_i(13 downto 0) <= "00000" & RETX_ddr_LEN(0) & x"0";
1694  when "001" => TCP_length_i(13 downto 0) <= "00000" & RETX_ddr_LEN(1) & x"0";
1695  when "010" => TCP_length_i(13 downto 0) <= "00000" & RETX_ddr_LEN(2) & x"0";
1696  when "100" => TCP_length_i(13 downto 0) <= RETXdataLEN(0) & '0';
1697  when "101" => TCP_length_i(13 downto 0) <= RETXdataLEN(1) & '0';
1698  when "110" => TCP_length_i(13 downto 0) <= RETXdataLEN(2) & '0';
1699  when others => TCP_length_i(13 downto 0) <= (others => '0');
1700  end case;
1701  end if;
1702 end process;
1703 g_RETX_ddr_rp : for i in 0 to 2 generate
1704  i_RETX_ddr_rp : RAM32x6Db PORT MAP(
1705  wclk => ClientClk2X,
1706  di => RETX_ddr_rp_di (i*6+5 downto i*6),
1707  we => RETX_ddr_rp_we ,
1708  wa => RETX_ddr_rp_a,
1709  ra => RETX_ddr_rp_a,
1710  do => RETX_ddr_rp_do (i*6+5 downto i*6)
1711  );
1712 end generate;
1713 TCP_we <= TCP_wFIFO_we;
1714 i_TCP_wFIFO_we : SRL16E
1715  port map (
1716  Q => TCP_wFIFO_we, -- SRL data output
1717  A0 => '0', -- Select[0] input
1718  A1 => '1', -- Select[1] input
1719  A2 => '0', -- Select[2] input
1720  A3 => '0', -- Select[3] input
1721  CE => '1', -- Clock enable input
1722  CLK => ClientClk2X, -- Clock input
1723  D => TCP_w_busy -- SRL data input
1724  );
1725 TCP_channel <= TCP_wFIFO_DI(33 downto 32);
1726 TCP_dout <= TCP_wFIFO_DI(31 downto 0);
1727 process(ClientClk2X, TCP_w_sel, RETX_ddr_wrqst)
1728 variable s : std_logic_vector(4 downto 0);
1729 begin
1730  s := TCP_w_sel & RETX_ddr_wrqst;
1731  if(ClientClk2X'event and ClientClk2X = '1')then
1732  if(FIFO_en = '0' or ClientClk2XresetSyncRegs(2) = '1')then
1733  TCP_w_sel <= "00";
1734  elsif(TCP_w_busy = '0')then
1735  case s is
1736  when "00001" | "01001" | "01011" | "10001" | "10011" | "10101" | "10111" =>
1737  TCP_w_sel <= "00";
1738  when "00010" | "00011" | "00110" | "00111" | "01010" | "10010" | "10110" =>
1739  TCP_w_sel <= "01";
1740  when "00100" | "00101" | "01100" | "01101" | "01110" | "01111" | "10100" =>
1741  TCP_w_sel <= "10";
1742  when others => null;
1743  end case;
1744  end if;
1745  if(FIFO_en = '0' or ClientClk2XresetSyncRegs(2) = '1')then
1746  TCP_w_busy <= '0';
1747  elsif(TCP_w_wc = x"f")then
1748  TCP_w_busy <= '0';
1749  elsif(RETX_ddr_wrqst /= "000")then
1750  TCP_w_busy <= '1';
1751  end if;
1752  if(ClientClk2XresetSyncRegs(2) = '1')then
1753  TCP_w_wc <= x"0";
1754  elsif(TCP_w_busy = '1')then
1755  TCP_w_wc <= TCP_w_wc + 1;
1756  end if;
1757  if(FIFO_en = '0' or ClientClk2XresetSyncRegs(2) = '1')then
1758  re_RETX_ddr_wq <= "000";
1759  else
1760  case TCP_w_sel is
1761  when "00" => re_RETX_ddr_wq(0) <= TCP_w_busy;
1762  when "01" => re_RETX_ddr_wq(1) <= TCP_w_busy;
1763  when others => re_RETX_ddr_wq(2) <= TCP_w_busy;
1764  end case;
1765  end if;
1766  case TCP_w_sel is
1767  when "00" => TCP_wFIFO_DI <= "00" & RETX_ddr_out(0);
1768  when "01" => TCP_wFIFO_DI <= "01" & RETX_ddr_out(1);
1769  when others => TCP_wFIFO_DI <= "10" & RETX_ddr_out(2);
1770  end case;
1771  end if;
1772 end process;
1773 process(ClientClk2X)
1774 begin
1775  if(ClientClk2X'event and ClientClk2X = '1')then
1776  case EnSFP(2 downto 0) is
1777  when "010" | "011" | "101" | "111" => TCPIP2SFP_sel(0) <= "01";
1778  when "100" | "110" => TCPIP2SFP_sel(0) <= "10";
1779  when others => TCPIP2SFP_sel(0) <= "00";
1780  end case;
1781  case EnSFP(2 downto 0) is
1782  when "010" | "011" | "111" => TCPIP2SFP_sel(1) <= "00";
1783  when "101" => TCPIP2SFP_sel(1) <= "10";
1784  when others => TCPIP2SFP_sel(1) <= "01";
1785  end case;
1786  case EnSFP(2 downto 0) is
1787  when "100" | "101" | "110" => TCPIP2SFP_sel(2) <= "00";
1788  when others => TCPIP2SFP_sel(2) <= "10";
1789  end case;
1790  for i in 0 to 1 loop
1791  SFP_EmacPhyTxc(i) <= EmacPhyTxc(conv_integer(TCPIP2SFP_sel(i)));
1792  SFP_EmacPhyTxD(i) <= EmacPhyTxD(conv_integer(TCPIP2SFP_sel(i)));
1793  SFP_down_i(i) <= LINK_down(conv_integer(TCPIP2SFP_sel(i)));
1794  end loop;
1795  if(TCPIP2SFP_sel(2)(1) = '0')then
1796  SFP_EmacPhyTxc(2) <= EmacPhyTxc(0);
1797  SFP_EmacPhyTxD(2) <= EmacPhyTxD(0);
1798  SFP_down_i(2) <= LINK_down(0);
1799  else
1800  SFP_EmacPhyTxc(2) <= EmacPhyTxc(2);
1801  SFP_EmacPhyTxD(2) <= EmacPhyTxD(2);
1802  SFP_down_i(2) <= LINK_down(2);
1803  end if;
1804  case EnSFP(2 downto 0) is
1805  when "010" | "011" | "111" => SFP2TCPIP(0) <= "01";
1806  when "100" | "101" | "110" => SFP2TCPIP(0) <= "10";
1807  when others => SFP2TCPIP(0) <= "00";
1808  end case;
1809  case EnSFP(2 downto 0) is
1810  when "010" | "011" | "101" | "111" => SFP2TCPIP(1) <= "00";
1811  when others => SFP2TCPIP(1) <= "01";
1812  end case;
1813  case EnSFP(2 downto 0) is
1814  when "100" | "110" => SFP2TCPIP(2) <= "00";
1815  when "101" => SFP2TCPIP(2) <= "01";
1816  when others => SFP2TCPIP(2) <= "10";
1817  end case;
1818 -- if(SFP_PhyEmacRxc(0) = x"1" and SFP_PhyEmacRxd(0) = x"555555fb")then
1819 -- Rx_start_cntr(15 downto 0) <= Rx_start_cntr(15 downto 0) + 1;
1820 -- end if;
1821 -- if(SFP_PhyEmacRxc(1) = x"1" and SFP_PhyEmacRxd(1) = x"555555fb")then
1822 -- Rx_start_cntr(31 downto 16) <= Rx_start_cntr(31 downto 16) + 1;
1823 -- end if;
1824  PhyEmacRxc(0) <= SFP_PhyEmacRxc(conv_integer(SFP2TCPIP(0)));
1825  PhyEmacRxD(0) <= SFP_PhyEmacRxD(conv_integer(SFP2TCPIP(0)));
1826  if(SFP2TCPIP(1)(0) = '0')then
1827  PhyEmacRxc(1) <= SFP_PhyEmacRxc(0);
1828  PhyEmacRxD(1) <= SFP_PhyEmacRxD(0);
1829  else
1830  PhyEmacRxc(1) <= SFP_PhyEmacRxc(1);
1831  PhyEmacRxD(1) <= SFP_PhyEmacRxD(1);
1832  end if;
1833  PhyEmacRxc(2) <= SFP_PhyEmacRxc(conv_integer(SFP2TCPIP(2)));
1834  PhyEmacRxD(2) <= SFP_PhyEmacRxD(conv_integer(SFP2TCPIP(2)));
1835  IPADDR(0) <= SFP_IPADDR(conv_integer(SFP2TCPIP(0)));
1836  IPADDR(1) <= SFP_IPADDR(conv_integer(SFP2TCPIP(1)));
1837  IPADDR(2) <= SFP_IPADDR(conv_integer(SFP2TCPIP(2)));
1838  rate_limit(0) <= SFP_rate_limit(conv_integer(SFP2TCPIP(0)));
1839  rate_limit(1) <= SFP_rate_limit(conv_integer(SFP2TCPIP(1)));
1840  rate_limit(2) <= SFP_rate_limit(conv_integer(SFP2TCPIP(2)));
1841 -- MACADDR(0) <= x"00ac1234568" & "10" & SFP2TCPIP(0);
1842 -- MACADDR(1) <= x"00ac1234568" & "100" & SFP2TCPIP(1)(0);
1843 -- MACADDR(2) <= x"00ac1234568" & "10" & SFP2TCPIP(2);
1844  MACADDR(0) <= x"00ac12345" & not SN & '0' & SFP2TCPIP(0);
1845  MACADDR(1) <= x"00ac12345" & not SN & "00" & SFP2TCPIP(1)(0);
1846  MACADDR(2) <= x"00ac12345" & not SN & '0' & SFP2TCPIP(2);
1847  reset_TCPIP(0) <= SFPresetSyncRegs(conv_integer(SFP2TCPIP(0)))(2);
1848  if(SFP2TCPIP(1)(0) = '0')then
1849  reset_TCPIP(1) <= SFPresetSyncRegs(conv_integer(SFP2TCPIP(0)))(2);
1850  else
1851  reset_TCPIP(1) <= SFPresetSyncRegs(conv_integer(SFP2TCPIP(1)))(2);
1852  end if;
1853  reset_TCPIP(2) <= SFPresetSyncRegs(conv_integer(SFP2TCPIP(2)))(2);
1854  end if;
1855 end process;
1856 g_XGbEPCS : for i in 0 to 2 generate
1857  i_XGbEPCS: XGbEPCS32 PORT MAP (
1858  reset => TCPresetSyncRegs(2),
1859 -- reset => PCS_reset(i),
1860  clk2x => ClientClk2X,
1861  clk => ClientClk,
1862  TXUSRCLK => txusrclk,
1863  TX_high => TX_high,
1864  RXUSRCLK => SFP_RXUSRCLK(i),
1865  RXRESETDONE => SFP_RXRESETDONE(i),
1866  inh_TX => inh_TX(i),
1867  RESET_TXSync => reset_TXSyncRegs(2),
1868  GTX_RXGEARBOXSLIP_OUT => SFP_RXGEARBOXSLIP(i),
1869  GTX_TXD => SFP_TXD(i),
1870  GTX_TXHEADER => SFP_TXHEADER(i),
1871  GTX_TX_PAUSE => GTX_TX_PAUSE,
1872  GTX_RXD => SFP_RXD(i),
1873  GTX_RXDVLD => SFP_RXDVLD(i),
1874  GTX_RXHEADER => SFP_RXHEADER(i),
1875  GTX_RXHEADERVLD => SFP_RXHEADERVLD(i),
1876  GTX_RXGOOD => SFP_RXGOOD(i),
1877  EmacPhyTxC => SFP_EmacPhyTxc(i),
1878  EmacPhyTxD => SFP_EmacPhyTxd(i),
1879  PhyEmacRxC => SFP_PhyEmacRxC(i),
1880  PhyEmacRxD => SFP_PhyEmacRxD(i)
1881  );
1882 end generate;
1883 SFP_pd(0) <= "00" when Dis_pd = '1' else "11" when enSFP(3) = '1' or enSFP(0) = '0' else "00";
1884 SFP_pd(1) <= "00" when Dis_pd = '1' else "11" when enSFP(3) = '1' or enSFP(1) = '0' else "00";
1885 SFP_pd(2) <= "00" when Dis_pd = '1' else "11" when enSFP(3) = '1' or enSFP(2) = '0' else "00";
1886 process(DRPclk)
1887 begin
1888  if(DRPclk'event and DRPclk = '1')then
1889  for i in 0 to 2 loop
1890  SFP_pd_q(i) <= SFP_pd_q(i)(2 downto 0) & SFP_pd(i)(0);
1891  end loop;
1892  if(SFP_pd_q(0)(3 downto 2) = "10" or SFP_pd_q(1)(3 downto 2) = "10" or SFP_pd_q(2)(3 downto 2) = "10")then
1893  reset_cntr <= (others => '0');
1894  elsif(reset_cntr(20) = '0')then
1895  reset_cntr <= reset_cntr + 1;
1896  end if;
1897  reset_cntr20_q <= reset_cntr(20);
1898  soft_reset <= not reset_cntr20_q and reset_cntr(20);
1899  end if;
1900 end process;
1901 i_SFP3_init : SFP3_v2_7_init
1902  port map
1903  (
1904  SYSCLK_IN => DRPclk,
1905  SOFT_RESET_IN => soft_reset,
1906  DONT_RESET_ON_DATA_ERROR_IN => '0',
1907  GT0_TX_FSM_RESET_DONE_OUT => SFP_TX_FSM_RESET_DONE (0),
1908  GT0_RX_FSM_RESET_DONE_OUT => SFP_RX_FSM_RESET_DONE (0),
1909  GT0_DATA_VALID_IN => SFP_RXGOOD(0),
1910  GT1_TX_FSM_RESET_DONE_OUT => SFP_TX_FSM_RESET_DONE (1),
1911  GT1_RX_FSM_RESET_DONE_OUT => SFP_RX_FSM_RESET_DONE(1),
1912  GT1_DATA_VALID_IN => SFP_RXGOOD(1),
1913  GT2_TX_FSM_RESET_DONE_OUT => SFP_TX_FSM_RESET_DONE (2),
1914  GT2_RX_FSM_RESET_DONE_OUT => SFP_RX_FSM_RESET_DONE(2),
1915  GT2_DATA_VALID_IN => SFP_RXGOOD(2),
1916 
1917 
1918 
1919 
1920 
1921  --_____________________________________________________________________
1922  --_____________________________________________________________________
1923  --GT0 (X1Y12)
1924 
1925  ---------------------------- Channel - DRP Ports --------------------------
1926  GT0_DRPADDR_IN => SFP_drpaddr(0),
1927  GT0_DRPCLK_IN => DRPclk,
1928  GT0_DRPDI_IN => SFP_drpdi(0),
1929  GT0_DRPDO_OUT => SFP_drpdo(0),
1930  GT0_DRPEN_IN => SFP_drpen(0),
1931  GT0_DRPRDY_OUT => SFP_drprdy(0),
1932  GT0_DRPWE_IN => SFP_drpwe(0),
1933  ------------------------------- Loopback Ports -----------------------------
1934  GT0_LOOPBACK_IN => SFP_LOOPBACK_IN(0),
1935  ------------------------------ Power-Down Ports ----------------------------
1936  GT0_RXPD_IN => SFP_pd(0),
1937  GT0_TXPD_IN => SFP_pd(0),
1938  --------------------- RX Initialization and Reset Ports --------------------
1939  GT0_RXUSERRDY_IN => SFP_rxuserrdy(0),
1940  -------------------------- RX Margin Analysis Ports ------------------------
1941  GT0_EYESCANDATAERROR_OUT => SFP_EYESCANDATAERROR_OUT (0),
1942  ------------------------- Receive Ports - CDR Ports ------------------------
1943  GT0_RXCDRLOCK_OUT => open,
1944  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
1945  GT0_RXUSRCLK_IN => SFP_RXUSRCLK(0),
1946  GT0_RXUSRCLK2_IN => SFP_RXUSRCLK(0),
1947  ------------------ Receive Ports - FPGA RX interface Ports -----------------
1948  GT0_RXDATA_OUT => SFP_RXD_inv(0),
1949  ------------------- Receive Ports - Pattern Checker Ports ------------------
1950  GT0_RXPRBSERR_OUT => SFP_RXPRBSERR_OUT(0),
1951  GT0_RXPRBSSEL_IN => SFP_RXPRBSSEL_IN(0),
1952  ------------------- Receive Ports - Pattern Checker ports ------------------
1953  GT0_RXPRBSCNTRESET_IN => '0',
1954  --------------------------- Receive Ports - RX AFE -------------------------
1955  GT0_GTXRXP_IN => SFP0_RXP,
1956  ------------------------ Receive Ports - RX AFE Ports ----------------------
1957  GT0_GTXRXN_IN => SFP0_RXN,
1958  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
1959  GT0_RXBUFRESET_IN => '0',
1960  GT0_RXBUFSTATUS_OUT => open,
1961  --------------- Receive Ports - RX Fabric Output Control Ports -------------
1962  GT0_RXOUTCLK_OUT => SFP_rxoutclk(0),
1963  ---------------------- Receive Ports - RX Gearbox Ports --------------------
1964  GT0_RXDATAVALID_OUT => SFP_RXDVLD(0),
1965  GT0_RXHEADER_OUT => SFP_RXHEADER(0),
1966  GT0_RXHEADERVALID_OUT => SFP_RXHEADERVLD(0),
1967  --------------------- Receive Ports - RX Gearbox Ports --------------------
1968  GT0_RXGEARBOXSLIP_IN => SFP_RXGEARBOXSLIP(0),
1969  ------------- Receive Ports - RX Initialization and Reset Ports ------------
1970  GT0_GTRXRESET_IN => '0',
1971  GT0_RXPMARESET_IN => '0',
1972  ------------------ Receive Ports - RX Margin Analysis ports ----------------
1973  GT0_RXLPMEN_IN => '0',
1974  -------------- Receive Ports -RX Initialization and Reset Ports ------------
1975  GT0_RXRESETDONE_OUT => SFP_rxresetdone(0),
1976  --------------------- TX Initialization and Reset Ports --------------------
1977  GT0_GTTXRESET_IN => '0',
1978  GT0_TXUSERRDY_IN => SFP_txuserrdy(0),
1979  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
1980  GT0_TXUSRCLK_IN => txusrclk,
1981  GT0_TXUSRCLK2_IN => txusrclk,
1982  --------------- Transmit Ports - TX Configurable Driver Ports --------------
1983  GT0_TXDIFFCTRL_IN => "1110",
1984  GT0_TXINHIBIT_IN => '0',
1985  GT0_TXMAINCURSOR_IN => (others => '0'),
1986  ------------------ Transmit Ports - TX Data Path interface -----------------
1987  GT0_TXDATA_IN => SFP_TXD_inv(0),
1988  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
1989  GT0_GTXTXN_OUT => SFP0_TXN,
1990  GT0_GTXTXP_OUT => SFP0_TXP,
1991  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
1992  GT0_TXOUTCLK_OUT => SFP_TXOUTCLK(0),
1993  GT0_TXOUTCLKFABRIC_OUT => open,
1994  GT0_TXOUTCLKPCS_OUT => open,
1995  --------------------- Transmit Ports - TX Gearbox Ports --------------------
1996  GT0_TXHEADER_IN => SFP_TXHEADER(0),
1997  GT0_TXSEQUENCE_IN => SFP_TXSEQUENCE(0),
1998  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
1999  GT0_TXRESETDONE_OUT => open,
2000  ------------------ Transmit Ports - pattern Generator Ports ----------------
2001  GT0_TXPRBSSEL_IN => SFP_TXPRBSSEL_IN(0),
2002 
2003 
2004 
2005 
2006 
2007 
2008  --_____________________________________________________________________
2009  --_____________________________________________________________________
2010  --GT1 (X1Y13)
2011 
2012  ---------------------------- Channel - DRP Ports --------------------------
2013  GT1_DRPADDR_IN => SFP_drpaddr(1),
2014  GT1_DRPCLK_IN => DRPclk,
2015  GT1_DRPDI_IN => SFP_drpdi(1),
2016  GT1_DRPDO_OUT => SFP_drpdo(1),
2017  GT1_DRPEN_IN => SFP_drpen(1),
2018  GT1_DRPRDY_OUT => SFP_drprdy(1),
2019  GT1_DRPWE_IN => SFP_drpwe(1),
2020  ------------------------------- Loopback Ports -----------------------------
2021  GT1_LOOPBACK_IN => SFP_LOOPBACK_IN(1),
2022  ------------------------------ Power-Down Ports ----------------------------
2023  GT1_RXPD_IN => SFP_pd(1),
2024  GT1_TXPD_IN => SFP_pd(1),
2025  --------------------- RX Initialization and Reset Ports --------------------
2026  GT1_RXUSERRDY_IN => SFP_rxuserrdy(1),
2027  -------------------------- RX Margin Analysis Ports ------------------------
2028  GT1_EYESCANDATAERROR_OUT => SFP_EYESCANDATAERROR_OUT(1),
2029  ------------------------- Receive Ports - CDR Ports ------------------------
2030  GT1_RXCDRLOCK_OUT => open,
2031  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
2032  GT1_RXUSRCLK_IN => SFP_RXUSRCLK(1),
2033  GT1_RXUSRCLK2_IN => SFP_RXUSRCLK(1),
2034  ------------------ Receive Ports - FPGA RX interface Ports -----------------
2035  GT1_RXDATA_OUT => SFP_RXD_inv(1),
2036  ------------------- Receive Ports - Pattern Checker Ports ------------------
2037  GT1_RXPRBSERR_OUT => SFP_RXPRBSERR_OUT(1),
2038  GT1_RXPRBSSEL_IN => SFP_RXPRBSSEL_IN(1),
2039  ------------------- Receive Ports - Pattern Checker ports ------------------
2040  GT1_RXPRBSCNTRESET_IN => '0',
2041  --------------------------- Receive Ports - RX AFE -------------------------
2042  GT1_GTXRXP_IN => SFP1_RXP,
2043  ------------------------ Receive Ports - RX AFE Ports ----------------------
2044  GT1_GTXRXN_IN => SFP1_RXN,
2045  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
2046  GT1_RXBUFRESET_IN => '0',
2047  GT1_RXBUFSTATUS_OUT => open,
2048  --------------- Receive Ports - RX Fabric Output Control Ports -------------
2049  GT1_RXOUTCLK_OUT => SFP_rxoutclk(1),
2050  ---------------------- Receive Ports - RX Gearbox Ports --------------------
2051  GT1_RXDATAVALID_OUT => SFP_RXDVLD(1),
2052  GT1_RXHEADER_OUT => SFP_RXHEADER(1),
2053  GT1_RXHEADERVALID_OUT => SFP_RXHEADERVLD(1),
2054  --------------------- Receive Ports - RX Gearbox Ports --------------------
2055  GT1_RXGEARBOXSLIP_IN => SFP_RXGEARBOXSLIP(1),
2056  ------------- Receive Ports - RX Initialization and Reset Ports ------------
2057  GT1_GTRXRESET_IN => '0',
2058  GT1_RXPMARESET_IN => '0',
2059  ------------------ Receive Ports - RX Margin Analysis ports ----------------
2060  GT1_RXLPMEN_IN => '0',
2061  -------------- Receive Ports -RX Initialization and Reset Ports ------------
2062  GT1_RXRESETDONE_OUT => SFP_rxresetdone(1),
2063  --------------------- TX Initialization and Reset Ports --------------------
2064  GT1_GTTXRESET_IN => '0',
2065  GT1_TXUSERRDY_IN => SFP_txuserrdy(1),
2066  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
2067  GT1_TXUSRCLK_IN => txusrclk,
2068  GT1_TXUSRCLK2_IN => txusrclk,
2069  --------------- Transmit Ports - TX Configurable Driver Ports --------------
2070  GT1_TXDIFFCTRL_IN => "1110",
2071  GT1_TXINHIBIT_IN => '0',
2072  GT1_TXMAINCURSOR_IN => (others => '0'),
2073  ------------------ Transmit Ports - TX Data Path interface -----------------
2074  GT1_TXDATA_IN => SFP_TXD_inv(1),
2075  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
2076  GT1_GTXTXN_OUT => SFP1_TXN,
2077  GT1_GTXTXP_OUT => SFP1_TXP,
2078  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
2079  GT1_TXOUTCLK_OUT => open,
2080  GT1_TXOUTCLKFABRIC_OUT => open,
2081  GT1_TXOUTCLKPCS_OUT => open,
2082  --------------------- Transmit Ports - TX Gearbox Ports --------------------
2083  GT1_TXHEADER_IN => SFP_TXHEADER(1),
2084  GT1_TXSEQUENCE_IN => SFP_TXSEQUENCE(1),
2085  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
2086  GT1_TXRESETDONE_OUT => open,
2087  ------------------ Transmit Ports - pattern Generator Ports ----------------
2088  GT1_TXPRBSSEL_IN => SFP_TXPRBSSEL_IN(1),
2089 
2090 
2091  --_____________________________________________________________________
2092  --_____________________________________________________________________
2093  --GT2 (X1Y14)
2094 
2095  ---------------------------- Channel - DRP Ports --------------------------
2096  GT2_DRPADDR_IN => SFP_drpaddr(2),
2097  GT2_DRPCLK_IN => DRPclk,
2098  GT2_DRPDI_IN => SFP_drpdi(2),
2099  GT2_DRPDO_OUT => SFP_drpdo(2),
2100  GT2_DRPEN_IN => SFP_drpen(2),
2101  GT2_DRPRDY_OUT => SFP_drprdy(2),
2102  GT2_DRPWE_IN => SFP_drpwe(2),
2103  ------------------------------- Loopback Ports -----------------------------
2104  GT2_LOOPBACK_IN => SFP_LOOPBACK_IN(2),
2105  ------------------------------ Power-Down Ports ----------------------------
2106  GT2_RXPD_IN => SFP_pd(2),
2107  GT2_TXPD_IN => SFP_pd(2),
2108  --------------------- RX Initialization and Reset Ports --------------------
2109  GT2_RXUSERRDY_IN => SFP_rxuserrdy(2),
2110  -------------------------- RX Margin Analysis Ports ------------------------
2111  GT2_EYESCANDATAERROR_OUT => SFP_EYESCANDATAERROR_OUT (2),
2112  ------------------------- Receive Ports - CDR Ports ------------------------
2113  GT2_RXCDRLOCK_OUT => open,
2114  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
2115  GT2_RXUSRCLK_IN => SFP_RXUSRCLK(2),
2116  GT2_RXUSRCLK2_IN => SFP_RXUSRCLK(2),
2117  ------------------ Receive Ports - FPGA RX interface Ports -----------------
2118  GT2_RXDATA_OUT => SFP_RXD_inv(2),
2119  ------------------- Receive Ports - Pattern Checker Ports ------------------
2120  GT2_RXPRBSERR_OUT => SFP_RXPRBSERR_OUT(2),
2121  GT2_RXPRBSSEL_IN => SFP_RXPRBSSEL_IN(2),
2122  ------------------- Receive Ports - Pattern Checker ports ------------------
2123  GT2_RXPRBSCNTRESET_IN => '0',
2124  --------------------------- Receive Ports - RX AFE -------------------------
2125  GT2_GTXRXP_IN => SFP2_RXP,
2126  ------------------------ Receive Ports - RX AFE Ports ----------------------
2127  GT2_GTXRXN_IN => SFP2_RXN,
2128  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
2129  GT2_RXBUFRESET_IN => '0',
2130  GT2_RXBUFSTATUS_OUT => open,
2131  --------------- Receive Ports - RX Fabric Output Control Ports -------------
2132  GT2_RXOUTCLK_OUT => SFP_rxoutclk(2),
2133  ---------------------- Receive Ports - RX Gearbox Ports --------------------
2134  GT2_RXDATAVALID_OUT => SFP_RXDVLD(2),
2135  GT2_RXHEADER_OUT => SFP_RXHEADER(2),
2136  GT2_RXHEADERVALID_OUT => SFP_RXHEADERVLD(2),
2137  --------------------- Receive Ports - RX Gearbox Ports --------------------
2138  GT2_RXGEARBOXSLIP_IN => SFP_RXGEARBOXSLIP(2),
2139  ------------- Receive Ports - RX Initialization and Reset Ports ------------
2140  GT2_GTRXRESET_IN => '0',
2141  GT2_RXPMARESET_IN => '0',
2142  ------------------ Receive Ports - RX Margin Analysis ports ----------------
2143  GT2_RXLPMEN_IN => '0',
2144  -------------- Receive Ports -RX Initialization and Reset Ports ------------
2145  GT2_RXRESETDONE_OUT => SFP_rxresetdone(2),
2146  --------------------- TX Initialization and Reset Ports --------------------
2147  GT2_GTTXRESET_IN => '0',
2148  GT2_TXUSERRDY_IN => SFP_txuserrdy(2),
2149  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
2150  GT2_TXUSRCLK_IN => txusrclk,
2151  GT2_TXUSRCLK2_IN => txusrclk,
2152  --------------- Transmit Ports - TX Configurable Driver Ports --------------
2153  GT2_TXDIFFCTRL_IN => "1110",
2154  GT2_TXINHIBIT_IN => '0',
2155  GT2_TXMAINCURSOR_IN => (others => '0'),
2156  ------------------ Transmit Ports - TX Data Path interface -----------------
2157  GT2_TXDATA_IN => SFP_TXD_inv(2),
2158  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
2159  GT2_GTXTXN_OUT => SFP2_TXN,
2160  GT2_GTXTXP_OUT => SFP2_TXP,
2161  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
2162  GT2_TXOUTCLK_OUT => open,
2163  GT2_TXOUTCLKFABRIC_OUT => open,
2164  GT2_TXOUTCLKPCS_OUT => open,
2165  --------------------- Transmit Ports - TX Gearbox Ports --------------------
2166  GT2_TXHEADER_IN => SFP_TXHEADER(2),
2167  GT2_TXSEQUENCE_IN => SFP_TXSEQUENCE(2),
2168  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
2169  GT2_TXRESETDONE_OUT => open,
2170  ------------------ Transmit Ports - pattern Generator Ports ----------------
2171  GT2_TXPRBSSEL_IN => SFP_TXPRBSSEL_IN(2),
2172 
2173 
2174  --____________________________COMMON PORTS________________________________
2175  ---------------------- Common Block - Ref Clock Ports ---------------------
2176  GT0_GTREFCLK0_COMMON_IN => REFCLK,
2177  ------------------------- Common Block - QPLL Ports ------------------------
2178  GT0_QPLLLOCK_OUT => qplllock,
2179  GT0_QPLLLOCKDETCLK_IN => DRPclk,
2180  GT0_QPLLRESET_IN => qpllreset
2181 
2182  );
2183 process(SFP_TXD,SFP_RXD,SFP_RXD_inv)
2184  begin
2185  for j in 0 to 2 loop
2186  for i in 0 to 31 loop
2187  SFP_TXD_inv(j)(i) <= SFP_TXD(j)(31-i);
2188  SFP_RXD(j)(i) <= SFP_RXD_inv(j)(31-i);
2189  end loop;
2190  end loop;
2191 end process;
2192 i_REFCLK : IBUFDS_GTE2 port map(O => REFCLK, ODIV2 => open, CEB => '0', I => SFP_REFCLK_P, IB => SFP_REFCLK_N);
2193 i_txusrclk : BUFG port map (I => SFP_TXOUTCLK(0), O => txusrclk);
2194 g_SFP_rxusrclk : for i in 0 to 2 generate
2195  i_SFP_rxusrclk : BUFG port map (I => SFP_RXOUTCLK(i), O => SFP_rxusrclk(i));
2196 end generate;
2197 i_REFCLK2X_in: bufg port map(i => REFCLK, o => REFCLK2X_in);
2198 i_ClientClk2X : BUFG port map (I => ClientClk2X_dcm, O => ClientClk2X);
2199 i_ClientClk : BUFG port map (I => ClientClk_dcm, O => ClientClk);
2200 i_REFCLK2XPLLRST : SRL16 generic map(INIT => x"ffff")
2201  port map (
2202  Q => REFCLK2XPLLRST , -- SRL data output
2203  A0 => '1', -- Select[0] input
2204  A1 => '1', -- Select[1] input
2205  A2 => '1', -- Select[2] input
2206  A3 => '1', -- Select[3] input
2207  CLK => REFCLK2X_in, -- Clock input
2208  D => '0' -- SRL data input
2209  );
2210 i_REFCLK2XPLL : PLLE2_BASE
2211  generic map (
2212  BANDWIDTH => "OPTIMIZED", -- OPTIMIZED, HIGH, LOW
2213  CLKFBOUT_MULT => 8, -- Multiply value for all CLKOUT, (2-64)
2214  CLKFBOUT_PHASE => 0.0, -- Phase offset in degrees of CLKFB, (-360.000-360.000).
2215  CLKIN1_PERIOD => 6.4, -- Input clock period in ns to ps resolution (i.e. 33.333 is 30 MHz).
2216  -- CLKOUT0_DIVIDE - CLKOUT5_DIVIDE: Divide amount for each CLKOUT (1-128)
2217  CLKOUT0_DIVIDE => 4,
2218  DIVCLK_DIVIDE => 1, -- Master division value, (1-56)
2219  REF_JITTER1 => 0.0, -- Reference input jitter in UI, (0.000-0.999).
2220  STARTUP_WAIT => "FALSE" -- Delay DONE until PLL Locks, ("TRUE"/"FALSE")
2221  )
2222  port map (
2223  -- Clock Outputs: 1-bit (each) output: User configurable clock outputs
2224  CLKOUT0 => ClientClk2X_dcm,
2225  -- Feedback Clocks: 1-bit (each) output: Clock feedback ports
2226  CLKFBOUT => ClientClk_dcm, -- 1-bit output: Feedback clock
2227  -- Status Port: 1-bit (each) output: PLL status ports
2228  LOCKED => ClientClk_lock , -- 1-bit output: LOCK
2229  -- Clock Input: 1-bit (each) input: Clock input
2230  CLKIN1 => REFCLK2X_in, -- 1-bit input: Input clock
2231  -- Control Ports: 1-bit (each) input: PLL control ports
2232  PWRDWN => '0', -- 1-bit input: Power-down
2233  RST => REFCLK2XPLLRST , -- 1-bit input: Reset
2234  -- Feedback Clocks: 1-bit (each) input: Clock feedback ports
2235  CLKFBIN => ClientClk -- 1-bit input: Feedback clock
2236  );
2237 process(ipb_clk)
2238 begin
2239  if(ipb_clk'event and ipb_clk = '1')then
2240  if(ipb_addr(27) = '0' and ipb_addr(15 downto 0) = x"1c20" and ipb_write = '1' and ipb_strobe = '1')then
2241  en_stop <= ipb_wdata(4 downto 0);
2242  end if;
2243  if(ipb_addr(27) = '0' and ipb_addr(15 downto 0) = x"1c21" and ipb_write = '1' and ipb_strobe = '1')then
2244  SFP_rate_limit(0)(6 downto 0) <= ipb_wdata(6 downto 0);
2245  end if;
2246  if(ipb_addr(27) = '0' and ipb_addr(15 downto 0) = x"1c22" and ipb_write = '1' and ipb_strobe = '1')then
2247  SFP_rate_limit(1)(6 downto 0) <= ipb_wdata(6 downto 0);
2248  end if;
2249  if(ipb_addr(27) = '0' and ipb_addr(15 downto 0) = x"1c23" and ipb_write = '1' and ipb_strobe = '1')then
2250  SFP_rate_limit(2)(6 downto 0) <= ipb_wdata(6 downto 0);
2251  end if;
2252  if(ipb_addr(27) = '0' and ipb_addr(15 downto 0) = x"1c2f" and ipb_write = '1' and ipb_strobe = '1')then
2253  RTOmin <= ipb_wdata(15 downto 0);
2254  end if;
2255  end if;
2256 end process;
2257 process(ipb_addr)
2258 variable s : std_logic_vector(1 downto 0);
2259 begin
2260  case ipb_addr(11 downto 10) is
2261  when "00" =>
2262  case enSFP(2 downto 0) is
2263  when "010" | "011" | "101" | "111" => s := "01";
2264  when "110" => s := "10";
2265  when others => s := "00";
2266  end case;
2267  when "01" =>
2268  case enSFP(2 downto 0) is
2269  when "010" | "011" | "111" => s := "00";
2270  when "101" => s := "10";
2271  when others => s := "01";
2272  end case;
2273  when "10" =>
2274  case enSFP(2 downto 0) is
2275  when "100" | "101" | "110" => s := "00";
2276  when others => s := "10";
2277  end case;
2278  when others => s := "11";
2279  end case;
2280  if(ipb_addr(15 downto 12) = x"1")then
2281  case s is
2282  when "00" =>
2283  if(ipb_addr(9 downto 8) = "11")then
2284  case ipb_addr(3 downto 0) is
2285  when x"0" => ipb_rdata <= TotalEvtLengthCntr(0)(31 downto 0);
2286  when x"1" => ipb_rdata <= x"00" & TotalEvtLengthCntr(0)(55 downto 32);
2287  when x"2" => ipb_rdata <= EvtLength_errCntr(0);
2288  when x"3" => ipb_rdata <= AMClength_errCntr(0);
2289  when x"4" => ipb_rdata <= AMCvalid_errCntr(0);
2290  when x"5" => ipb_rdata <= AMCcrc_errCntr(0);
2291  when others => ipb_rdata <= (others => '0');
2292  end case;
2293  else
2294  ipb_rdata <= TCPIP_rdata(0);
2295  end if;
2296  when "01" =>
2297  if(ipb_addr(9 downto 8) = "11")then
2298  case ipb_addr(3 downto 0) is
2299  when x"0" => ipb_rdata <= TotalEvtLengthCntr(1)(31 downto 0);
2300  when x"1" => ipb_rdata <= x"00" & TotalEvtLengthCntr(1)(55 downto 32);
2301  when x"2" => ipb_rdata <= EvtLength_errCntr(1);
2302  when x"3" => ipb_rdata <= AMClength_errCntr(1);
2303  when x"4" => ipb_rdata <= AMCvalid_errCntr(1);
2304  when x"5" => ipb_rdata <= AMCcrc_errCntr(1);
2305  when others => ipb_rdata <= (others => '0');
2306  end case;
2307  else
2308  ipb_rdata <= TCPIP_rdata(1);
2309  end if;
2310  when "10" =>
2311  if(ipb_addr(9 downto 8) = "11")then
2312  case ipb_addr(3 downto 0) is
2313  when x"0" => ipb_rdata <= TotalEvtLengthCntr(2)(31 downto 0);
2314  when x"1" => ipb_rdata <= x"00" & TotalEvtLengthCntr(2)(55 downto 32);
2315  when x"2" => ipb_rdata <= EvtLength_errCntr(2);
2316  when x"3" => ipb_rdata <= AMClength_errCntr(2);
2317  when x"4" => ipb_rdata <= AMCvalid_errCntr(2);
2318  when x"5" => ipb_rdata <= AMCcrc_errCntr(2);
2319  when others => ipb_rdata <= (others => '0');
2320  end case;
2321  else
2322  ipb_rdata <= TCPIP_rdata(2);
2323  end if;
2324  when others =>
2325  case ipb_addr(5 downto 4) is
2326  when "00" =>
2327  case ipb_addr(3 downto 0) is
2328  when x"0" => ipb_rdata <= "00000" & NXT_MonBuf(1) & "00000" & NXT_MonBuf(0);
2329  when x"1" => ipb_rdata <= x"0000" & "00000" & NXT_MonBuf(2);
2330  when x"2" => ipb_rdata <= "00000" & UNA_MonBuf(1) & "00000" & UNA_MonBuf(0);
2331  when x"3" => ipb_rdata <= "00000" & UNA_MonBuf(3) & "00000" & UNA_MonBuf(2);
2332  when x"4" => ipb_rdata <= x"0000" & "00000" & UNA_MonBuf(4);
2333  when x"5" => ipb_rdata <= x"0" & NXT_TCPBuf(1) & x"0" & NXT_TCPBuf(0);
2334  when x"6" => ipb_rdata <= x"00000" & NXT_TCPBuf(2);
2335  when x"7" => ipb_rdata <= "00000" & UNA_TCPBuf(1) & "00000" & UNA_TCPBuf(0);
2336  when x"8" => ipb_rdata <= "00000" & UNA_TCPBuf(3) & "00000" & UNA_TCPBuf(2);
2337  when x"9" => ipb_rdata <= "00000" & Written_MonBuf(1) & "00000" & Written_MonBuf(0);
2338  when x"a" => ipb_rdata <= "00000" & Written_MonBuf(3) & "00000" & Written_MonBuf(2);
2339  when x"b" => ipb_rdata <= '0' & ReadBusy & '0' & SFP_RXGOOD & x"00" & "00" & sfp_pd(2) & sfp_pd(1) & sfp_pd(0) & '0' & SFP_TX_FSM_RESET_DONE & '0' & SFP_RX_FSM_RESET_DONE;
2340  when x"c" => ipb_rdata <= x"000" & SFP2TCPIP(2) & SFP2TCPIP(1) & SFP2TCPIP(0) & TCPIP2SFP_sel(2) & TCPIP2SFP_sel(1) & TCPIP2SFP_sel(0) & '0' & EnTCPIP & '0' & LINK_down;
2341  when x"d" => ipb_rdata <= cmsCRC_errCntr(0);
2342  when x"e" => ipb_rdata <= cmsCRC_errCntr(1);
2343  when others => ipb_rdata <= cmsCRC_errCntr(2);
2344  end case;
2345  when "01" =>
2346  case ipb_addr(3 downto 0) is
2347  when x"0" => ipb_rdata <= '0' & RETX_ddr_rrqst & '0' & RETX_ddr_wrqst & '0' & EVENTdata_avl & '0' & AddrBuf_full & '0' & evt_FIFO_full & '0' & wport_FIFO_full & '0' & wport_rdy & '0' & evt_data_rdy;
2348  when x"1" => ipb_rdata <= TCP_rrqst_i & TCP_rFIFO_ra & "000" & TCP_rFIFO_wa & "00" & rrqstMask & '0' & RETXdataAck & '0' & RETXdataRqst;
2349  when x"2" => ipb_rdata <= "00000" & MonBuf_wa & "00000" & MonBuf_ra;
2350  when x"3" => ipb_rdata <= EventData_reCntr(0);
2351  when x"4" => ipb_rdata <= EventData_reCntr(1);
2352  when x"5" => ipb_rdata <= EventData_reCntr(2);
2353  when x"6" => ipb_rdata <= EventBufAddr_weCntr(0);
2354  when x"7" => ipb_rdata <= EventBufAddr_weCntr(1);
2355  when x"8" => ipb_rdata <= EventBufAddr_weCntr(2);
2356  when x"9" => ipb_rdata <= EventData_weCntr(0);
2357  when x"a" => ipb_rdata <= EventData_weCntr(1);
2358  when x"b" => ipb_rdata <= EventData_weCntr(2);
2359  when x"c" => ipb_rdata <= SFP_IPADDR(0);
2360  when x"d" => ipb_rdata <= SFP_IPADDR(1);
2361  when x"e" => ipb_rdata <= SFP_IPADDR(2);
2362 -- when others => ipb_rdata <= CWND_max;
2363  when others => ipb_rdata <= (others => '0');
2364  end case;
2365  when "10" =>
2366  case ipb_addr(3 downto 0) is
2367  when x"0" => ipb_rdata <= x"000000" & "000" & en_stop;
2368  when x"1" => ipb_rdata <= x"000000" & SFP_rate_limit(0);
2369  when x"2" => ipb_rdata <= x"000000" & SFP_rate_limit(1);
2370  when x"3" => ipb_rdata <= x"000000" & SFP_rate_limit(2);
2371  when x"4" => ipb_rdata <= SFP_evt_cntr(0);
2372  when x"5" => ipb_rdata <= SFP_evt_cntr(1);
2373  when x"6" => ipb_rdata <= SFP_evt_cntr(2);
2374  when x"8" => ipb_rdata <= SFP_word_cntr(0);
2375  when x"9" => ipb_rdata <= SFP_word_cntr(1);
2376  when x"a" => ipb_rdata <= SFP_word_cntr(2);
2377  when x"c" => ipb_rdata <= SFP_blk_cntr(0);
2378  when x"d" => ipb_rdata <= SFP_blk_cntr(1);
2379  when x"e" => ipb_rdata <= SFP_blk_cntr(2);
2380  when x"f" => ipb_rdata <= x"0000" & RTOmin;
2381  when others => ipb_rdata <= (others => '0');
2382  end case;
2383  when others => ipb_rdata <= (others => '0');
2384  end case;
2385  end case;
2386  else
2387  ipb_rdata <= (others => '0');
2388  end if;
2389 end process;
2390 process(ipb_clk)
2391 begin
2392  if(ipb_clk'event and ipb_clk = '1')then
2393  if(ipb_addr(27) = '0' and ipb_addr(15 downto 2) = "00011100000111" and ipb_strobe = '1' and ipb_write = '1')then
2394  if(ipb_addr(1 downto 0) = "11")then
2395 -- CWND_max <= x"0" & ipb_wdata(27 downto 0);
2396  else
2397  SFP_IPADDR(conv_integer(ipb_addr(1 downto 0))) <= ipb_wdata;
2398  end if;
2399  end if;
2400  end if;
2401 end process;
2402 end Behavioral;
2403 
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