Behavioral Architecture Reference

List of all members.

Functions
boolean	A_GT_B ( A: in std_logic_vector ( 31 downto 0 ) , B: in std_logic_vector ( 31 downto 0 ) )
boolean	A_GE_B ( A: in std_logic_vector ( 31 downto 0 ) , B: in std_logic_vector ( 31 downto 0 ) )

Processes
PROCESS_993	( clk2x )
PROCESS_995	( clk2x )
PROCESS_996	( clk2x )
PROCESS_997	( sysclk ,IS_CONNECTED ,EventBufAddr_wa ,EventBufAddr_ra1SyncRegs ,EventBufAddr_ra0SyncRegs )
PROCESS_998	( sysclk )
PROCESS_999	( clk2x )
PROCESS_1000	( clk2x )
PROCESS_1001	( clk2x )
PROCESS_1002	( clk2x )
PROCESS_1003	( clk2x ,rstCntr )
PROCESS_1004	( ipb_addr )

Components
XGbEMAC	<Entity XGbEMAC>
EMAC_Rx_if	<Entity EMAC_Rx_if>
TCP_OPTION	<Entity TCP_OPTION>
checksum	<Entity checksum>
TCPdata_chksum	<Entity TCPdata_chksum>
FIFO65x12k	<Entity FIFO65x12k>
SDP32x18	<Entity SDP32x18>
RTO_CALC	<Entity RTO_CALC>
TCP_CC	<Entity TCP_CC>
RAM32x6D	<Entity RAM32x6D>
FIFO65x8k	<Entity FIFO65x8k>

Constants
zero	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
N	integer := 8
bit_FIN	integer := 0
bit_SYN	integer := 1
bit_RST	integer := 2
bit_PSH	integer := 3
bit_ACK	integer := 4
INIT_buf_h	bitarray9x64 := ( ( others = > ' 0 ' ) , ( others = > ' 0 ' ) , ( others = > ' 0 ' ) , ( others = > ' 0 ' ) , ( others = > ' 0 ' ) , x " 0000008000000080 " , ( others = > ' 0 ' ) , x " 0000040000000400 " , ( others = > ' 0 ' ) )
INIT_buf_l	bitarray9x64 := ( x " 0000080000000800 " , x " 0000040000000400 " , ( others = > ' 0 ' ) , ( others = > ' 0 ' ) , x " 0000004000000040 " , x " 0000004000000040 " , ( others = > ' 0 ' ) , x " 0000044000000440 " , ( others = > ' 0 ' ) )
waittime	integer := 10
RCV_WND	std_logic_vector ( 31 downto 0 ) := x " 00000001 "

Types
state	( CLOSED , LISTEN , SYNRCVD , ESTAB , LASTACK )
stateC	( IDLE , ReadEventData , Wait4Send )

Signals
EmacClientTack	std_logic := ' 0 '
EmacClientRxGoodFrame	std_logic := ' 0 '
EmacClientRxbadFrame	std_logic := ' 0 '
EmacClientRxd	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
EmacClientRxdWe	std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
ClientEmacTxd	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
ClientEmacTxdVld	std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
CLIENTEMACTXUNDERRUN	std_logic := ' 0 '
en_RxDout	std_logic := ' 0 '
RxDout_avl	std_logic := ' 0 '
RxDout_type	std_logic_vector ( 1 downto 0 ) := ( others = > ' 0 ' )
RxDout_lastword	std_logic := ' 0 '
RxDout_valid	std_logic := ' 0 '
RxDout_valid_dl	std_logic_vector ( 1 downto 0 ) := ( others = > ' 0 ' )
TCPheader_we	std_logic := ' 0 '
RxDoutMSB	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
RxDout	std_logic_vector ( 35 downto 0 ) := ( others = > ' 0 ' )
buf_we	std_logic_vector ( 1 downto 0 ) := ( others = > ' 0 ' )
buf_wa	std_logic_vector ( 4 downto 0 ) := ( others = > ' 0 ' )
buf_ra	std_logic_vector ( 4 downto 0 ) := ( others = > ' 0 ' )
buf_di	std_logic_vector ( 35 downto 0 ) := ( others = > ' 0 ' )
buf_DO	std_logic_vector ( 35 downto 0 ) := ( others = > ' 0 ' )
eof	std_logic := ' 0 '
IS_ARP_ICMP	std_logic := ' 0 '
MUX_TCPHDR	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
headerFIFO_DI	std_logic_vector ( 35 downto 0 ) := ( others = > ' 0 ' )
headerFIFO_DO	std_logic_vector ( 35 downto 0 ) := ( others = > ' 0 ' )
headerFIFO_eof	std_logic := ' 0 '
headerFIFO_AlmostFull	std_logic := ' 0 '
headerFIFO_full	std_logic := ' 0 '
headerFIFO_EMPTY	std_logic := ' 0 '
headerFIFO_RDEN	std_logic := ' 0 '
rd_headerFIFO	std_logic := ' 0 '
headerFIFO_WREN	std_logic := ' 0 '
headerFIFO_RDCOUNT	std_logic_vector ( 8 downto 0 ) := ( others = > ' 0 ' )
headerFIFO_WRCOUNT	std_logic_vector ( 8 downto 0 ) := ( others = > ' 0 ' )
dataFIFO_RDCOUNT	std_logic_vector ( 8 downto 0 ) := ( others = > ' 0 ' )
dataFIFO_WRCOUNT	std_logic_vector ( 8 downto 0 ) := ( others = > ' 0 ' )
dataFIFO_DI	std_logic_vector ( 64 downto 0 ) := ( others = > ' 0 ' )
dataFIFO_DO	std_logic_vector ( 64 downto 0 ) := ( others = > ' 0 ' )
TCPdata	std_logic_vector ( 64 downto 0 ) := ( others = > ' 0 ' )
dataFIFO_full	std_logic := ' 0 '
dataFIFO_eof	std_logic := ' 0 '
dataFIFO_empty	std_logic := ' 0 '
ReTx_FIFO_empty	std_logic := ' 0 '
dataFIFO_RDEN	std_logic := ' 0 '
AttachData	std_logic := ' 0 '
AttachData_dl	std_logic := ' 0 '
dataFIFO_WREN	std_logic := ' 0 '
FIFO_rst	std_logic := ' 0 '
reset_dl	std_logic := ' 0 '
FIFO_en	std_logic := ' 0 '
IP_ID	std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
IP_ID2Send	std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
ReTxIP_ID	std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
TCPdata_q	std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
ClientEmacTxd_sel	std_logic_vector ( 1 downto 0 ) := ( others = > ' 0 ' )
TCPstate	state := CLOSED
TCPstates	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
LISTENing	std_logic := ' 0 '
IS_CLOSED	std_logic := ' 0 '
IS_CONNECTED	std_logic := ' 0 '
en_LINK_SyncRegs	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
CTRLstate	stateB := IDLE
CTRLstates	std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
NOT_MY_PORT	std_logic := ' 0 '
CONN_MATCH	std_logic := ' 0 '
SEG_LEN_IS_0	std_logic := ' 0 '
SEG_SEQ_OR	std_logic := ' 0 '
SEG_SEQ_PLUS_LEN_OR	std_logic := ' 0 '
SND_SPACE_OK	std_logic := ' 0 '
SND_SPACE_CC_OK	std_logic := ' 0 '
SEG_ACK_OK	std_logic := ' 0 '
SEG_ACK_GT_SND_NXT	std_logic := ' 0 '
rdy2send	std_logic := ' 0 '
SND_SYNorFIN	std_logic := ' 0 '
SEG_SYNorFIN	std_logic := ' 0 '
SND_UNACK	std_logic := ' 0 '
update_SND_UNA	std_logic := ' 0 '
update_SND_WND	std_logic := ' 0 '
update_RCV_NXT	std_logic := ' 0 '
update_TSrecent	std_logic := ' 0 '
KEEPALIVEcntr	std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
TIMEWAITcntr	std_logic_vector ( waittime downto 0 ) := ( others = > ' 0 ' )
CTRLcntr	std_logic_vector ( 4 downto 0 ) := ( others = > ' 0 ' )
DestPORT	std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
IPHDR_LEN	std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
IPHDR_END	std_logic_vector ( 4 downto 0 ) := ( others = > ' 0 ' )
SND_UNA	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
SND_NXT	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
SND_WND	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
SND_WND_UL	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
SND_WND_UL_CC	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
SND_SEQ_LAST	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
SND_WND_SCALE	std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
SND_WL1	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
SND_WL2	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
ISS	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
recover	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
TO_recover	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
RCV_NXT	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
RCV_NXT_PLUS_WND	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
IRS	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
SEG_SEQ	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
SEG_SEQ_PLUS_ONE	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
SEG_SEQ_PLUS_LEN	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
SEG_ACK	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
SEG_TCP_LEN	std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
SEG_TCPHDR_LEN	std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
SEG_LEN	std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
tmp_SEG_WND	std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
input_SEG_WND0	std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
input_SEG_WND1	std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
input_SEG_WND2	std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
SEG_WNDp	std_logic_vector ( 18 downto 0 ) := ( others = > ' 0 ' )
SEG_WND	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
SEG_CTRL	std_logic_vector ( 4 downto 0 ) := ( others = > ' 0 ' )
DATA_OFFSET	std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
TCPHDR_cntr	std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
SND_CTRL	std_logic_vector ( 5 downto 0 ) := ( others = > ' 0 ' )
SND_SEQ	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
SND_ACK	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
DATA_LEN	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
HDR_LEN	std_logic_vector ( 13 downto 0 ) := ( others = > ' 0 ' )
TOTAL_LEN	std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
IPHDR_chksum	std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
TCP_LEN	std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
TCP_chksum	std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
DATA_chksum	std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
SavedChksum	std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
ReTxData_avl_dl	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
bad_ReTx_chksum	std_logic := ' 0 '
CWND_GE_SND_WND	std_logic := ' 0 '
OPTION_begin	std_logic := ' 0 '
OPTION_end	std_logic := ' 0 '
OPTION_rdy	std_logic := ' 0 '
rd_OPTION	std_logic := ' 0 '
TS_OPTION	std_logic := ' 0 '
OPTION_do	std_logic_vector ( 35 downto 0 ) := ( others = > ' 0 ' )
MSS	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
MSS_cutoff	std_logic_vector ( 12 downto 0 ) := ( others = > ' 0 ' )
sample_cntr	std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
sum_RTT	std_logic_vector ( 35 downto 0 ) := ( others = > ' 0 ' )
avg_RTT	std_logic_vector ( 27 downto 0 ) := ( others = > ' 0 ' )
RTT_cntr	std_logic_vector ( 27 downto 0 ) := ( others = > ' 0 ' )
TS_RTT	std_logic_vector ( 27 downto 0 ) := ( others = > ' 0 ' )
STD_RTT	std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
sel_SND_DATA	std_logic_vector ( 1 downto 0 ) := ( others = > ' 0 ' )
SND_DATA	std_logic_vector ( 33 downto 0 ) := ( others = > ' 0 ' )
SND_DATA_dl	std_logic_vector ( 33 downto 0 ) := ( others = > ' 0 ' )
OPTION_data	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
TCPHDR_end	std_logic_vector ( 4 downto 0 ) := ( others = > ' 0 ' )
SND_DATA_r	std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
chksum_in	std_logic_vector ( 16 downto 0 ) := ( others = > ' 0 ' )
RTT_cycle	std_logic := ' 0 '
EnNewData	std_logic := ' 0 '
ReTxEntry	std_logic_vector ( 11 downto 0 ) := ( others = > ' 0 ' )
SEGinFLIGHT	std_logic_vector ( 11 downto 0 ) := ( others = > ' 0 ' )
NewDataLimit	std_logic_vector ( 10 downto 0 ) := ( others = > ' 0 ' )
NewDataCntr	std_logic_vector ( 10 downto 0 ) := ( others = > ' 0 ' )
rst_chksum	std_logic := ' 0 '
ce_IPHDR_chksum	std_logic := ' 0 '
ce_TCP_chksum	std_logic := ' 0 '
is_IPHDR_chksum	std_logic := ' 0 '
sel_IPHDR_chksum	std_logic := ' 0 '
is_TCP_chksum	std_logic := ' 0 '
sel_TCP_chksum	std_logic := ' 0 '
SND_DATA_vld	std_logic := ' 0 '
SND_DATA_end	std_logic := ' 0 '
SND_DATA_end_dl	std_logic := ' 0 '
rst_DATA_chksum	std_logic := ' 0 '
DATAstate	stateC := IDLE
DATAstates	std_logic_vector ( 1 downto 0 ) := ( others = > ' 0 ' )
ReTxData_avl	std_logic := ' 0 '
chk_ReTxQueue	std_logic_vector ( 1 downto 0 ) := ( others = > ' 0 ' )
ReTxData	std_logic_vector ( 64 downto 0 ) := ( others = > ' 0 ' )
ReTx_FIFO_h_WRCOUNT	std_logic_vector ( 9 downto 0 ) := ( others = > ' 0 ' )
ReTx_FIFO_h_RDCOUNT	std_logic_vector ( 9 downto 0 ) := ( others = > ' 0 ' )
ReTx_FIFO_l_WRCOUNT	std_logic_vector ( 9 downto 0 ) := ( others = > ' 0 ' )
ReTx_FIFO_l_RDCOUNT	std_logic_vector ( 9 downto 0 ) := ( others = > ' 0 ' )
ReTxDataAddr_i	std_logic_vector ( 25 downto 0 ) := ( others = > ' 0 ' )
ReTxDataLastAddr	std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
SendReTxData	std_logic := ' 0 '
FastReTxData	std_logic := ' 0 '
TO_ReTxData	std_logic := ' 0 '
sel_ReTx_DATA	std_logic := ' 0 '
AddReTxEntry	std_logic := ' 0 '
is_ReTx	std_logic := ' 0 '
ReTxData_re	std_logic := ' 0 '
WaitReTxData	std_logic := ' 0 '
EoB	std_logic := ' 0 '
push	std_logic := ' 0 '
data2send	std_logic := ' 0 '
EVENTdata_re_i	std_logic := ' 0 '
TCP_DATA_LEN	std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
TCP_DATA_chksum	std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
was_IDLE	std_logic := ' 0 '
ReTx_cnt	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
DATA_SIZE	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
ReTxDataLEN_i	std_logic_vector ( 12 downto 0 ) := ( others = > ' 0 ' )
data_wc	std_logic_vector ( 12 downto 0 ) := ( others = > ' 0 ' )
saved_data_wc	std_logic_vector ( 10 downto 0 ) := ( others = > ' 0 ' )
ReTx_ddr_cnt	std_logic_vector ( 12 downto 0 ) := ( others = > ' 0 ' )
ReTx_ddr_empty	std_logic := ' 1 '
ReTx_ddr_full	std_logic := ' 0 '
ReTxQueue_WEA	std_logic := ' 0 '
ReTxQueue_WEB	std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
ReTxQueue_DIA	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
ReTxQueue_DIB	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
ReTxQueue_DOBp	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
ReTxQueue_DOB	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
ReTxQueue_ADDRB	std_logic_vector ( 9 downto 0 ) := ( others = > ' 0 ' )
ReTxQueue_wp	std_logic_vector ( 9 downto 0 ) := ( others = > ' 0 ' )
ReTxQueue_rp	std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
ReleasePending	std_logic := ' 1 '
ReTxentry_avl	std_logic := ' 1 '
ReTxQueue_entry	std_logic_vector ( 8 downto 0 ) := ( others = > ' 0 ' )
ReTx_ddr_wq_we	std_logic := ' 0 '
RETX_ddr_wq_re	std_logic := ' 0 '
ReTx_ddr_wq_ceReg	std_logic := ' 0 '
ReTx_ddr_wrqst_i	std_logic := ' 0 '
ReTx_ddr_rrqst_i	std_logic := ' 0 '
ReTx_ddr_rrqst_q	std_logic := ' 0 '
ReTx_ddr_out_vld	std_logic := ' 0 '
ReTx_ddr_wq_full	std_logic := ' 0 '
ReTx_ddr_LEN_i	std_logic_vector ( 4 downto 0 ) := ( others = > ' 0 ' )
ReTx_ddr_wq_wa	std_logic_vector ( 4 downto 0 ) := ( others = > ' 0 ' )
ReTx_ddr_wq_ra	std_logic_vector ( 4 downto 0 ) := ( others = > ' 0 ' )
ReTx_ddr_wq_wc	std_logic_vector ( 5 downto 0 ) := ( others = > ' 0 ' )
ReTx_ddr_wq_in	std_logic_vector ( 35 downto 0 ) := ( others = > ' 0 ' )
ReTx_ddr_out_i	std_logic_vector ( 35 downto 0 ) := ( others = > ' 0 ' )
sel_ddr	std_logic := ' 0 '
ce_ReTxQueue_rp	std_logic := ' 0 '
update_UNA_Buf	std_logic := ' 0 '
ec_ReTx_ADDR	std_logic := ' 0 '
ReTx_CTRL	std_logic_vector ( 4 downto 0 ) := ( others = > ' 0 ' )
ReTx_SEQ	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
DupACK_cnt	std_logic_vector ( 1 downto 0 ) := ( others = > ' 0 ' )
RELEASE_type	std_logic_vector ( 1 downto 0 ) := ( others = > ' 0 ' )
FastReTx	std_logic := ' 0 '
FastRecovery	std_logic := ' 0 '
TO_Recovery	std_logic := ' 0 '
FastReTxStart	std_logic := ' 0 '
FastReTxDone	std_logic := ' 0 '
TO_ReTxDone	std_logic := ' 0 '
save_ReTx	std_logic := ' 0 '
save_ReTxTime	std_logic := ' 0 '
PartialACK	std_logic_vector ( 1 downto 0 ) := ( others = > ' 0 ' )
wasSYNRCVD	std_logic := ' 0 '
NewDataACK	std_logic := ' 0 '
DupACK	std_logic := ' 0 '
IsDupACK	std_logic := ' 0 '
OldData	std_logic := ' 0 '
sample_RTT	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
time_sample	std_logic := ' 0 '
set_ReTx_TO	std_logic := ' 0 '
set_ReTx_TO_dl	std_logic_vector ( 1 downto 0 ) := ( others = > ' 0 ' )
TSclock11_r	std_logic := ' 0 '
ReTx_TO	std_logic := ' 0 '
ReTxNXT	std_logic := ' 0 '
RTTvld	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
RTO	std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
RTO_timer	std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
RTT	std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
CWND	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
CWND_LTA	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
debug_opt	std_logic_vector ( 135 downto 0 ) := ( others = > ' 0 ' )
debug_RTO	std_logic_vector ( 135 downto 0 ) := ( others = > ' 0 ' )
debug_CC	std_logic_vector ( 271 downto 0 ) := ( others = > ' 0 ' )
ARP_rcvd_cntr	std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
ICMP_rcvd_cntr	std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
inc_ARP_sent	std_logic := ' 0 '
inc_ICMP_sent	std_logic := ' 0 '
ARP_sent_cntr	std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
ICMP_sent_cntr	std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
ReTxData_wc	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
en_RxDout_cntr	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
Tack_cntr	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
ReTx_DataSeg_cntr	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
ReTx_DataErr_cntr	std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
FastReTx_cntr	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
ReTxDataACK_cntr	std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
Save_ReTx_cntr	std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
ReTxNXT_cntr	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
DataSeg_cntr	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
bad_chksum_pair	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
time_cntr	std_logic_vector ( 16 downto 0 ) := ( others = > ' 0 ' )
rate_cntr	std_logic_vector ( 24 downto 0 ) := ( others = > ' 0 ' )
rate	std_logic_vector ( 24 downto 0 ) := ( others = > ' 0 ' )
deadtime_cntr	std_logic_vector ( 25 downto 0 ) := ( others = > ' 0 ' )
deadtime	std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
status	array32x32 := ( others = > ( others = > ' 0 ' ) )
statusb	array32x32 := ( others = > ( others = > ' 0 ' ) )
ReTx_FIFO_WrErr	std_logic := ' 0 '
ReTx_FIFO_WrError	std_logic := ' 0 '
ReTx_FIFO_RdError	std_logic := ' 0 '
ReTxDataRqst_i	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
EMAC_Rx_rdata	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
SEG_ADDR	std_logic_vector ( 25 downto 0 ) := ( others = > ' 0 ' )
EventBufAddr_wa	std_logic_vector ( 4 downto 0 ) := ( others = > ' 0 ' )
EventBufAddr_ra	std_logic_vector ( 4 downto 0 ) := ( others = > ' 0 ' )
EventBufAddr_dop	std_logic_vector ( 13 downto 12 ) := ( others = > ' 0 ' )
EventBufAddr_do	std_logic_vector ( 13 downto 0 ) := ( others = > ' 0 ' )
EventBufAddr_ra1SyncRegs	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
EventBufAddr_ra0SyncRegs	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
DAQ_header	std_logic := ' 0 '
bad_ReTx_LEN	std_logic := ' 0 '
ReTxDataCntr	std_logic_vector ( 13 downto 0 ) := ( others = > ' 0 ' )
bad_LEN_pair	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
bad_ReTx_LENCntr	std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
bad_ReTx_chksumCntr	std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
DupAckCntr	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
NewAckCntr	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
UNA_MonBuf_i	std_logic_vector ( 10 downto 0 ) := ( others = > ' 0 ' )
KiloByte_toggleSyncRegs	std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
EoB_toggleSyncRegs	std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
Written_MonBuf	std_logic_vector ( 10 downto 0 ) := ( others = > ' 0 ' )
ADDR_offset	std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
Written_MonBlock	std_logic_vector ( 8 downto 0 ) := ( others = > ' 0 ' )
ddr_wptr	std_logic_vector ( 18 downto 0 ) := ( others = > ' 0 ' )
ddr_rptr	std_logic_vector ( 18 downto 0 ) := ( others = > ' 0 ' )
entry_in_ddr	std_logic_vector ( 18 downto 0 ) := ( others = > ' 0 ' )
CLOSE_flag	std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
rate_pause	std_logic := ' 0 '
delta_rate	std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
wc	std_logic_vector ( 21 downto 0 ) := ( others = > ' 0 ' )

Instantiations
i_XGbEMAC	XGbEMAC <Entity XGbEMAC>
i_EMAC_Rx_if	EMAC_Rx_if <Entity EMAC_Rx_if>
i_buf_H	SDP32x18 <Entity SDP32x18>
i_buf_L	SDP32x18 <Entity SDP32x18>
i_ReTx_FIFO	FIFO65x8k <Entity FIFO65x8k>
i_IPHDR_checksum	checksum <Entity checksum>
i_TCP_checksum	checksum <Entity checksum>
i_TCP_OPTION	TCP_OPTION <Entity TCP_OPTION>
i_EventBufAddr	RAM32x6D <Entity RAM32x6D>
i_TCPdata_chksum	TCPdata_chksum <Entity TCPdata_chksum>
i_dataFIFO	FIFO65x12k <Entity FIFO65x12k>
i_ReTx_ddr_wq	RAM32x6D <Entity RAM32x6D>
i_RTO_CALC	RTO_CALC <Entity RTO_CALC>
i_TCP_CC	TCP_CC <Entity TCP_CC>

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Detailed Description

Definition at line 94 of file TCPIP.vhd.

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The documentation for this class was generated from the following files:

• src/TCPIP_if/TCPIP.vhd