AMC13
Firmwares for the different applications of the AMC13 uTCA board made at Boston University
 All Classes Variables
TCPIP.vhd
1 ----------------------------------------------------------------------------------
2 -- Company:
3 -- Engineer:
4 --
5 -- Create Date: 10:32:01 07/14/2013
6 -- Design Name:
7 -- Module Name: IP_test - Behavioral
8 -- Project Name:
9 -- Target Devices:
10 -- Tool versions:
11 -- Description:
12 --
13 -- Dependencies:
14 --
15 -- Revision:
16 -- Revision 0.01 - File Created
17 -- Additional Comments:
18 --
19 ----------------------------------------------------------------------------------
20 library IEEE;
21 use IEEE.STD_LOGIC_1164.ALL;
22 use IEEE.STD_LOGIC_ARITH.ALL;
23 use IEEE.STD_LOGIC_UNSIGNED.ALL;
24 use IEEE.std_logic_misc.all;
25 use IEEE.numeric_std.all;
26 use work.amc13_pack.all;
27 
28 -- Uncomment the following library declaration if using
29 -- arithmetic functions with Signed or Unsigned values
30 --use IEEE.NUMERIC_STD.ALL;
31 
32 -- Uncomment the following library declaration if instantiating
33 -- any Xilinx primitives in this code.
34 -- This module uses NewReno modification to TCP's Fast Recovery Algorithm [RFC2582]
35 library UNISIM;
36 use UNISIM.VComponents.all;
37 Library UNIMACRO;
38 use UNIMACRO.vcomponents.all;
39 
40 entity TCPIP is
41  generic (simulation : boolean := false; en_KEEPALIVE : std_logic := '0');
42  Port (
43  reset : IN std_logic;
44  rstCntr : IN std_logic;
45  sysclk : IN std_logic;
46  clk2x : IN std_logic; -- 2xSFP_REFCLK 312.5MHz norminal
47  clk : IN std_logic;
48  strobe_us : IN std_logic;
49  strobe_ms : IN std_logic;
50  en_LINK : IN std_logic;
51  LINK_down : OUT std_logic;
52  MY_PORT : in STD_LOGIC_VECTOR (15 downto 0); -- my TCP port number
53  MY_IP : in STD_LOGIC_VECTOR (31 downto 0); -- my IP address
54  MY_ETH : in STD_LOGIC_VECTOR (47 downto 0); -- my Ethernet address
55  TSclock : in STD_LOGIC_VECTOR (31 downto 0);
56  RTOmin : in STD_LOGIC_VECTOR (15 downto 0);
57 -- CWND_max : in STD_LOGIC_VECTOR (31 downto 0);
58  rate_limit : in STD_LOGIC_VECTOR (7 downto 0);
59  EVENTdata : in STD_LOGIC_VECTOR (66 downto 0); -- bit 67 BoE, bit 66 EoE, bit 65 BoB and bit 64 EoB
60  EventBufAddr : IN std_logic_vector(13 downto 0);
61  EventBufAddr_we : IN std_logic;
62  AddrBuf_full : OUT std_logic;
63  EVENTdata_avl : IN std_logic; -- source must have either EOE or at least 8kbytes of data in its buffer
64  EVENTdata_re : OUT std_logic; -- could be paused if dataFIFO_full is asserted
65  DDR2TCPdata : in STD_LOGIC_VECTOR (32 downto 0); -- Bit 33 marks the end of ReTxData
66  ReTxData_we : in std_logic_VECTOR (1 downto 0);
67  ReTxData_chksum : in std_logic_VECTOR (15 downto 0);
68  ReTx_ddr_out : out STD_LOGIC_VECTOR (31 downto 0);
69  re_RETX_ddr_wq : IN std_logic;
70  ReTx_ddr_wrqst : OUT std_logic;
71  ReTx_ddr_LEN_max : in STD_LOGIC_VECTOR (4 downto 0); -- in unit of 64 bytess
72  ReTx_ddr_LEN : out STD_LOGIC_VECTOR (4 downto 0); -- in unit of 64 bytess
73  ReTx_ddr_data_we : IN std_logic;
74  ReTx_ddr_rrqst : OUT std_logic;
75  ReTxDataACK : IN std_logic;
76  ReTxDataRqst : OUT std_logic;
77  ReTxDataAddr : out STD_LOGIC_VECTOR (25 downto 0); -- in unit of 64bit words
78  ReTxDataLEN : out STD_LOGIC_VECTOR (12 downto 0); -- in unit of 64bit words
79  KiloByte_toggle : in STD_LOGIC;
80  EoB_toggle : in STD_LOGIC;
81  TCP_wcount : in STD_LOGIC;
82  UNA_MonBuf : out STD_LOGIC_VECTOR (10 downto 0);
83  UNA_TCPBuf : out STD_LOGIC_VECTOR (10 downto 0);
84  PhyEmacRxC : in STD_LOGIC_VECTOR (3 downto 0);
85  PhyEmacRxD : in STD_LOGIC_VECTOR (31 downto 0);
86  EmacPhyTxC : out STD_LOGIC_VECTOR (3 downto 0) := (others => '0');
87  EmacPhyTxD : out STD_LOGIC_VECTOR (31 downto 0) := (others => '0');
88  ipb_addr : in STD_LOGIC_VECTOR(31 downto 0);
89  ipb_rdata : out STD_LOGIC_VECTOR(31 downto 0);
90  cs_out : out STD_LOGIC_VECTOR (511 downto 0)
91  );
92 end TCPIP;
93 
94 architecture Behavioral of TCPIP is
95 function A_GT_B (A, B : std_logic_vector(31 downto 0)) return boolean is
96 variable tmp : std_logic_vector(31 downto 0);
97 begin
98  tmp := A - B;
99  if(tmp(31) = '0' and or_reduce(tmp(30 downto 0)) = '1')then
100  return true;
101  else
102  return false;
103  end if;
104 end A_GT_B;
105 function A_GE_B (A, B : std_logic_vector(31 downto 0)) return boolean is
106 variable tmp : std_logic_vector(31 downto 0);
107 begin
108  tmp := A - B;
109  if(tmp(31) = '0')then
110  return true;
111  else
112  return false;
113  end if;
114 end A_GE_B;
115 COMPONENT XGbEMAC
116  PORT(
117  clk : IN std_logic;
118  reset : IN std_logic;
119  enTxJumboFrame : IN std_logic;
120  enRxJumboFrame : IN std_logic;
121  PhyEmacRxc : IN std_logic_vector(3 downto 0);
122  PhyEmacRxd : IN std_logic_vector(31 downto 0);
123  ClientEmacTxd : IN std_logic_vector(31 downto 0);
124  ClientEmacTxdVld : IN std_logic_vector(3 downto 0);
125  ClientEmacTxUnderrun : IN std_logic;
126  EmacPhyTxc : OUT std_logic_vector(3 downto 0);
127  EmacPhyTxd : OUT std_logic_vector(31 downto 0);
128  EmacClientTack : OUT std_logic;
129  EmacClientRxd : OUT std_logic_vector(31 downto 0);
130  EmacClientRxdWe : OUT std_logic_vector(3 downto 0);
131  EmacClientRxGoodFrame : OUT std_logic;
132  EmacClientRxbadFrame : OUT std_logic
133  );
134 END COMPONENT;
135 COMPONENT EMAC_Rx_if
136  PORT(
137  clk : IN std_logic;
138  reset : IN std_logic;
139  rstCntr : IN std_logic;
140  no_TCP_DATA : IN std_logic;
141  EMAC_RxD : IN std_logic_vector(31 downto 0);
142  EMAC_RxDVLD : IN std_logic_vector(3 downto 0);
143  EMAC_RxGoodFrame : IN std_logic;
144  EMAC_RxBadFrame : IN std_logic;
145  MY_IP : IN std_logic_vector(31 downto 0);
146  MY_ETH : IN std_logic_vector(47 downto 0);
147  en_Dout : IN std_logic;
148  Dout_avl : OUT std_logic;
149  Dout_type : out STD_LOGIC_VECTOR (1 downto 0):= "00";
150  Dout : OUT std_logic_vector(35 downto 0);
151  last_word : OUT std_logic;
152  Dout_valid : OUT std_logic;
153  ipb_addr : in STD_LOGIC_VECTOR(31 downto 0);
154  ipb_rdata : out STD_LOGIC_VECTOR(31 downto 0);
155  csa : out STD_LOGIC_VECTOR (135 downto 0);
156  csb : out STD_LOGIC_VECTOR (135 downto 0)
157  );
158 END COMPONENT;
159 COMPONENT TCP_OPTION
160  PORT(
161  clk : IN std_logic;
162  CLOSED : IN std_logic;
163  update_TSrecent : IN std_logic;
164  TSclock : IN std_logic_vector(31 downto 0);
165  RCV_SYN : IN std_logic;
166  SND_SYN : IN std_logic;
167  LISTEN : IN std_logic;
168  Save_ReTx : in STD_LOGIC;
169  Save_ReTxTime : in STD_LOGIC;
170  OPTION_begin : IN std_logic;
171  OPTION_end : IN std_logic;
172  di : IN std_logic_vector(31 downto 0);
173  rd_dout : IN std_logic;
174  scale : OUT std_logic_vector(3 downto 0);
175  DATA_OFFSET : OUT std_logic_vector(3 downto 0);
176  MSS : OUT std_logic_vector(15 downto 0);
177  RTT : OUT std_logic_vector(27 downto 0);
178  OPTION_rdy : OUT std_logic;
179  TS_OPTION : OUT std_logic;
180  OldData : out STD_LOGIC;
181  dout : OUT std_logic_vector(31 downto 0);
182  debug : OUT std_logic_vector(135 downto 0)
183  );
184 END COMPONENT;
185 COMPONENT checksum
186  PORT(
187  c : IN std_logic;
188  r : IN std_logic;
189  r_value : IN std_logic_vector(15 downto 0);
190  ce : IN std_logic;
191  d : IN std_logic_vector(16 downto 0);
192  bad_chksum : OUT std_logic;
193  s : OUT std_logic_vector(15 downto 0)
194  );
195 END COMPONENT;
196 COMPONENT TCPdata_chksum
197  PORT(
198  c : IN std_logic;
199  r : IN std_logic;
200  ce : IN std_logic;
201  d : IN std_logic_vector(63 downto 0);
202  DATA_OFFSET : IN std_logic_vector(3 downto 0);
203  length_in : IN std_logic_vector(12 downto 0);
204  en_out : IN std_logic;
205  s : OUT std_logic_vector(15 downto 0);
206  chksum : OUT std_logic_vector(15 downto 0);
207  DATA_SIZE : OUT std_logic_vector(31 downto 0);
208  DATA_LEN : OUT std_logic_vector(15 downto 0)
209  );
210 END COMPONENT;
211 COMPONENT FIFO65x12k
212  generic(ALMOSTFULL_OFFSET : bit_vector(15 downto 0) := x"0008");
213  PORT(
214  clk : IN std_logic;
215  fifo_rst : IN std_logic;
216  fifo_en : IN std_logic;
217  di : IN std_logic_vector(64 downto 0);
218  we : IN std_logic;
219  re : IN std_logic;
220  do : OUT std_logic_vector(64 downto 0);
221  full : OUT std_logic;
222  empty : OUT std_logic
223  );
224 END COMPONENT;
225 COMPONENT SDP32x18
226  generic (INIT : bitarray9x64);
227  PORT(
228  clk : IN std_logic;
229  we : IN std_logic;
230  DI : IN std_logic_vector(17 downto 0);
231  WA : IN std_logic_vector(4 downto 0);
232  RA : IN std_logic_vector(4 downto 0);
233  DO : OUT std_logic_vector(17 downto 0)
234  );
235 END COMPONENT;
236 COMPONENT RTO_CALC
237  PORT(
238  clk : IN std_logic;
239  RTT : IN std_logic_vector(15 downto 0);
240  RTOmin : IN std_logic_vector(15 downto 0);
241  LISTEN : IN std_logic;
242  RTO_backoff : IN std_logic;
243  sample_RTT : IN std_logic;
244  RTO : OUT std_logic_vector(15 downto 0);
245  debug : OUT std_logic_vector(135 downto 0)
246  );
247 END COMPONENT;
248 COMPONENT TCP_CC
249  PORT(
250  clk : IN std_logic;
251  reset : IN std_logic;
252  SYNRCVD : IN std_logic;
253  ReTx_TO : IN std_logic;
254  Save_ReTx : IN std_logic;
255  FastReTxStart : in STD_LOGIC;
256  FR : in STD_LOGIC;
257  NewDataACK : IN std_logic;
258  PartialACK : IN std_logic;
259  DupACK : IN std_logic;
260  MSS : IN std_logic_vector(15 downto 0);
261 -- CWND_max : IN std_logic_vector(31 downto 0);
262  SEG_WND : IN std_logic_vector(31 downto 0);
263  SND_UNA : IN std_logic_vector(31 downto 0);
264  SND_NXT : IN std_logic_vector(31 downto 0);
265  CWND : OUT std_logic_vector(31 downto 0);
266  SND_WND_UL : OUT std_logic_vector(31 downto 0);
267  debug : OUT std_logic_vector(271 downto 0)
268  );
269 END COMPONENT;
270 COMPONENT RAM32x6D
271  PORT(
272  wclk : IN std_logic;
273  rclk : IN std_logic;
274  di : IN std_logic_vector(5 downto 0);
275  we : IN std_logic;
276  wa : IN std_logic_vector(4 downto 0);
277  ra : IN std_logic_vector(4 downto 0);
278  ceReg : IN std_logic;
279  do : OUT std_logic_vector(5 downto 0)
280  );
281 END COMPONENT;
282 COMPONENT FIFO65x8k
283  PORT(
284  clk : IN std_logic;
285  fifo_rst : IN std_logic;
286  fifo_en : IN std_logic;
287  di : IN std_logic_vector(32 downto 0);
288  we : IN std_logic_vector(1 downto 0);
289  re : IN std_logic;
290  do : OUT std_logic_vector(64 downto 0);
291  FIFO_WrErr : OUT std_logic;
292  empty : OUT std_logic
293  );
294 END COMPONENT;
295 constant zero : std_logic_vector(31 downto 0) := (others => '0');
296 constant N : integer := 8;
297 constant bit_FIN : integer := 0;
298 constant bit_SYN : integer := 1;
299 constant bit_RST : integer := 2;
300 constant bit_PSH : integer := 3;
301 constant bit_ACK : integer := 4;
302 constant INIT_buf_h : bitarray9x64 := ((others => '0'),(others => '0'),(others => '0'),(others => '0'),(others => '0'),x"0000008000000080",
303  (others => '0'),x"0000040000000400",(others => '0'));
304 constant INIT_buf_l : bitarray9x64 := (x"0000080000000800",x"0000040000000400",(others => '0'),(others => '0'),x"0000004000000040",
305  x"0000004000000040",(others => '0'),x"0000044000000440",(others => '0'));
306 signal EmacClientTack : std_logic := '0';
307 signal EmacClientRxGoodFrame : std_logic := '0';
308 signal EmacClientRxbadFrame : std_logic := '0';
309 signal EmacClientRxd : std_logic_vector(31 downto 0) := (others => '0');
310 signal EmacClientRxdWe : std_logic_vector(3 downto 0) := (others => '0');
311 signal ClientEmacTxd : std_logic_vector(31 downto 0) := (others => '0');
312 signal ClientEmacTxdVld : std_logic_vector(3 downto 0) := (others => '0');
313 signal CLIENTEMACTXUNDERRUN : std_logic := '0';
314 signal en_RxDout : std_logic := '0';
315 signal RxDout_avl : std_logic := '0';
316 signal RxDout_type : std_logic_vector(1 downto 0) := (others => '0');
317 signal RxDout_lastword : std_logic := '0';
318 signal RxDout_valid : std_logic := '0';
319 signal RxDout_valid_dl : std_logic_vector(1 downto 0) := (others => '0');
320 signal TCPheader_we : std_logic := '0';
321 signal RxDoutMSB : std_logic_vector(2 downto 0) := (others => '0');
322 signal RxDout : std_logic_vector(35 downto 0) := (others => '0');
323 signal buf_we : std_logic_vector(1 downto 0) := (others => '0');
324 signal buf_wa : std_logic_vector(4 downto 0) := (others => '0');
325 signal buf_ra : std_logic_vector(4 downto 0) := (others => '0');
326 signal buf_di : std_logic_vector(35 downto 0) := (others => '0');
327 signal buf_DO : std_logic_vector(35 downto 0) := (others => '0');
328 signal eof : std_logic := '0';
329 signal IS_ARP_ICMP : std_logic := '0';
330 signal MUX_TCPHDR : std_logic_vector(31 downto 0) := (others => '0');
331 signal headerFIFO_DI : std_logic_vector(35 downto 0) := (others => '0');
332 signal headerFIFO_DO : std_logic_vector(35 downto 0) := (others => '0');
333 signal headerFIFO_eof : std_logic := '0';
334 signal headerFIFO_AlmostFull : std_logic := '0';
335 signal headerFIFO_full : std_logic := '0';
336 signal headerFIFO_EMPTY : std_logic := '0';
337 signal headerFIFO_RDEN : std_logic := '0';
338 signal rd_headerFIFO : std_logic := '0';
339 signal headerFIFO_WREN : std_logic := '0';
340 signal headerFIFO_RDCOUNT : std_logic_vector(8 downto 0) := (others => '0');
341 signal headerFIFO_WRCOUNT : std_logic_vector(8 downto 0) := (others => '0');
342 signal dataFIFO_RDCOUNT : std_logic_vector(8 downto 0) := (others => '0');
343 signal dataFIFO_WRCOUNT : std_logic_vector(8 downto 0) := (others => '0');
344 signal dataFIFO_DI : std_logic_vector(64 downto 0) := (others => '0');
345 signal dataFIFO_DO : std_logic_vector(64 downto 0) := (others => '0');
346 signal TCPdata : std_logic_vector(64 downto 0) := (others => '0');
347 signal dataFIFO_full : std_logic := '0';
348 signal dataFIFO_eof : std_logic := '0';
349 signal dataFIFO_empty : std_logic := '0';
350 signal ReTx_FIFO_empty : std_logic := '0';
351 signal dataFIFO_RDEN : std_logic := '0';
352 signal AttachData : std_logic := '0';
353 signal AttachData_dl : std_logic := '0';
354 signal dataFIFO_WREN : std_logic := '0';
355 signal FIFO_rst : std_logic := '0';
356 signal reset_dl : std_logic := '0';
357 signal FIFO_en : std_logic := '0';
358 signal IP_ID : std_logic_vector(15 downto 0) := (others => '0');
359 signal IP_ID2Send : std_logic_vector(15 downto 0) := (others => '0');
360 signal ReTxIP_ID : std_logic_vector(15 downto 0) := (others => '0');
361 signal TCPdata_q : std_logic_vector(15 downto 0) := (others => '0');
362 signal ClientEmacTxd_sel : std_logic_vector(1 downto 0) := (others => '0');
363 type state is (CLOSED, LISTEN, SYNRCVD, ESTAB, LASTACK);
364 signal TCPstate : state := CLOSED;
365 signal TCPstates : std_logic_vector(2 downto 0) := (others => '0');
366 signal LISTENing : std_logic := '0';
367 signal IS_CLOSED : std_logic := '0';
368 signal IS_CONNECTED : std_logic := '0';
369 signal en_LINK_SyncRegs : std_logic_vector(2 downto 0) := (others => '0');
370 type stateB is (IDLE, SND_ARP_ICMP, RCV_IPHDR, RCV_TCPHDR, RCV_PROCESS, SND, WAIT4SND2END, RELEASE, RETX);
371 signal CTRLstate : stateB := IDLE;
372 signal CTRLstates : std_logic_vector(3 downto 0) := (others => '0');
373 signal NOT_MY_PORT : std_logic := '0';
374 signal CONN_MATCH : std_logic := '0';
375 signal SEG_LEN_IS_0 : std_logic := '0';
376 signal SEG_SEQ_OR : std_logic := '0';
377 signal SEG_SEQ_PLUS_LEN_OR : std_logic := '0';
378 signal SND_SPACE_OK : std_logic := '0';
379 signal SND_SPACE_CC_OK : std_logic := '0';
380 signal SEG_ACK_OK : std_logic := '0';
381 signal SEG_ACK_GT_SND_NXT : std_logic := '0';
382 signal rdy2send : std_logic := '0';
383 signal SND_SYNorFIN : std_logic := '0';
384 signal SEG_SYNorFIN : std_logic := '0';
385 signal SND_UNACK : std_logic := '0';
386 signal update_SND_UNA : std_logic := '0';
387 signal update_SND_WND : std_logic := '0';
388 signal update_RCV_NXT : std_logic := '0';
389 signal update_TSrecent : std_logic := '0';
390 signal KEEPALIVEcntr : std_logic_vector(15 downto 0) := (others => '0');
391 constant waittime : integer := 10;-- 10 about 1 second and 16 about one minute
392 signal TIMEWAITcntr : std_logic_vector(waittime downto 0) := (others => '0');
393 signal CTRLcntr : std_logic_vector(4 downto 0) := (others => '0');
394 signal DestPORT : std_logic_vector(15 downto 0) := (others => '0');
395 signal IPHDR_LEN : std_logic_vector(15 downto 0) := (others => '0');
396 signal IPHDR_END : std_logic_vector(4 downto 0) := (others => '0');
397 signal SND_UNA : std_logic_vector(31 downto 0) := (others => '0');
398 signal SND_NXT : std_logic_vector(31 downto 0) := (others => '0');
399 signal SND_WND : std_logic_vector(31 downto 0) := (others => '0');
400 signal SND_WND_UL : std_logic_vector(31 downto 0) := (others => '0');
401 signal SND_WND_UL_CC : std_logic_vector(31 downto 0) := (others => '0');
402 signal SND_SEQ_LAST : std_logic_vector(31 downto 0) := (others => '0');
403 signal SND_WND_SCALE : std_logic_vector(3 downto 0) := (others => '0');
404 signal SND_WL1 : std_logic_vector(31 downto 0) := (others => '0');
405 signal SND_WL2 : std_logic_vector(31 downto 0) := (others => '0');
406 signal ISS : std_logic_vector(31 downto 0) := (others => '0');
407 signal recover : std_logic_vector(31 downto 0) := (others => '0');
408 signal TO_recover : std_logic_vector(31 downto 0) := (others => '0');
409 signal RCV_NXT : std_logic_vector(31 downto 0) := (others => '0');
410 constant RCV_WND : std_logic_vector(31 downto 0) := x"00000001";
411 signal RCV_NXT_PLUS_WND : std_logic_vector(31 downto 0) := (others => '0');
412 signal IRS : std_logic_vector(31 downto 0) := (others => '0');
413 signal SEG_SEQ : std_logic_vector(31 downto 0) := (others => '0');
414 signal SEG_SEQ_PLUS_ONE : std_logic_vector(31 downto 0) := (others => '0');
415 signal SEG_SEQ_PLUS_LEN : std_logic_vector(31 downto 0) := (others => '0');
416 signal SEG_ACK : std_logic_vector(31 downto 0) := (others => '0');
417 signal SEG_TCP_LEN : std_logic_vector(15 downto 0) := (others => '0');
418 signal SEG_TCPHDR_LEN : std_logic_vector(15 downto 0) := (others => '0');
419 signal SEG_LEN : std_logic_vector(15 downto 0) := (others => '0');
420 signal tmp_SEG_WND : std_logic_vector(15 downto 0) := (others => '0');
421 signal input_SEG_WND0 : std_logic_vector(15 downto 0) := (others => '0');
422 signal input_SEG_WND1 : std_logic_vector(15 downto 0) := (others => '0');
423 signal input_SEG_WND2 : std_logic_vector(15 downto 0) := (others => '0');
424 signal SEG_WNDp : std_logic_vector(18 downto 0) := (others => '0');
425 signal SEG_WND : std_logic_vector(31 downto 0) := (others => '0');
426 signal SEG_CTRL : std_logic_vector(4 downto 0) := (others => '0');
427 signal DATA_OFFSET : std_logic_vector(3 downto 0) := (others => '0');
428 signal TCPHDR_cntr : std_logic_vector(3 downto 0) := (others => '0');
429 signal SND_CTRL : std_logic_vector(5 downto 0) := (others => '0');
430 signal SND_SEQ : std_logic_vector(31 downto 0) := (others => '0');
431 signal SND_ACK : std_logic_vector(31 downto 0) := (others => '0');
432 signal DATA_LEN : std_logic_vector(31 downto 0) := (others => '0');
433 signal HDR_LEN : std_logic_vector(13 downto 0) := (others => '0');
434 signal TOTAL_LEN : std_logic_vector(15 downto 0) := (others => '0');
435 signal IPHDR_chksum : std_logic_vector(15 downto 0) := (others => '0');
436 signal TCP_LEN : std_logic_vector(15 downto 0) := (others => '0');
437 signal TCP_chksum : std_logic_vector(15 downto 0) := (others => '0');
438 signal DATA_chksum : std_logic_vector(15 downto 0) := (others => '0');
439 signal SavedChksum : std_logic_vector(15 downto 0) := (others => '0');
440 signal ReTxData_avl_dl : std_logic_vector(2 downto 0) := (others => '0');
441 signal bad_ReTx_chksum : std_logic := '0';
442 signal CWND_GE_SND_WND : std_logic := '0';
443 signal OPTION_begin : std_logic := '0';
444 signal OPTION_end : std_logic := '0';
445 signal OPTION_rdy : std_logic := '0';
446 signal rd_OPTION : std_logic := '0';
447 signal TS_OPTION : std_logic := '0';
448 signal OPTION_do : std_logic_vector(35 downto 0) := (others => '0');
449 signal MSS : std_logic_vector(31 downto 0) := (others => '0');
450 signal MSS_cutoff : std_logic_vector(12 downto 0) := (others => '0');
451 signal sample_cntr : std_logic_vector(7 downto 0) := (others => '0');
452 signal sum_RTT : std_logic_vector(35 downto 0) := (others => '0');
453 signal avg_RTT : std_logic_vector(27 downto 0) := (others => '0');
454 signal RTT_cntr : std_logic_vector(27 downto 0) := (others => '0');
455 signal TS_RTT : std_logic_vector(27 downto 0) := (others => '0');
456 signal STD_RTT : std_logic_vector(15 downto 0) := (others => '0');
457 signal sel_SND_DATA : std_logic_vector(1 downto 0) := (others => '0');
458 signal SND_DATA : std_logic_vector(33 downto 0) := (others => '0');
459 signal SND_DATA_dl : std_logic_vector(33 downto 0) := (others => '0');
460 signal OPTION_data : std_logic_vector(31 downto 0) := (others => '0');
461 signal TCPHDR_end : std_logic_vector(4 downto 0) := (others => '0');
462 signal SND_DATA_r : std_logic_vector(15 downto 0) := (others => '0');
463 signal chksum_in : std_logic_vector(16 downto 0) := (others => '0');
464 signal RTT_cycle : std_logic := '0';
465 signal EnNewData : std_logic := '0';
466 signal ReTxEntry :std_logic_vector(11 downto 0) := (others => '0');
467 signal SEGinFLIGHT :std_logic_vector(11 downto 0) := (others => '0');
468 signal NewDataLimit :std_logic_vector(10 downto 0) := (others => '0');
469 signal NewDataCntr :std_logic_vector(10 downto 0) := (others => '0');
470 signal rst_chksum : std_logic := '0';
471 signal ce_IPHDR_chksum : std_logic := '0';
472 signal ce_TCP_chksum : std_logic := '0';
473 signal is_IPHDR_chksum : std_logic := '0';
474 signal sel_IPHDR_chksum : std_logic := '0';
475 signal is_TCP_chksum : std_logic := '0';
476 signal sel_TCP_chksum : std_logic := '0';
477 signal SND_DATA_vld : std_logic := '0';
478 signal SND_DATA_end : std_logic := '0';
479 signal SND_DATA_end_dl : std_logic := '0';
480 signal rst_DATA_chksum : std_logic := '0';
481 type stateC is (IDLE, ReadEventData, Wait4Send);
482 signal DATAstate : stateC := IDLE;
483 signal DATAstates : std_logic_vector(1 downto 0) := (others => '0');
484 signal ReTxData_avl : std_logic := '0';
485 signal chk_ReTxQueue : std_logic_vector(1 downto 0) := (others => '0');
486 signal ReTxData : std_logic_vector(64 downto 0) := (others => '0');
487 signal ReTx_FIFO_h_WRCOUNT : std_logic_vector(9 downto 0) := (others => '0');
488 signal ReTx_FIFO_h_RDCOUNT : std_logic_vector(9 downto 0) := (others => '0');
489 signal ReTx_FIFO_l_WRCOUNT : std_logic_vector(9 downto 0) := (others => '0');
490 signal ReTx_FIFO_l_RDCOUNT : std_logic_vector(9 downto 0) := (others => '0');
491 signal ReTxDataAddr_i : std_logic_vector(25 downto 0) := (others => '0');
492 signal ReTxDataLastAddr : std_logic_vector(15 downto 0) := (others => '0');
493 signal SendReTxData : std_logic := '0';
494 signal FastReTxData : std_logic := '0';
495 signal TO_ReTxData : std_logic := '0';
496 signal sel_ReTx_DATA : std_logic := '0';
497 signal AddReTxEntry : std_logic := '0';
498 signal is_ReTx : std_logic := '0';
499 signal ReTxData_re : std_logic := '0';
500 signal WaitReTxData : std_logic := '0';
501 signal EoB : std_logic := '0';
502 signal push : std_logic := '0';
503 signal data2send : std_logic := '0';
504 signal EVENTdata_re_i : std_logic := '0';
505 signal TCP_DATA_LEN : std_logic_vector(15 downto 0) := (others => '0');
506 signal TCP_DATA_chksum : std_logic_vector(15 downto 0) := (others => '0');
507 signal was_IDLE : std_logic := '0';
508 signal ReTx_cnt : std_logic_vector(2 downto 0) := (others => '0');
509 signal DATA_SIZE : std_logic_vector(31 downto 0) := (others => '0');
510 signal ReTxDataLEN_i : std_logic_vector(12 downto 0) := (others => '0');
511 signal data_wc : std_logic_vector(12 downto 0) := (others => '0');
512 signal saved_data_wc : std_logic_vector(10 downto 0) := (others => '0');
513 signal ReTx_ddr_cnt : std_logic_vector(12 downto 0) := (others => '0');
514 signal ReTx_ddr_empty : std_logic := '1';
515 signal ReTx_ddr_full : std_logic := '0';
516 signal ReTxQueue_WEA : std_logic := '0';
517 signal ReTxQueue_WEB : std_logic_vector(3 downto 0) := (others => '0');
518 signal ReTxQueue_DIA : std_logic_vector(31 downto 0) := (others => '0');
519 signal ReTxQueue_DIB : std_logic_vector(31 downto 0) := (others => '0');
520 signal ReTxQueue_DOBp : std_logic_vector(31 downto 0) := (others => '0');
521 signal ReTxQueue_DOB : std_logic_vector(31 downto 0) := (others => '0');
522 signal ReTxQueue_ADDRB : std_logic_vector(9 downto 0) := (others => '0');
523 signal ReTxQueue_wp : std_logic_vector(9 downto 0) := (others => '0');
524 signal ReTxQueue_rp : std_logic_vector(7 downto 0) := (others => '0');
525 signal ReleasePending : std_logic := '1';
526 signal ReTxentry_avl : std_logic := '1';
527 signal ReTxQueue_entry : std_logic_vector(8 downto 0) := (others => '0');
528 signal ReTx_ddr_wq_we : std_logic := '0';
529 signal RETX_ddr_wq_re : std_logic := '0';
530 signal ReTx_ddr_wq_ceReg : std_logic := '0';
531 signal ReTx_ddr_wrqst_i : std_logic := '0';
532 signal ReTx_ddr_rrqst_i : std_logic := '0';
533 signal ReTx_ddr_rrqst_q : std_logic := '0';
534 signal ReTx_ddr_out_vld : std_logic := '0';
535 signal ReTx_ddr_wq_full : std_logic := '0';
536 signal ReTx_ddr_LEN_i : std_logic_vector(4 downto 0) := (others => '0');
537 signal ReTx_ddr_wq_wa : std_logic_vector(4 downto 0) := (others => '0');
538 signal ReTx_ddr_wq_ra : std_logic_vector(4 downto 0) := (others => '0');
539 signal ReTx_ddr_wq_wc : std_logic_vector(5 downto 0) := (others => '0');
540 signal ReTx_ddr_wq_in : std_logic_vector(35 downto 0) := (others => '0');
541 signal ReTx_ddr_out_i : std_logic_vector(35 downto 0) := (others => '0');
542 signal sel_ddr : std_logic := '0';
543 signal ce_ReTxQueue_rp : std_logic := '0';
544 signal update_UNA_Buf : std_logic := '0';
545 signal ec_ReTx_ADDR : std_logic := '0';
546 signal ReTx_CTRL : std_logic_vector(4 downto 0) := (others => '0');
547 signal ReTx_SEQ : std_logic_vector(31 downto 0) := (others => '0');
548 signal DupACK_cnt : std_logic_vector(1 downto 0) := (others => '0');
549 signal RELEASE_type : std_logic_vector(1 downto 0) := (others => '0');
550 signal FastReTx : std_logic := '0';
551 signal FastRecovery : std_logic := '0';
552 signal TO_Recovery : std_logic := '0';
553 signal FastReTxStart : std_logic := '0';
554 signal FastReTxDone : std_logic := '0';
555 signal TO_ReTxDone : std_logic := '0';
556 signal save_ReTx : std_logic := '0';
557 signal save_ReTxTime : std_logic := '0';
558 signal PartialACK : std_logic_vector(1 downto 0) := (others => '0');
559 signal wasSYNRCVD : std_logic := '0';
560 signal NewDataACK : std_logic := '0';
561 signal DupACK : std_logic := '0';
562 signal IsDupACK : std_logic := '0';
563 signal OldData : std_logic := '0';
564 signal sample_RTT : std_logic_vector(2 downto 0) := (others => '0');
565 signal time_sample : std_logic := '0';
566 signal set_ReTx_TO : std_logic := '0';
567 signal set_ReTx_TO_dl : std_logic_vector(1 downto 0) := (others => '0');
568 signal TSclock11_r : std_logic := '0';
569 signal ReTx_TO : std_logic := '0';
570 signal ReTxNXT : std_logic := '0';
571 signal RTTvld : std_logic_vector(2 downto 0) := (others => '0');
572 signal RTO : std_logic_vector(15 downto 0) := (others => '0');
573 signal RTO_timer : std_logic_vector(15 downto 0) := (others => '0');
574 signal RTT : std_logic_vector(15 downto 0) := (others => '0');
575 signal CWND : std_logic_vector(31 downto 0) := (others => '0');
576 signal CWND_LTA : std_logic_vector(31 downto 0) := (others => '0');
577 signal debug_opt : std_logic_vector(135 downto 0) := (others => '0');
578 signal debug_RTO : std_logic_vector(135 downto 0) := (others => '0');
579 signal debug_CC : std_logic_vector(271 downto 0) := (others => '0');
580 signal ARP_rcvd_cntr : std_logic_vector(15 downto 0) := (others => '0');
581 signal ICMP_rcvd_cntr : std_logic_vector(15 downto 0) := (others => '0');
582 signal inc_ARP_sent : std_logic := '0';
583 signal inc_ICMP_sent : std_logic := '0';
584 signal ARP_sent_cntr : std_logic_vector(15 downto 0) := (others => '0');
585 signal ICMP_sent_cntr : std_logic_vector(15 downto 0) := (others => '0');
586 signal ReTxData_wc : std_logic_vector(31 downto 0) := (others => '0');
587 signal en_RxDout_cntr : std_logic_vector(31 downto 0) := (others => '0');
588 signal Tack_cntr : std_logic_vector(31 downto 0) := (others => '0');
589 signal ReTx_DataSeg_cntr : std_logic_vector(31 downto 0) := (others => '0');
590 signal ReTx_DataErr_cntr : std_logic_vector(15 downto 0) := (others => '0');
591 signal FastReTx_cntr : std_logic_vector(31 downto 0) := (others => '0');
592 signal ReTxDataACK_cntr : std_logic_vector(15 downto 0) := (others => '0');
593 signal Save_ReTx_cntr : std_logic_vector(15 downto 0) := (others => '0');
594 signal ReTxNXT_cntr : std_logic_vector(31 downto 0) := (others => '0');
595 signal DataSeg_cntr : std_logic_vector(31 downto 0) := (others => '0');
596 signal bad_chksum_pair : std_logic_vector(31 downto 0) := (others => '0');
597 signal time_cntr : std_logic_vector(16 downto 0) := (others => '0');
598 signal rate_cntr : std_logic_vector(24 downto 0) := (others => '0');
599 signal rate : std_logic_vector(24 downto 0) := (others => '0');
600 signal deadtime_cntr : std_logic_vector(25 downto 0) := (others => '0');
601 signal deadtime : std_logic_vector(15 downto 0) := (others => '0');
602 signal status : array32x32 := (others => (others => '0'));
603 signal statusb : array32x32 := (others => (others => '0'));
604 signal ReTx_FIFO_WrErr : std_logic := '0';
605 signal ReTx_FIFO_WrError : std_logic := '0';
606 signal ReTx_FIFO_RdError : std_logic := '0';
607 signal ReTxDataRqst_i : std_logic_vector(2 downto 0) := (others => '0');
608 signal EMAC_Rx_rdata : std_logic_vector(31 downto 0) := (others => '0');
609 signal SEG_ADDR : std_logic_vector(25 downto 0) := (others => '0');
610 signal EventBufAddr_wa : std_logic_vector(4 downto 0) := (others => '0');
611 signal EventBufAddr_ra : std_logic_vector(4 downto 0) := (others => '0');
612 signal EventBufAddr_dop : std_logic_vector(13 downto 12) := (others => '0');
613 signal EventBufAddr_do : std_logic_vector(13 downto 0) := (others => '0');
614 signal EventBufAddr_ra1SyncRegs : std_logic_vector(2 downto 0) := (others => '0');
615 signal EventBufAddr_ra0SyncRegs : std_logic_vector(2 downto 0) := (others => '0');
616 signal DAQ_header : std_logic := '0';
617 signal bad_ReTx_LEN : std_logic := '0';
618 signal ReTxDataCntr : std_logic_vector(13 downto 0) := (others => '0');
619 signal bad_LEN_pair : std_logic_vector(31 downto 0) := (others => '0');
620 signal bad_ReTx_LENCntr : std_logic_vector(15 downto 0) := (others => '0');
621 signal bad_ReTx_chksumCntr : std_logic_vector(15 downto 0) := (others => '0');
622 signal DupAckCntr : std_logic_vector(31 downto 0) := (others => '0');
623 signal NewAckCntr : std_logic_vector(31 downto 0) := (others => '0');
624 signal UNA_MonBuf_i : std_logic_vector(10 downto 0) := (others => '0');
625 signal KiloByte_toggleSyncRegs : std_logic_vector(3 downto 0) := (others => '0');
626 signal EoB_toggleSyncRegs : std_logic_vector(3 downto 0) := (others => '0');
627 signal Written_MonBuf : std_logic_vector(10 downto 0) := (others => '0');
628 signal ADDR_offset : std_logic_vector(3 downto 0) := (others => '0');
629 signal Written_MonBlock : std_logic_vector(8 downto 0) := (others => '0');
630 signal ddr_wptr : std_logic_vector(18 downto 0) := (others => '0');
631 signal ddr_rptr : std_logic_vector(18 downto 0) := (others => '0');
632 signal entry_in_ddr : std_logic_vector(18 downto 0) := (others => '0');
633 signal CLOSE_flag : std_logic_vector(3 downto 0) := (others => '0');
634 signal rate_pause : std_logic := '0';
635 signal delta_rate : std_logic_vector(7 downto 0) := (others => '0');
636 signal wc : std_logic_vector(21 downto 0) := (others => '0');
637 begin
638 --process(clk2x)
639 --begin
640 -- if(clk2x'event and clk2x = '1')then
641 -- if(FastReTxStart = '1' or FastReTxDone = '1' or (FastRecovery = '1' and (DupACK = '1' or NewDataACK = '1')))then
642 -- cs_out(288) <= '1';
643 -- else
644 -- cs_out(288) <= '0';
645 -- end if;
646 -- if(FastReTx = '1' or ReTx_TO = '1' or ReTxNXT = '1' or ((FastRecovery = '1' or TO_recovery = '1') and NewDataACK = '1'))then
647 -- cs_out(289) <= '1';
648 -- else
649 -- cs_out(289) <= '0';
650 -- end if;
651 -- end if;
652 --end process;
653 --cs_out(272) <= TO_recovery;
654 --cs_out(271) <= OldData;
655 --cs_out(269) <= option_rdy;
656 --cs_out(256) <= FastReTx;
657 --cs_out(255) <= ReTxNXT;
658 --cs_out(254) <= FastReTxDone;
659 --cs_out(253 downto 252) <= DupACK_Cnt;
660 --cs_out(251 downto 220) <= SND_NXT;
661 --cs_out(219 downto 188) <= SND_UNA;
662 --cs_out(187 downto 156) <= SEG_ACK;
663 --cs_out(251 downto 156) <= debug_opt(95 downto 0);
664 --cs_out(155 downto 122) <= debug_opt(129 downto 96);
665 --cs_out(153 downto 122) <= recover;
666 --cs_out(121 downto 0) <= debug_CC(121 downto 0);
667 LINK_down <= '0' when TCPstate = ESTAB else '1';
668 EVENTdata_re <= EVENTdata_re_i;
669 ReTx_ddr_out <= ReTx_ddr_out_i(31 downto 0);
670 ReTx_ddr_wrqst <= ReTx_ddr_wrqst_i;
671 ReTx_ddr_rrqst <= ReTx_ddr_rrqst_i;
672 ReTxDataLEN <= ReTxDataLEN_i;
673 UNA_MonBuf <= UNA_MonBuf_i;
674 UNA_TCPBuf <= (others => '0');
675 ReTxDataRqst <= ReTxDataRqst_i(2);
676 ReTxDataAddr <= ReTxDataAddr_i;
677 ReTx_ddr_LEN <= ReTx_ddr_LEN_i;
678 i_XGbEMAC: XGbEMAC PORT MAP(
679  clk => clk2x,
680  reset => reset,
681  enTxJumboFrame => '1',
682  enRxJumboFrame => '0',
683  EmacPhyTxc => EmacPhyTxc,
684  EmacPhyTxd => EmacPhyTxd,
685  PhyEmacRxc => PhyEmacRxC,
686  PhyEmacRxd => PhyEmacRxD,
687  ClientEmacTxd => ClientEmacTxd,
688  ClientEmacTxdVld => ClientEmacTxdVld,
689  ClientEmacTxUnderrun => '0',
690  EmacClientTack => EmacClientTack ,
691  EmacClientRxd => EmacClientRxd,
692  EmacClientRxdWe => EmacClientRxdWe,
693  EmacClientRxGoodFrame => EmacClientRxGoodFrame,
694  EmacClientRxbadFrame => EmacClientRxbadFrame
695  );
696 i_EMAC_Rx_if: EMAC_Rx_if PORT MAP(
697  clk => clk2x,
698  reset => reset,
699  rstCntr => rstCntr,
700  no_TCP_DATA => '1',
701  EMAC_RxD => EmacClientRxd,
702  EMAC_RxDVLD => EmacClientRxdWe,
703  EMAC_RxGoodFrame => EmacClientRxGoodFrame,
704  EMAC_RxBadFrame => EmacClientRxbadFrame,
705  MY_IP => MY_IP,
706  MY_ETH => MY_ETH,
707  en_Dout => en_RxDout,
708  Dout_avl => RxDout_avl,
709  Dout_type => RxDout_type,
710  Dout => RxDout ,
711  last_word => RxDout_lastword,
712  Dout_valid => RxDout_valid,
713  ipb_addr => ipb_addr,
714  ipb_rdata => EMAC_Rx_rdata,
715  csa => open,
716  csb => open
717  );
718 i_buf_H: SDP32x18 generic map (INIT => INIT_buf_h) PORT MAP(
719  clk => clk2x,
720  we => buf_we (1),
721  DI => buf_di (35 downto 18),
722  WA => buf_wa ,
723  RA => buf_ra ,
724  DO => buf_DO (35 downto 18)
725  );
726 i_buf_L: SDP32x18 generic map (INIT => INIT_buf_l) PORT MAP(
727  clk => clk2x,
728  we => buf_we (0),
729  DI => buf_di (17 downto 0),
730  WA => buf_wa ,
731  RA => buf_ra ,
732  DO => buf_DO (17 downto 0)
733  );
734 buf_di <= '0' & RxDout(34) & RxDout(31 downto 16) & RxDout(33 downto 32) & RxDout(15 downto 0);
735 process(clk2x)
736 begin
737  if(clk2x'event and clk2x = '1')then
738  EventBufAddr_do(13 downto 12) <= EventBufAddr_dop;
739  if(TCPstate = CLOSED or TCPstate = LISTEN)then
740  buf_wa(4) <= '0';
741  else
742  buf_wa(4) <= '1';
743  end if;
744  if(buf_wa(3 downto 0) = x"0")then
745  IPHDR_END <= (others => '1');
746  elsif(buf_wa(3 downto 0) = x"3")then
747  IPHDR_END <= ('0' & RxDout(11 downto 8)) + "00011";
748  end if;
749  if(buf_wa(3 downto 0) = x"3")then
750  IPHDR_LEN <= "0000000000" & RxDout(11 downto 8) & "00";
751  end if;
752  if(buf_wa(3 downto 0) = x"4")then
753  SEG_TCP_LEN <= RxDout(31 downto 16) - IPHDR_LEN;
754  end if;
755  if(buf_wa(3 downto 0) = x"8")then
756  if(RxDout(15 downto 0) = MY_PORT)then
757  NOT_MY_PORT <= '0';
758  else
759  NOT_MY_PORT <= '1';
760  end if;
761  end if;
762  if(buf_wa(3 downto 0) = x"9")then
763  SEG_SEQ(31 downto 16) <= RxDout(15 downto 0);
764  end if;
765  if(buf_wa(3 downto 0) = x"a")then
766  SEG_SEQ(15 downto 0) <= RxDout(31 downto 16);
767  SEG_ACK(31 downto 16) <= RxDout(15 downto 0);
768  end if;
769  if(buf_wa(3 downto 0) = x"b")then
770  SEG_ACK(15 downto 0) <= RxDout(31 downto 16);
771  SEG_TCPHDR_LEN(5 downto 2) <= RxDout(15 downto 12);
772  SEG_CTRL <= RxDout(4 downto 0);
773  SEG_SYNorFIN <= RxDout(bit_SYN) or RxDout(bit_FIN);
774  end if;
775  SEG_LEN <= SEG_TCP_LEN - SEG_TCPHDR_LEN + SEG_SYNorFIN;
776  SEG_LEN_IS_0 <= not or_reduce(SEG_LEN);
777  if(buf_wa(3 downto 0) = x"c")then
778  case SND_WND_SCALE(1 downto 0) is
779  when "01" => SEG_WNDp <= zero(18 downto 17) & RxDout(31 downto 16) & zero(0);
780  when "10" => SEG_WNDp <= zero(18) & RxDout(31 downto 16) & zero(1 downto 0);
781  when "11" => SEG_WNDp <= RxDout(31 downto 16) & zero(2 downto 0);
782  when others => SEG_WNDp <= zero(18 downto 16) & RxDout(31 downto 16);
783  end case;
784  end if;
785  if(OPTION_begin = '1')then
786  case SND_WND_SCALE(3 downto 2) is
787  when "01" => SEG_WND <= zero(31 downto 23) & SEG_WNDp & zero(3 downto 0);
788  when "10" => SEG_WND <= zero(31 downto 27) & SEG_WNDp & zero(7 downto 0);
789  when "11" => SEG_WND <= zero(31) & SEG_WNDp & zero(11 downto 0);
790  when others => SEG_WND <= zero(31 downto 19) & SEG_WNDp;
791  end case;
792  end if;
793  if(buf_wa(3 downto 0) = x"c")then
794  tmp_SEG_WND <= RxDout(31 downto 16);
795  end if;
796  if(TCPstate = LISTEN)then
797  ISS <= TSclock;
798  end if;
799  if(buf_wa(3 downto 0) = x"c" and CONN_MATCH = '1' and NOT_MY_PORT = '0' and TCPstate /= CLOSED and RxDout_valid = '1' and RxDout_type = "00")then -- check options only for valid segment
800  OPTION_begin <= '1';
801  else
802  OPTION_begin <= '0';
803  end if;
804  OPTION_end <= RxDout_lastword;
805  SEG_SEQ_PLUS_ONE <= SEG_SEQ + 1;
806  SEG_SEQ_PLUS_LEN <= SEG_SEQ + (x"0000" & SEG_LEN);
807  RCV_NXT_PLUS_WND <= RCV_NXT + RCV_WND;
808  if(TCPstate = LISTEN or CTRLstate = IDLE)then
809  CONN_MATCH <= '1';
810  elsif((buf_wa(3 downto 0) = x"6" or buf_wa(3 downto 0) = x"7") and RxDout(15 downto 0) /= buf_do(15 downto 0))then
811  CONN_MATCH <= '0';
812  elsif((buf_wa(3 downto 0) = x"7" or buf_wa(3 downto 0) = x"8") and buf_we(1) = '1' and RxDout(31 downto 16) /= buf_do(33 downto 18))then
813  CONN_MATCH <= '0';
814  end if;
815  if(A_GE_B(SEG_SEQ, RCV_NXT) and A_GT_B(RCV_NXT_PLUS_WND, SEG_SEQ))then
816  SEG_SEQ_OR <= '0';
817  else
818  SEG_SEQ_OR <= '1';
819  end if;
820  if(A_GT_B(SEG_SEQ_PLUS_LEN, RCV_NXT) and A_GE_B(RCV_NXT_PLUS_WND, SEG_SEQ_PLUS_LEN))then
821  SEG_SEQ_PLUS_LEN_OR <= '0';
822  else
823  SEG_SEQ_PLUS_LEN_OR <= '1';
824  end if;
825  if(A_GE_B(RCV_NXT, SEG_SEQ))then
826  update_TSrecent <= '1';
827  else
828  update_TSrecent <= '0';
829  end if;
830  if(A_GE_B(RCV_NXT, SEG_SEQ) and A_GT_B(SEG_SEQ_PLUS_LEN, RCV_NXT))then
831  update_RCV_NXT <= '1';
832  else
833  update_RCV_NXT <= '0';
834  end if;
835  if(chk_ReTxQueue(0) = '1' and A_GE_B(SEG_ACK, ReTxQueue_DOB))then
836  ce_ReTxQueue_rp <= '1';
837  else
838  ce_ReTxQueue_rp <= '0';
839  end if;
840  if(SEG_ACK = SND_UNA)then
841  IsDupACK <= '1';
842  else
843  IsDupACK <= '0';
844  end if;
845  update_UNA_Buf <= ce_ReTxQueue_rp;
846  if(IS_CONNECTED = '0')then
847  UNA_MonBuf_i <= (others => '0');
848  elsif(update_UNA_Buf = '1' and ReTxQueue_DOB(31) = '1')then
849  UNA_MonBuf_i <= UNA_MonBuf_i + 1;
850  end if;
851  if(TCPstate = CLOSED or TCPstate = LISTEN or SND_UNA = SND_NXT)then
852  SND_UNACK <= '0';
853  else
854  SND_UNACK <= '1';
855  end if;
856  if(A_GE_B(CWND_LTA, SND_WND))then
857  SND_WND_UL <= SND_WND + SND_UNA - 1;
858  else
859  SND_WND_UL <= CWND_LTA + SND_UNA - 1;
860  end if;
861  SND_SEQ_LAST <= SND_NXT + DATA_SIZE;
862  if(A_GE_B(SND_WND_UL, SND_SEQ_LAST) or SND_UNACK = '0')then
863  SND_SPACE_OK <= '1';
864  else
865  SND_SPACE_OK <= '0';
866  end if;
867  if(A_GE_B(SND_WND_UL_CC, SND_SEQ_LAST) or FastRecovery = '0')then
868  SND_SPACE_CC_OK <= '1';
869  else
870  SND_SPACE_CC_OK <= '0';
871  end if;
872  if(A_GE_B(SEG_ACK, SND_UNA) and A_GE_B(SND_NXT, SEG_ACK))then
873  SEG_ACK_OK <= '1';
874  else
875  SEG_ACK_OK <= '0';
876  end if;
877  if(SAMPLE_RTT(0) = '0' and A_GT_B(SEG_ACK, SND_UNA) and A_GE_B(SND_NXT, SEG_ACK))then
878  UPDATE_SND_UNA <= '1';
879  else
880  UPDATE_SND_UNA <= '0';
881  end if;
882  if(SAMPLE_RTT(0) = '1')then
883  SAMPLE_RTT(1) <= '1';
884  elsif(OPTION_rdy = '1')then
885  SAMPLE_RTT(1) <= '0';
886  end if;
887  if(TS_OPTION = '1')then
888  SAMPLE_RTT(2) <= SAMPLE_RTT(1) and OPTION_rdy;
889  else
890  SAMPLE_RTT(2) <= SAMPLE_RTT(0);
891  end if;
892  if(A_GT_B(SEG_ACK, SND_NXT))then
893  SEG_ACK_GT_SND_NXT <= '1';
894  else
895  SEG_ACK_GT_SND_NXT <= '0';
896  end if;
897  if(A_GT_B(SEG_SEQ, SND_WL1) or (A_GE_B(SEG_SEQ, SND_WL1) and A_GE_B(SEG_ACK, SND_WL2)))then
898  update_SND_WND <= '1';
899  else
900  update_SND_WND <= '0';
901  end if;
902  SND_SYNorFIN <= SND_CTRL(bit_SYN) or SND_CTRL(bit_FIN);
903  end if;
904 end process;
905 process(clk2x)
906 variable diff : std_logic_vector(31 downto 0);
907 begin
908  diff := ReTxQueue_DOB - (x"0000" & ReTx_SEQ(15 downto 0));
909  if(clk2x'event and clk2x = '1')then
910  headerFIFO_full <= headerFIFO_AlmostFull;
911  en_LINK_SyncRegs <= en_LINK_SyncRegs(1 downto 0) & en_LINK;
912  if(IS_CONNECTED = '0' or SendReTxData = '1')then
913  ReTxData_avl <= '0';
914  elsif(ReTxData_we(1) = '1' and DDR2TCPdata(32) = '1')then
915  ReTxData_avl <= '1';
916  end if;
917  if(ReTxDataRqst_i(2) = '1')then
918  ReTxDataCntr <= (others => '0');
919  elsif(ReTxData_we /= "00")then
920  ReTxDataCntr <= ReTxDataCntr + 1;
921  end if;
922  ReTxData_avl_dl <= ReTxData_avl_dl(1 downto 0) & ReTxData_avl;
923  if(ReTxData_avl_dl(2 downto 1) = "01")then
924  if(SavedChksum /= ReTxData_chksum)then
925  bad_ReTx_chksum <= '1';
926  bad_chksum_pair <= SavedChksum & ReTxData_chksum;
927  end if;
928  if(ReTxDataCntr(13 downto 1) /= ReTxDataLEN_i or ReTxDataCntr(0) = '1')then
929  bad_ReTx_LEN <= '1';
930  bad_LEN_pair <= "00" & ReTxDataCntr & "000" & ReTxDataLEN_i;
931  end if;
932  else
933  bad_ReTx_chksum <= '0';
934  bad_ReTx_LEN <= '0';
935  end if;
936  if(TCPstate /= CLOSED and TCPstate /= LISTEN)then
937  TIMEWAITcntr <= (others => '0');
938  elsif(TIMEWAITcntr(waittime) = '0' and strobe_ms = '1')then
939  TIMEWAITcntr <= TIMEWAITcntr + 1;
940  end if;
941  if(en_KEEPALIVE = '0' or TCPstate /= ESTAB or (CTRLstate = SND and buf_ra(4) = '0'))then
942  KEEPALIVEcntr <= (others => '0');
943  elsif(strobe_ms = '1')then
944  KEEPALIVEcntr <= KEEPALIVEcntr + 1;
945  end if;
946  if(CTRLstate = IDLE and ReTxentry_avl = '1' and ReleasePending = '0')then
947  RTTvld(0) <= '1';
948  else
949  RTTvld(0) <= '0';
950  end if;
951  RTTvld(2 downto 1) <= RTTvld(1 downto 0);
952  if(NewDataACK = '1' or SND_UNACK = '0' or save_ReTx = '1')then
953  STD_RTT <= (others => '0');
954  elsif(RTTvld(2) = '1')then
955 -- STD_RTT <= TSclock(27 downto 12) - ReTxQueue_DOB(15 downto 0);
956  STD_RTT <= TSclock(23 downto 8) - ReTxQueue_DOB(15 downto 0);
957  end if;
958 -- TSclock11_r <= TSclock(11);
959  TSclock11_r <= TSclock(7);
960  if(NewDataACK = '1' or SND_UNACK = '0' or set_ReTx_TO_dl(1) = '1')then
961  RTO_timer <= RTO;
962 -- elsif(TSclock(11) = '0' and TSclock11_r = '1')then
963  elsif(TSclock(7) = '0' and TSclock11_r = '1')then
964  RTO_timer <= RTO_timer - 1;
965  end if;
966  if(IS_CONNECTED = '0' or NewDataACK = '1' or save_ReTx = '1' or SND_UNACK = '0')then
967  ReTx_TO <= '0';
968  elsif(set_ReTx_TO = '1')then
969  ReTx_TO <= '1';
970  end if;
971 -- set_ReTx_TO <= not TSclock(11) and TSclock11_r and not or_reduce(RTO_timer);
972  set_ReTx_TO <= not TSclock(7) and TSclock11_r and not or_reduce(RTO_timer);
973  set_ReTx_TO_dl <= set_ReTx_TO_dl(0) & set_ReTx_TO;
974  if(or_reduce(ReTxQueue_entry(8 downto 1)) = '1' or (ReTxQueue_entry(0) = '1' and ce_ReTxQueue_rp = '0'))then
975  ReTxentry_avl <= '1';
976  else
977  ReTxentry_avl <= '0';
978  end if;
979  if(IS_CONNECTED = '0' or NewDataACK = '1')then
980  ReTx_cnt <= (others => '0');
981  elsif(save_ReTx = '1' and ReTxNXT = '0')then
982  ReTx_cnt <= ReTx_cnt + 1;
983  end if;
984  ReTxDataLastAddr <= ReTxDataAddr_i(15 downto 0) + ("000" & ReTxDataLEN_i);
985  if(IS_CONNECTED = '0' or ReTxDataACK = '1')then -- reset request once acknowledged
986  ReTxDataRqst_i <= "000";
987  else
988  if(ec_ReTx_ADDR = '1' and ReTxQueue_DOB(27 downto 26) = "00")then -- SYN and FIN has no data, save the request for later processing
989  ReTxDataRqst_i(0) <= '1';
990  end if;
991  ReTxDataRqst_i(1) <= ReTxDataRqst_i(0);
992 -- check that the data to be retransmitted must be in the memory. Written_MonBuf(10 downto 9) = "11" means negative counts. If at least one event not acknowleged is in the
993 -- memory, or number of blocks in the memory is more than the one to be retransmitted
994  if(ReTxDataRqst_i(1) = '1' and Written_MonBuf(10 downto 9) /= "11" and (or_reduce(Written_MonBuf) = '1' or ReTxDataLastAddr(15 downto 7) < Written_MonBlock))then
995  ReTxDataRqst_i(2) <= '1';
996  end if;
997  end if;
998  if(TCPstate = SYNRCVD or TCPstate = ESTAB)then
999  IS_CONNECTED <= '1';
1000  else
1001  IS_CONNECTED <= '0';
1002  end if;
1003  if(TCPstate = LISTEN)then
1004  LISTENing <= '1';
1005  else
1006  LISTENing <= '0';
1007  end if;
1008  if(TCPstate = CLOSED)then
1009  IS_CLOSED <= '1';
1010  else
1011  IS_CLOSED <= '0';
1012  end if;
1013  case DupACK_Cnt is
1014  when "01" => CWND_LTA <= CWND + MSS;-- Limited Transmission Algorithm
1015  when "10" => CWND_LTA <= CWND + ('0' & MSS(31 downto 1));-- Limited Transmission Algorithm
1016  when others => CWND_LTA <= CWND;
1017  end case;
1018  if(TCPstate = SYNRCVD)then
1019  wasSYNRCVD <= '1';
1020  else
1021  wasSYNRCVD <= '0';
1022  end if;
1023  if(CTRLstate /= SND)then
1024  rdy2send <= '0';
1025  elsif(OPTION_rdy = '1' and (ReTx_ddr_wq_full = '0' or SendReTxData = '1'))then
1026  rdy2send <= '1';
1027  end if;
1028  if(IS_CONNECTED = '0' or (NewDataACK = '1' and PartialACK(1) = '0') or FastReTx = '1')then
1029  TO_Recovery <= '0';
1030  elsif(TO_ReTxDone = '1')then
1031  TO_Recovery <= '1';
1032  end if;
1033  if(IS_CONNECTED = '0' or (NewDataACK = '1' and PartialACK(0) = '0') or ReTx_TO = '1')then
1034  FastRecovery <= '0';
1035  elsif(DupACK_Cnt(1) = '1' and DupACK = '1' and A_GT_B(SEG_ACK, recover))then
1036  FastRecovery <= '1';
1037  end if;
1038  if(IS_CONNECTED = '0' or save_ReTx = '1' or SND_UNACK = '0')then
1039  ReTxNXT <= '0';
1040  elsif(((FastRecovery = '1' and PartialACK(0) = '1') or (TO_Recovery = '1' and PartialACK(1) = '1')) and NewDataACK = '1')then
1041  ReTxNXT <= '1';
1042  end if;
1043  if(IS_CONNECTED = '0' or NewDataACK = '1' or save_ReTx = '1' or SND_UNACK = '0')then
1044  FastReTx <= '0';
1045  elsif((DupACK_Cnt(1) = '1' and DupACK = '1' and A_GT_B(SEG_ACK, recover)) or ((FastRecovery = '1' or TO_Recovery = '1') and DupACK = '1' and TS_OPTION = '1' and OldData = '0'))then
1046  FastReTx <= '1';
1047  end if;
1048  if(DupACK_Cnt(1) = '1' and DupACK = '1' and A_GT_B(SEG_ACK, recover))then
1049  FastReTxStart <= '1';
1050  else
1051  FastReTxStart <= '0';
1052  end if;
1053  if(save_ReTx = '1')then
1054  FastReTxData <= FastReTx;
1055  TO_ReTxData <= ReTx_TO;
1056  end if;
1057  if(headerFIFO_DI(35 downto 34) = "11" and headerFIFO_WREN = '1' and SendReTxData = '1' and FastReTxData = '1')then
1058  FastReTxDone <= '1';
1059  else
1060  FastReTxDone <= '0';
1061  end if;
1062  if(headerFIFO_DI(35 downto 34) = "11" and headerFIFO_WREN = '1' and SendReTxData = '1' and TO_ReTxData = '1')then
1063  TO_ReTxDone <= '1';
1064  else
1065  TO_ReTxDone <= '0';
1066  end if;
1067  if(TO_ReTxDone = '1')then
1068  TO_recover <= SND_NXT;
1069  end if;
1070  if(FastReTxDone = '1')then
1071  recover <= SND_NXT;
1072  elsif(FastRecovery = '0')then
1073  recover <= SND_UNA - 1;
1074  end if;
1075  if(A_GE_B(SEG_ACK, recover))then
1076  PartialACK(0) <= '0';
1077  else
1078  PartialACK(0) <= '1';
1079  end if;
1080  if(A_GE_B(SEG_ACK, TO_recover))then
1081  PartialACK(1) <= '0';
1082  else
1083  PartialACK(1) <= '1';
1084  end if;
1085  if(IS_CONNECTED = '0' or SND_UNACK = '0' or NewDataACK = '1' or FastRecovery = '1' or TO_Recovery = '1')then
1086  DupACK_cnt <= (others => '0');
1087  elsif(DupACK = '1')then
1088  DupACK_cnt <= DupACK_cnt + 1;
1089  end if;
1090  if(FIFO_en = '0')then
1091  CTRLstate <= IDLE;
1092  DupACK <= '0';
1093  en_RxDout <= '0';
1094  TCPstate <= CLOSED;
1095  CLOSE_flag <= "0000";
1096  inc_ARP_sent <= '0';
1097  inc_ICMP_sent <= '0';
1098  ReleasePending <= '0';
1099  else
1100  case CTRLstate is
1101  when IDLE =>
1102  NewDataACK <= '0';
1103  sample_RTT(0) <= '0';
1104  SendReTxData <= '0';
1105  DupACK <= '0';
1106  en_RxDout <= '0';
1107  TCPheader_we <= '0';
1108  buf_we <= "00";
1109  IS_ARP_ICMP <= '0';
1110  save_ReTx <= '0';
1111  AddReTxEntry <= '0';
1112  chk_ReTxQueue <= "00";
1113  CTRLcntr <= (others => '0');
1114  buf_wa(3 downto 0) <= (others => '0');
1115  buf_ra <= (others => '0');
1116  AttachData <= '0';
1117  ReTxQueue_ADDRB(1 downto 0) <= "00";
1118  if(en_RxDout = '1')then
1119  if(RxDout_type = "00")then
1120  CTRLstate <= RCV_IPHDR;
1121  buf_ra(0) <= '1';
1122  else
1123  IS_ARP_ICMP <= '1';
1124  CTRLstate <= SND_ARP_ICMP;
1125  buf_ra(4) <= buf_wa(4);
1126  end if;
1127  if(RxDout_type /= "10")then -- RxDout_type = "10" is ARP reply, this server does not send ARP request
1128  inc_ARP_sent <= RxDout_type(1) and RxDout_type(0);
1129  inc_ICMP_sent <= RxDout_type(0) and not RxDout_type(1);
1130  buf_we <= "11";
1131  end if;
1132  elsif((en_LINK_SyncRegs(2) = '0' and TCPstate /= CLOSED) or (ReTx_cnt(2) = '1' and (FastReTx = '1' or ReTx_TO = '1')))then
1133  TCPstate <= CLOSED;
1134  CLOSE_flag <= "0001";
1135  if(TCPstate = ESTAB)then
1136  SND_SEQ <= SND_NXT;
1137  SND_CTRL <= "000100";--RST
1138  CTRLstate <= SND;
1139  end if;
1140  elsif(en_LINK_SyncRegs(2) = '1' and TCPstate = CLOSED and (simulation or TIMEWAITcntr(waittime) = '1'))then
1141  WaitReTxData <= '0';
1142  TCPstate <= LISTEN;
1143  ReleasePending <= '0';
1144  elsif((FastReTx = '1' or ReTx_TO = '1' or ReTxNXT = '1') and WaitReTxData = '0' and ReTx_FIFO_empty = '1' and headerFIFO_full = '0' and ReleasePending = '0')then
1145  CTRLstate <= RETX;
1146  elsif(RxDout_avl = '1' and headerFIFO_full = '0')then
1147  en_RxDout <= '1';
1148  elsif(TCPstate = ESTAB)then
1149  if(ReTxData_avl = '1')then
1150  SendReTxData <= '1';
1151  WaitReTxData <= '0';
1152  AttachData <= '1';
1153  SND_CTRL(4 downto 0) <= ReTx_CTRL;
1154  SND_SEQ <= ReTx_SEQ;
1155  SND_ACK <= RCV_NXT;
1156  CTRLstate <= SND;
1157  elsif((ReTx_ddr_wq_full = '0' and headerFIFO_full = '0' and Data2Send = '1' and SND_SPACE_OK = '1' and SND_SPACE_CC_OK = '1' and EnNewData = '1') or KEEPALIVEcntr(15) = '1')then
1158  SND_SEQ <= SND_NXT;
1159  AttachData <= Data2Send;
1160  if(Data2Send = '1' and EoB = '1')then
1161  SND_CTRL <= EoB & '1' & push & "000";--ACK and PUSH
1162  else
1163  SND_CTRL <= "010000";--ACK
1164  end if;
1165  SND_ACK <= RCV_NXT;
1166  AddReTxEntry <= Data2Send;
1167  CTRLstate <= SND;
1168  elsif(ReleasePending = '1' and ReTxentry_avl = '1')then
1169  CTRLstate <= RELEASE;
1170  end if;
1171  end if;
1172  when RETX =>
1173  ReTxQueue_ADDRB(0) <= not ReTxQueue_ADDRB(0);
1174  ReTxQueue_ADDRB(1) <= ReTxQueue_ADDRB(1) xor ReTxQueue_ADDRB(0);
1175  if(ReTxQueue_ADDRB(1 downto 0) = "10")then
1176  ReTx_SEQ(15 downto 0) <= ReTxQueue_DOB(31 downto 16);
1177  end if;
1178  if(ReTxQueue_ADDRB(1 downto 0) = "11")then
1179  ReTx_SEQ(31 downto 16) <= diff(31 downto 16);
1180  ReTxDataLEN_i <= diff(15 downto 3);
1181  save_ReTx <= '1';
1182  else
1183  save_ReTx <= '0';
1184  end if;
1185  if(save_ReTx = '1')then
1186  SavedChksum <= ReTxQueue_DOB(31 downto 16);
1187  ReTxIP_ID <= ReTxQueue_DOB(15 downto 0);
1188  end if;
1189  ec_ReTx_ADDR <= save_ReTx;
1190  if(ec_ReTx_ADDR = '1')then
1191  ReTx_CTRL <= ReTxQueue_DOB(30 downto 26);
1192  ReTxDataAddr_i <= ReTxQueue_DOB(25 downto 0);
1193  if(ReTxQueue_DOB(27 downto 26) = "00")then
1194  CTRLstate <= IDLE;
1195  WaitReTxData <= '1';
1196  else
1197  SND_CTRL(4 downto 0) <= ReTxQueue_DOB(30 downto 26);
1198  SND_SEQ <= ReTx_SEQ;
1199  SND_ACK <= RCV_NXT;
1200  CTRLstate <= SND;
1201  end if;
1202  end if;
1203  when RELEASE =>
1204  if(ReTxQueue_ADDRB(1 downto 0) = "10")then
1205  if(ReTxentry_avl = '0')then
1206  CTRLstate <= IDLE;
1207  else
1208  chk_ReTxQueue(0) <= '1';
1209  end if;
1210  else
1211  chk_ReTxQueue(0) <= '0';
1212  end if;
1213 -- if(chk_ReTxQueue(0) = '1' and SEG_ACK = ReTxQueue_DOB)then
1214  if(chk_ReTxQueue(0) = '1' and A_GE_B(ReTxQueue_DOB, SEG_ACK))then
1215  ReleasePending <= '0';
1216  end if;
1217  chk_ReTxQueue(1) <= chk_ReTxQueue(0);
1218  ReTxQueue_ADDRB(0) <= not ReTxQueue_ADDRB(0);
1219  ReTxQueue_ADDRB(1) <= ReTxQueue_ADDRB(1) xor ReTxQueue_ADDRB(0);
1220  if(chk_ReTxQueue(1) = '1' and ReleasePending = '0')then
1221  CTRLstate <= IDLE;
1222  end if;
1223  when SND_ARP_ICMP =>
1224  inc_ARP_sent <= '0';
1225  inc_ICMP_sent <= '0';
1226  if(RxDout_valid = '0')then
1227  CTRLstate <= IDLE;
1228  buf_we <= "00";
1229  end if;
1230  when RCV_IPHDR =>
1231  if(CTRLcntr = IPHDR_END)then
1232  buf_we <= "10";
1233  else
1234  case buf_wa(3 downto 0) is
1235  when x"2" | x"3" | x"4" => buf_we <= "00";
1236  when x"5" | x"8" => buf_we <= "01";
1237  when others => buf_we <= "11";
1238  end case;
1239  end if;
1240  CTRLcntr <= CTRLcntr + 1;
1241  if(buf_wa(3) = '0' or CTRLcntr = IPHDR_END)then
1242  buf_wa(3 downto 0) <= buf_wa(3 downto 0) + 1;
1243  buf_ra(3 downto 0) <= buf_ra(3 downto 0) + 1;
1244  end if;
1245  if(CTRLcntr = IPHDR_END)then
1246  CTRLstate <= RCV_TCPHDR;
1247  end if;
1248  when RCV_TCPHDR =>
1249  buf_we <= "00";
1250  if(buf_wa(3 downto 0) /= x"d")then
1251  buf_wa(3 downto 0) <= buf_wa(3 downto 0) + 1;
1252  buf_ra(3 downto 0) <= buf_ra(3 downto 0) + 1;
1253  end if;
1254  if(RxDout_valid = '0')then
1255  CTRLstate <= RCV_PROCESS;
1256  end if;
1257  CTRLcntr <= (others => '0');
1258  when RCV_PROCESS =>
1259  ReTxQueue_ADDRB(1 downto 0) <= "00";
1260  if(NOT_MY_PORT = '1' or CONN_MATCH = '0')then
1261  buf_ra(4) <= buf_wa(4);
1262  end if;
1263  if(TCPstate = CLOSED or NOT_MY_PORT = '1' or CONN_MATCH = '0')then
1264  if(SEG_CTRL(bit_RST) = '1')then
1265  CTRLstate <= IDLE;
1266  else
1267  if(SEG_CTRL(bit_ACK) = '0')then
1268  SND_SEQ <= (others => '0');
1269  SND_ACK <= SEG_SEQ_PLUS_LEN;
1270  SND_CTRL <= "010100";--ACK,RST
1271  else
1272  SND_SEQ <= SEG_ACK;
1273  SND_CTRL <= "000100";--RST
1274  end if;
1275  CTRLstate <= SND;
1276  end if;
1277  elsif(TCPstate = LISTEN)then
1278  if(SEG_CTRL(bit_RST) = '1')then
1279  CTRLstate <= IDLE;
1280  elsif(SEG_CTRL(bit_ACK) = '1')then
1281  SND_SEQ <= SEG_ACK;
1282  SND_CTRL <= "000100";--RST
1283  CTRLstate <= SND;
1284  elsif(SEG_CTRL(bit_SYN) = '1')then
1285  RCV_NXT <= SEG_SEQ_PLUS_LEN;-- if any data attached, they are discarded
1286  SND_WND <= SEG_WND;
1287  input_SEG_WND0 <= tmp_SEG_WND;
1288  IRS <= SEG_SEQ;
1289  SND_UNA <= ISS;
1290  SND_SEQ <= ISS;
1291  SND_ACK <= SEG_SEQ_PLUS_ONE;
1292  SND_CTRL <= "010010";--ACK,SYN
1293  AddReTxEntry <= '1';
1294  CTRLstate <= SND;
1295  if(SEG_CTRL(bit_FIN) = '1')then -- This is part of the processing in TCPstate SYNRCVD
1296  TCPstate <= CLOSED;
1297  else
1298  TCPstate <= SYNRCVD;
1299  end if;
1300  else
1301  SND_SEQ <= (others => '0');
1302  SND_ACK <= SEG_SEQ_PLUS_LEN;
1303  SND_CTRL <= "010100";--ACK,RST
1304  CTRLstate <= SND;
1305  end if;
1306  elsif(SEG_SEQ_OR = '1' and SEG_SEQ_PLUS_LEN_OR = '1')then
1307  if(SEG_CTRL(bit_RST) = '1')then
1308  CTRLstate <= IDLE;
1309  else
1310  SND_SEQ <= SND_NXT;
1311  SND_ACK <= RCV_NXT;
1312  SND_CTRL <= "010000";--ACK
1313  CTRLstate <= SND;
1314  end if;
1315  elsif(SEG_CTRL(bit_RST) = '1')then
1316  if(TCPstate = SYNRCVD)then
1317  TCPstate <= LISTEN;
1318  CTRLstate <= IDLE;
1319  else
1320  TCPstate <= CLOSED;
1321  CLOSE_flag <= "0010";
1322  CTRLstate <= IDLE;
1323  end if;
1324  elsif(SEG_CTRL(bit_SYN) = '1' and SEG_SEQ_OR = '0')then
1325  TCPstate <= CLOSED;
1326  CLOSE_flag <= "0100";
1327  if(SEG_CTRL(bit_ACK) = '1')then
1328  SND_SEQ <= SND_NXT;
1329  SND_ACK <= SEG_SEQ_PLUS_LEN;
1330  SND_CTRL <= "010100";--ACK,RST
1331  else
1332  SND_SEQ <= SEG_ACK;
1333  SND_CTRL <= "000100";--RST
1334  end if;
1335  CTRLstate <= SND;
1336  elsif(SEG_CTRL(bit_ACK) = '0')then
1337  CTRLstate <= IDLE;
1338  elsif(OPTION_rdy = '1')then
1339  if(TCPstate = SYNRCVD)then
1340  if(SEG_ACK_OK = '1')then
1341  TCPstate <= ESTAB;
1342  SND_WND <= SEG_WND; -- stay in RCV_PROCESS state and continue process in TCPstate ESTAB
1343  SND_WL1 <= SEG_SEQ;
1344  SND_WL2 <= SEG_ACK;
1345  input_SEG_WND1 <= tmp_SEG_WND;
1346  else
1347  SND_SEQ <= SEG_ACK;
1348  SND_CTRL <= "000100";--RST
1349  CTRLstate <= SND;
1350  end if;
1351  end if;
1352  if(TCPstate = ESTAB)then
1353  if(UPDATE_SND_UNA = '1')then
1354  ReleasePending <= '1';
1355  sample_RTT(0) <= '1';
1356  SND_UNA <= SEG_ACK;
1357  NewDataACK <= not wasSYNRCVD;
1358  if(update_SND_WND = '1')then
1359  SND_WND <= SEG_WND;
1360  SND_WL1 <= SEG_SEQ;
1361  SND_WL2 <= SEG_ACK;
1362  input_SEG_WND2 <= tmp_SEG_WND;
1363  end if;
1364  CTRLstate <= IDLE;
1365  elsif(SEG_ACK_GT_SND_NXT = '1')then
1366  SND_SEQ <= SND_NXT;
1367  SND_ACK <= RCV_NXT;
1368  SND_CTRL <= "010000";--ACK
1369  CTRLstate <= SND;
1370  else
1371  DupACK <= IsDupACK;
1372  if(SEG_CTRL(bit_FIN) = '0')then
1373  if(SEG_LEN_IS_0 = '1')then
1374  CTRLstate <= IDLE;
1375  else
1376  if(update_RCV_NXT = '1')then
1377  RCV_NXT <= SEG_SEQ_PLUS_LEN;
1378  SND_ACK <= SEG_SEQ_PLUS_LEN;
1379  else
1380  SND_ACK <= RCV_NXT;-- just discard the segment
1381  end if;
1382  SND_SEQ <= SND_NXT;
1383  SND_CTRL <= "010000";--ACK
1384  CTRLstate <= SND;
1385  end if;
1386  end if;
1387  end if;
1388  end if;
1389  if(TCPstate = LASTACK and SEG_ACK_OK = '1')then
1390  TCPstate <= CLOSED;
1391  CLOSE_flag <= "1000";
1392  CTRLstate <= IDLE;
1393  end if;
1394  if(SEG_CTRL(bit_FIN) = '1')then
1395  if(TCPstate = CLOSED or TCPstate = LISTEN)then
1396  CTRLstate <= IDLE;
1397  else
1398  RCV_NXT <= SEG_SEQ_PLUS_LEN;
1399  SND_SEQ <= SND_NXT;
1400  SND_ACK <= SEG_SEQ_PLUS_LEN;
1401  SND_CTRL <= "010000";--ACK
1402  if(TCPstate = SYNRCVD or TCPstate = ESTAB)then
1403  SND_CTRL <= "010001";--ACK, FIN
1404  TCPstate <= LASTACK;
1405  AddReTxEntry <= '1';
1406  end if;
1407  CTRLstate <= SND;
1408  end if;
1409  end if;
1410  end if;
1411  buf_ra(3 downto 0) <= (others => '0');
1412  when SND =>
1413  DupACK <= '0';
1414  if(AddReTxEntry = '1')then
1415  SND_NXT <= SND_SEQ + DATA_LEN + SND_SYNorFIN;
1416  end if;
1417  if(CTRLcntr(2 downto 0) = "111")then
1418  AddReTxEntry <= '0';
1419  end if;
1420  if(rdy2send = '1')then
1421  if(AddReTxEntry = '1' and CTRLcntr(2) = '1')then
1422  case CTRLcntr(1 downto 0) is
1423  when "00" =>
1424 -- ReTx_ddr_wq_in(31 downto 0) <= SND_SEQ(15 downto 0) & TSclock(27 downto 12);
1425  ReTx_ddr_wq_in(31 downto 0) <= SND_SEQ(15 downto 0) & TSclock(23 downto 8);
1426  ReTX_ddr_wq_we <= '1';
1427  when "01" =>
1428  ReTx_ddr_wq_in(31 downto 0) <= SND_NXT;
1429  when "10" =>
1430  ReTx_ddr_wq_in(31 downto 0) <= DATA_chksum & IP_ID;
1431  when others =>
1432  ReTx_ddr_wq_in(31 downto 0) <= SND_CTRL & SEG_ADDR;
1433  end case;
1434  else
1435  ReTX_ddr_wq_we <= '0';
1436  end if;
1437  buf_ra(3 downto 0) <= buf_ra(3 downto 0) + 1;
1438  CTRLcntr <= CTRLcntr + 1;
1439  if(CTRLcntr = TCPHDR_end)then
1440  if(AttachData = '0')then
1441  CTRLstate <= IDLE;
1442  else
1443  CTRLstate <= WAIT4SND2END;
1444  end if;
1445  TCPheader_we <= '0';
1446  else
1447  TCPheader_we <= '1';
1448  end if;
1449  end if;
1450  when WAIT4SND2END =>
1451  if(headerFIFO_DI(35 downto 34) = "11" and headerFIFO_WREN = '1')then
1452  CTRLstate <= IDLE;
1453  end if;
1454  when others => CTRLstate <= IDLE;
1455  end case;
1456  end if;
1457  end if;
1458 end process;
1459 process(clk2x)
1460 begin
1461  if(clk2x'event and clk2x = '1')then
1462  if(reset = '1')then
1463  FIFO_en <= '0';
1464  elsif(FIFO_rst = '0' and reset_dl = '1')then
1465  FIFO_en <= '1';
1466  end if;
1467  end if;
1468 end process;
1469 i_FIFO_rst : SRL16E
1470  generic map (
1471  INIT => X"0000")
1472  port map (
1473  Q => FIFO_rst, -- SRL data output
1474  A0 => '1', -- Select[0] input
1475  A1 => '1', -- Select[1] input
1476  A2 => '1', -- Select[2] input
1477  A3 => '0', -- Select[3] input
1478  CE => '1', -- Clock enable input
1479  CLK => clk2x, -- Clock input
1480  D => reset -- SRL data input
1481  );
1482 i_reset_dl1 : SRL16E
1483  generic map (
1484  INIT => X"0000")
1485  port map (
1486  Q => reset_dl, -- SRL data output
1487  A0 => '1', -- Select[0] input
1488  A1 => '1', -- Select[1] input
1489  A2 => '1', -- Select[2] input
1490  A3 => '0', -- Select[3] input
1491  CE => '1', -- Clock enable input
1492  CLK => clk2x, -- Clock input
1493  D => FIFO_rst -- SRL data input
1494  );
1495 i_headerFIFO : FIFO_DUALCLOCK_MACRO
1496  generic map (
1497  DEVICE => "7SERIES", -- Target Device: "VIRTEX5", "VIRTEX6", "7SERIES"
1498  ALMOST_FULL_OFFSET => X"0180", -- Sets almost full threshold
1499  ALMOST_EMPTY_OFFSET => X"0080", -- Sets the almost empty threshold
1500  DATA_WIDTH => 36, -- Valid values are 1-72 (37-72 only valid when FIFO_SIZE="36Kb")
1501  FIFO_SIZE => "18Kb", -- Target BRAM, "18Kb" or "36Kb"
1502  FIRST_WORD_FALL_THROUGH => TRUE) -- Sets the FIFO FWFT to TRUE or FALSE
1503  port map (
1504  ALMOSTEMPTY => open, -- 1-bit output almost empty
1505  ALMOSTFULL => headerFIFO_AlmostFull, -- 1-bit output almost full
1506  DO => headerFIFO_DO, -- Output data, width defined by DATA_WIDTH parameter
1507  EMPTY => headerFIFO_EMPTY, -- 1-bit output empty
1508  FULL => open, -- 1-bit output full
1509  RDCOUNT => headerFIFO_RDCOUNT, -- Output read count, width determined by FIFO depth
1510  RDERR => open, -- 1-bit output read error
1511  WRCOUNT => headerFIFO_WRCOUNT, -- Output write count, width determined by FIFO depth
1512  WRERR => open, -- 1-bit output write error
1513  DI => headerFIFO_DI, -- Input data, width defined by DATA_WIDTH parameter
1514  RDCLK => clk2x, -- 1-bit input read clock
1515  RDEN => headerFIFO_RDEN, -- 1-bit input read enable
1516  RST => FIFO_rst, -- 1-bit input reset
1517  WRCLK => clk2x, -- 1-bit input write clock
1518  WREN => headerFIFO_WREN -- 1-bit input write enable
1519  );
1520 headerFIFO_RDEN <= fifo_en and not ClientEmacTxd_sel(1) and ((not rate_pause and not headerFIFO_EMPTY and not ClientEmacTxdVld(3)) or EmacClientTack or rd_headerFIFO);
1521 i_ReTx_FIFO : FIFO65x8k PORT MAP(
1522  clk => clk2x,
1523  fifo_rst => FIFO_rst,
1524  fifo_en => fifo_en,
1525  di => DDR2TCPdata,
1526  we => ReTxData_we,
1527  re => ReTxData_re,
1528  empty => ReTx_FIFO_empty,
1529  FIFO_WrErr => ReTx_FIFO_WrErr,
1530  do => ReTxData
1531  );
1532 g_SND_DATA_dl: for i in 0 to 33 generate
1533  i_SND_DATA_dl : SRL16E
1534  port map (
1535  Q => SND_DATA_dl(i), -- SRL data output
1536  A0 => '1', -- Select[0] input
1537  A1 => '1', -- Select[1] input
1538  A2 => '1', -- Select[2] input
1539  A3 => '0', -- Select[3] input
1540  CE => '1', -- Clock enable input
1541  CLK => clk2x, -- Clock input
1542  D => SND_DATA(i) -- SRL data input
1543  );
1544 end generate;
1545 i_sel_IPHDR_chksum : SRL16E
1546  port map (
1547  Q => sel_IPHDR_chksum, -- SRL data output
1548  A0 => '1', -- Select[0] input
1549  A1 => '1', -- Select[1] input
1550  A2 => '1', -- Select[2] input
1551  A3 => '0', -- Select[3] input
1552  CE => '1', -- Clock enable input
1553  CLK => clk2x, -- Clock input
1554  D => is_IPHDR_chksum -- SRL data input
1555  );
1556 i_sel_TCP_chksum : SRL16E
1557  port map (
1558  Q => sel_TCP_chksum , -- SRL data output
1559  A0 => '1', -- Select[0] input
1560  A1 => '1', -- Select[1] input
1561  A2 => '1', -- Select[2] input
1562  A3 => '0', -- Select[3] input
1563  CE => '1', -- Clock enable input
1564  CLK => clk2x, -- Clock input
1565  D => is_TCP_chksum -- SRL data input
1566  );
1567 i_headerFIFO_WREN : SRL16E
1568  port map (
1569  Q => headerFIFO_WREN, -- SRL data output
1570  A0 => '0', -- Select[0] input
1571  A1 => '0', -- Select[1] input
1572  A2 => '0', -- Select[2] input
1573  A3 => '1', -- Select[3] input
1574  CE => '1', -- Clock enable input
1575  CLK => clk2x, -- Clock input
1576  D => SND_DATA_vld -- SRL data input
1577  );
1578 i_headerFIFO_DI34 : SRL16E
1579  port map (
1580  Q => SND_DATA_end_dl, -- SRL data output
1581  A0 => '1', -- Select[0] input
1582  A1 => '0', -- Select[1] input
1583  A2 => '1', -- Select[2] input
1584  A3 => '0', -- Select[3] input
1585  CE => '1', -- Clock enable input
1586  CLK => clk2x, -- Clock input
1587  D => SND_DATA_end -- SRL data input
1588  );
1589 i_headerFIFO_DI35 : SRL16E
1590  port map (
1591  Q => AttachData_dl, -- SRL data output
1592  A0 => '1', -- Select[0] input
1593  A1 => '1', -- Select[1] input
1594  A2 => '1', -- Select[2] input
1595  A3 => '0', -- Select[3] input
1596  CE => '1', -- Clock enable input
1597  CLK => clk2x, -- Clock input
1598  D => AttachData -- SRL data input
1599  );
1600 i_IPHDR_checksum: checksum PORT MAP(
1601  c => clk2x,
1602  r => rst_chksum,
1603  r_value => x"ffff",
1604  ce => ce_IPHDR_chksum,
1605  d => chksum_in,
1606  bad_chksum => open,
1607  s => IPHDR_chksum
1608  );
1609 i_TCP_checksum: checksum PORT MAP(
1610  c => clk2x,
1611  r => rst_chksum,
1612  r_value => TCP_LEN,
1613  ce => ce_TCP_chksum,
1614  d => chksum_in,
1615  bad_chksum => open,
1616  s => TCP_chksum
1617  );
1618 -- headerFIFO input control
1619 process(clk2x)
1620 begin
1621  if(clk2x'event and clk2x = '1')then
1622  headerFIFO_DI(34) <= SND_DATA_end_dl;
1623  if(SND_DATA_end_dl = '1')then
1624  headerFIFO_DI(35) <= AttachData_dl;
1625  else
1626  headerFIFO_DI(35) <= SendReTxData;
1627  end if;
1628  save_ReTxTime <= SendReTxData and SND_DATA_end_dl;
1629  RxDout_valid_dl <= RxDout_valid_dl(0) & RxDout_valid;
1630  if(IS_ARP_ICMP = '1')then
1631  SND_DATA_vld <= RxDout_valid_dl(1);
1632  SND_DATA_end <= SND_DATA_vld and not RxDout_valid_dl(1);
1633  SND_DATA(33 downto 32) <= buf_DO(17 downto 16);
1634  else
1635  SND_DATA_vld <= TCPheader_we;
1636  SND_DATA_end <= SND_DATA_vld and not TCPheader_we;
1637  SND_DATA(33 downto 32) <= "00";
1638  end if;
1639  if(SendReTxData = '1')then
1640  TCP_DATA_LEN <= ReTxDataLEN_i & "000";
1641  TCP_DATA_chksum <= ReTxData_chksum;
1642  IP_ID2Send <= ReTxIP_ID;
1643  else
1644  TCP_DATA_LEN <= DATA_LEN(15 downto 0);
1645  TCP_DATA_chksum <= DATA_chksum;
1646  IP_ID2Send <= IP_ID;
1647  end if;
1648  if(reset = '1')then
1649  IP_ID <= (others => '0');
1650  elsif(CTRLcntr(2 downto 0) = "100" and AddReTxEntry = '1')then
1651  IP_ID <= IP_ID + 1;
1652  end if;
1653  TCP_LEN <= (DATA_OFFSET & "00") + TCP_DATA_LEN;
1654  HDR_LEN <= ("0000000000" & DATA_OFFSET) + "00000000000101";
1655  TOTAL_LEN <= (TCP_DATA_LEN(15 downto 2) + HDR_LEN) & "00";
1656  if(CTRLcntr(3) = '0')then
1657  MUX_TCPHDR <= TOTAL_LEN & IP_ID2Send;
1658  else
1659  case CTRLcntr(1 downto 0) is
1660  when "10" => MUX_TCPHDR <= SND_SEQ(15 downto 0) & SND_ACK(31 downto 16);
1661  when "11" => MUX_TCPHDR <= SND_ACK(15 downto 0) & DATA_OFFSET & "0000000" & SND_CTRL(4 downto 0);
1662  when others => MUX_TCPHDR <= RCV_WND(15 downto 0) & TCP_DATA_chksum;
1663  end case;
1664  end if;
1665  case CTRLcntr is
1666  when "00000" | "00001" | "00010" | "00011" | "00101" | "00110" | "00111" | "01000" => sel_SND_DATA <= "00";
1667  when "01001" => sel_SND_DATA <= "01";
1668  when "00100" | "01010" | "01011" | "01100" => sel_SND_DATA <= "10";
1669  when others => sel_SND_DATA <= "11";
1670  end case;
1671  case sel_SND_DATA is
1672  when "00" => SND_DATA(31 downto 0) <= buf_DO(33 downto 18) & buf_DO(15 downto 0);
1673  when "01" => SND_DATA(31 downto 0) <= buf_DO(33 downto 18) & SND_SEQ(31 downto 16);
1674  when "10" => SND_DATA(31 downto 0) <= MUX_TCPHDR;
1675  when others => SND_DATA(31 downto 0) <= OPTION_data;
1676  end case;
1677  if(CTRLcntr(3 downto 0) = x"b")then
1678  rd_OPTION <= '1';
1679  else
1680  rd_OPTION <= '0';
1681  end if;
1682  if(CTRLcntr(3 downto 0) = x"4")then
1683  rst_chksum <= '1';
1684  else
1685  rst_chksum <= '0';
1686  end if;
1687  SND_DATA_r <= SND_DATA(15 downto 0);
1688  chksum_in <= ('0' & SND_DATA_r) + ('0' & SND_DATA(31 downto 16));
1689  if(CTRLstate = SND and CTRLcntr(3 downto 0) = x"6")then
1690  ce_IPHDR_chksum <= '1';
1691  elsif(CTRLcntr(3 downto 0) = x"b")then
1692  ce_IPHDR_chksum <= '0';
1693  end if;
1694  if(CTRLcntr(3 downto 0) = x"7")then
1695  is_IPHDR_chksum <= '1';
1696  else
1697  is_IPHDR_chksum <= '0';
1698  end if;
1699  TCPHDR_end <= ('0' & DATA_OFFSET) + "01001";
1700  if(CTRLstate = SND and CTRLcntr(3 downto 0) = x"9")then
1701  ce_TCP_chksum <= '1';
1702  elsif(TCPHDR_cntr(3 downto 2) = "11")then
1703  ce_TCP_chksum <= '0';
1704  end if;
1705  if(ce_TCP_chksum = '0')then
1706  TCPHDR_cntr <= DATA_OFFSET;
1707  else
1708  TCPHDR_cntr <= TCPHDR_cntr - 1;
1709  end if;
1710  if(CTRLcntr(3 downto 0) = x"d")then
1711  is_TCP_chksum <= '1';
1712  else
1713  is_TCP_chksum <= '0';
1714  end if;
1715  if(sel_IPHDR_chksum = '1')then
1716  headerFIFO_DI(32 downto 16) <= SND_DATA_dl(32 downto 32) & IPHDR_chksum;
1717  else
1718  headerFIFO_DI(32 downto 16) <= SND_DATA_dl(32 downto 16);
1719  end if;
1720  if(IS_ARP_ICMP = '1')then
1721  headerFIFO_DI(33) <= SND_DATA_dl(33);
1722  else
1723  headerFIFO_DI(33) <= headerFIFO_DI(34);
1724  end if;
1725  if(sel_TCP_chksum = '1')then
1726  headerFIFO_DI(15 downto 0) <= TCP_chksum;
1727  else
1728  headerFIFO_DI(15 downto 0) <= SND_DATA_dl(15 downto 0);
1729  end if;
1730  end if;
1731 end process;
1732 i_TCP_OPTION: TCP_OPTION PORT MAP(
1733  clk => clk2x,
1734  CLOSED => IS_CLOSED,
1735  update_TSrecent => update_TSrecent,
1736  TSclock => TSclock,
1737  RCV_SYN => SEG_CTRL(bit_SYN),
1738  SND_SYN => SND_CTRL(bit_SYN),
1739  LISTEN => LISTENing,
1740  Save_ReTx => Save_ReTx,
1741  Save_ReTxTime => Save_ReTxTime,
1742  OPTION_begin => OPTION_begin,
1743  OPTION_end => OPTION_end,
1744  di => RxDout (31 downto 0),
1745  scale => SND_WND_SCALE,
1746  DATA_OFFSET => DATA_OFFSET,
1747  MSS => MSS(15 downto 0),
1748  RTT => TS_RTT ,
1749  OPTION_rdy => OPTION_rdy,
1750  TS_OPTION => TS_OPTION,
1751  rd_dout => rd_OPTION,
1752  OldData => OldData,
1753  dout => OPTION_data,
1754  debug => debug_opt
1755  );
1756 -- dataFIFO input control
1757 g_EventBufAddr: for i in 0 to 1 generate
1758  i_EventBufAddr: RAM32x6D PORT MAP(
1759  wclk => sysclk ,
1760  rclk => clk2x,
1761  di => EventBufAddr(i*6+5 downto i*6),
1762  we => EventBufAddr_we,
1763  wa => EventBufAddr_wa,
1764  ra => EventBufAddr_ra,
1765  ceReg => '1',
1766  do => EventBufAddr_do(i*6+5 downto i*6)
1767  );
1768  i_EventBufAddrH : RAM32X1D
1769  port map (
1770  DPO => EventBufAddr_dop(i+12), -- Read-only 1-bit data output
1771  SPO => open, -- R/W 1-bit data output
1772  A0 => EventBufAddr_wa(0), -- R/W address[0] input bit
1773  A1 => EventBufAddr_wa(1), -- R/W address[1] input bit
1774  A2 => EventBufAddr_wa(2), -- R/W address[2] input bit
1775  A3 => EventBufAddr_wa(3), -- R/W address[3] input bit
1776  A4 => EventBufAddr_wa(4), -- R/W address[4] input bit
1777  D => EventBufAddr(i+12), -- Write 1-bit data input
1778  DPRA0 => EventBufAddr_ra(0), -- Read-only address[0] input bit
1779  DPRA1 => EventBufAddr_ra(1), -- Read-only address[1] input bit
1780  DPRA2 => EventBufAddr_ra(2), -- Read-only address[2] input bit
1781  DPRA3 => EventBufAddr_ra(3), -- Read-only address[3] input bit
1782  DPRA4 => EventBufAddr_ra(4), -- Read-only address[4] input bit
1783  WCLK => sysclk, -- Write clock input
1784  WE => EventBufAddr_we -- Write enable input
1785  );
1786 end generate;
1787 process(sysclk,IS_CONNECTED,EventBufAddr_wa,EventBufAddr_ra1SyncRegs,EventBufAddr_ra0SyncRegs)
1788 variable s : std_logic_vector(3 downto 0);
1789 begin
1790  s := EventBufAddr_wa(1 downto 0) & EventBufAddr_ra1SyncRegs(2) & EventBufAddr_ra0SyncRegs(2);
1791  if(IS_CONNECTED = '0')then
1792  EventBufAddr_wa <= (others => '0');
1793  EventBufAddr_ra1SyncRegs <= (others => '0');
1794  EventBufAddr_ra0SyncRegs <= (others => '0');
1795  elsif(sysclk'event and sysclk = '1')then
1796  if(EventBufAddr_we = '1')then
1797  EventBufAddr_wa(1) <= EventBufAddr_wa(0);
1798  EventBufAddr_wa(0) <= not EventBufAddr_wa(1);
1799  end if;
1800  EventBufAddr_ra1SyncRegs <= EventBufAddr_ra1SyncRegs(1 downto 0) & EventBufAddr_ra(1);
1801  EventBufAddr_ra0SyncRegs <= EventBufAddr_ra0SyncRegs(1 downto 0) & EventBufAddr_ra(0);
1802  case s is
1803  when x"1" | x"7" | x"8" | x"e" => AddrBuf_full <= '1';
1804  when others => AddrBuf_full <= '0';
1805  end case;
1806  end if;
1807 end process;
1808 process(sysclk)
1809 begin
1810  if(sysclk'event and sysclk = '1')then
1811  if(EventBufAddr_we = '1')then
1812  ADDR_offset <= EventBufAddr(3 downto 0);
1813  end if;
1814  end if;
1815 end process;
1816 process(clk2x)
1817 begin
1818  if(clk2x'event and clk2x = '1')then
1819  if(IS_CONNECTED = '0')then
1820  EventBufAddr_ra <= (others => '0');
1821  elsif(EVENTdata_re_i = '1' and EVENTdata_avl = '1' and EVENTdata(65) = '1')then
1822  EventBufAddr_ra(1) <= EventBufAddr_ra(0);
1823  EventBufAddr_ra(0) <= not EventBufAddr_ra(1);
1824  end if;
1825  if(EVENTdata_re_i = '1' and EVENTdata_avl = '1' and EVENTdata(65) = '1')then
1826  SEG_ADDR(25 downto 12) <= EventBufAddr_do;
1827  SEG_ADDR(11 downto 0) <= (others => '0');
1828  elsif(headerFIFO_DI(35 downto 34) = "11" and headerFIFO_WREN = '1' and SendReTxData = '0')then
1829  SEG_ADDR(15 downto 0) <= SEG_ADDR(15 downto 0) + ("000" & data_wc);
1830  end if;
1831  MSS_cutoff <= MSS(15 downto 3) - 1;
1832  if(IS_CONNECTED = '0' and DATAstate /= IDLE)then
1833  DATAstate <= IDLE;
1834  else
1835  case DATAstate is
1836  when IDLE =>
1837  EoB <= '0';
1838  push <= '0';
1839  data2send <= '0';
1840  EVENTdata_re_i <= '0';
1841  data_wc <= (others => '0');
1842  if(EVENTdata_avl = '1' and dataFIFO_full = '0')then
1843  DATAstate <= ReadEVENTdata;
1844  EVENTdata_re_i <= '1';
1845  end if;
1846  when ReadEVENTdata =>
1847  if(EVENTdata_re_i = '1' and EVENTdata_avl = '1' and (EVENTdata(64) = '1' or data_wc = MSS_cutoff))then
1848  DATAstate <= Wait4Send;
1849  data2send <= '1';
1850  EVENTdata_re_i <= '0';
1851  else
1852  EVENTdata_re_i <= not dataFIFO_full;
1853  end if;
1854  if(EVENTdata_re_i = '1' and EVENTdata_avl = '1' and EVENTdata(66) = '1')then
1855  push <= '1';
1856  end if;
1857  if(EVENTdata_re_i = '1' and EVENTdata_avl = '1' and EVENTdata(64) = '1')then
1858  EoB <= '1';
1859  end if;
1860  if(EVENTdata_re_i = '1' and EVENTdata_avl = '1')then
1861  data_wc <= data_wc + 1;
1862  end if;
1863  when Wait4Send =>
1864  if(headerFIFO_DI(35 downto 34) = "11" and headerFIFO_WREN = '1' and SendReTxData = '0')then
1865  DATAstate <= IDLE;
1866  data2send <= '0';
1867  end if;
1868  when others => DATAstate <= IDLE;
1869  end case;
1870  end if;
1871  if(DATAstate = IDLE)then
1872  was_IDLE <= '1';
1873  else
1874  was_IDLE <= '0';
1875  end if;
1876  if(data_wc = MSS_cutoff)then
1877  dataFIFO_DI <= '1' & Eventdata(63 downto 0);
1878  else
1879  dataFIFO_DI <= Eventdata(64 downto 0);
1880  end if;
1881  dataFIFO_WREN <= EVENTdata_re_i and EVENTdata_avl;
1882  end if;
1883 end process;
1884 i_TCPdata_chksum: TCPdata_chksum PORT MAP(
1885  c => clk2x,
1886  r => rst_DATA_chksum,
1887  ce => dataFIFO_WREN,
1888  d => dataFIFO_DI(63 downto 0),
1889  DATA_OFFSET => x"0",
1890  length_in => data_wc, -- in 64bit words
1891  en_out => AttachData,
1892  s => DATA_chksum,
1893  chksum => open,
1894  DATA_SIZE => DATA_SIZE, -- in bytes
1895  DATA_LEN => DATA_LEN(15 downto 0) -- in bytes
1896  );
1897 rst_DATA_chksum <= was_IDLE;
1898 i_dataFIFO : FIFO65x12k PORT MAP(
1899  clk => clk2x,
1900  fifo_rst => FIFO_rst,
1901  fifo_en => fifo_en,
1902  di => dataFIFO_DI,
1903  we => dataFIFO_WREN,
1904  re => dataFIFO_RDEN,
1905  full => dataFIFO_full,
1906  empty => dataFIFO_empty ,
1907  do => dataFIFO_DO
1908  );
1909 dataFIFO_RDEN <= '1' when IS_CLOSED = '1' or (sel_ReTx_DATA = '0' and ClientEmacTxd_sel = "10") else '0';
1910 TCPdata <= ReTxData when sel_ReTx_DATA = '1' else dataFIFO_DO(64 downto 0);
1911 ReTxData_re <= '1' when IS_CLOSED = '1' or (sel_ReTx_DATA = '1' and ClientEmacTxd_sel = "10") else '0';
1912 -- output to EMAC
1913 process(clk2x)
1914 begin
1915  if(clk2x'event and clk2x = '1')then
1916  TCPdata_q <= TCPdata(15 downto 0);
1917  headerFIFO_eof <= headerFIFO_DO(34);
1918  if(EmacClientTack = '1')then
1919  sel_ReTx_DATA <= headerFIFO_DO(35);
1920  end if;
1921  if(fifo_en = '0')then
1922  rd_headerFIFO <= '0';
1923  elsif(EmacClientTack = '1')then
1924  rd_headerFIFO <= '1';
1925  elsif(headerFIFO_eof = '1')then
1926  rd_headerFIFO <= '0';
1927  end if;
1928  if((headerFIFO_eof = '1' and ClientEmacTxd_sel(0) = '0') or (dataFIFO_eof = '1' and ClientEmacTxd_sel(0) = '1'))then
1929  eof <= '1';
1930  else
1931  eof <= '0';
1932  end if;
1933  if(TCPdata(64) = '1' and ClientEmacTxd_sel(0) = '0')then
1934  dataFIFO_eof <= '1';
1935  else
1936  dataFIFO_eof <= '0';
1937  end if;
1938  if(fifo_en = '0' or (dataFIFO_eof = '1' and ClientEmacTxd_sel(0) = '1'))then
1939  ClientEmacTxd_sel <= "00";
1940  elsif(headerFIFO_DO(34) = '1')then
1941  ClientEmacTxd_sel <= '0' & headerFIFO_DO(35);
1942  elsif(ClientEmacTxd_sel = "01")then
1943  ClientEmacTxd_sel <= "10";
1944  elsif(ClientEmacTxd_sel(1) = '1')then
1945  ClientEmacTxd_sel(0) <= not ClientEmacTxd_sel(0);
1946  end if;
1947  case ClientEmacTxd_sel is
1948  when "00" =>
1949  if(ClientEmacTxdVld(3) = '0' or EmacClientTack = '1' or rd_headerFIFO = '1')then
1950  ClientEmacTxd <= headerFIFO_DO(31 downto 0);
1951  end if;
1952  if(fifo_en = '0' or eof = '1' or headerFIFO_EMPTY = '1' or rate_pause = '1')then
1953  ClientEmacTxdVld <= x"0";
1954  else
1955  case headerFIFO_DO(33 downto 32) is
1956  when "00" => ClientEmacTxdVld <= x"f";
1957  when "01" => ClientEmacTxdVld <= x"8";
1958  when "10" => ClientEmacTxdVld <= x"c";
1959  when others => ClientEmacTxdVld <= x"e";
1960  end case;
1961  end if;
1962  when "01" => ClientEmacTxd <= headerFIFO_DO(31 downto 16) & TCPdata(63 downto 48);
1963  ClientEmacTxdVld <= x"f";
1964  when "10" => ClientEmacTxd <= TCPdata(47 downto 16);
1965  ClientEmacTxdVld <= x"f";
1966  when others => ClientEmacTxd <= TCPdata_q & TCPdata(63 downto 48);
1967  ClientEmacTxdVld <= "11" & not dataFIFO_eof & not dataFIFO_eof;
1968  end case;
1969  if(delta_rate(7 downto 0) = x"00" or EmacClientTack = '1')then
1970  wc <= (others => '0');
1971  elsif(ClientEmacTxd_sel(1) = '1' or rd_headerFIFO = '1')then
1972  wc <= wc + delta_rate;
1973  elsif(rate_pause = '1')then
1974  wc <= wc - rate_limit;
1975  end if;
1976  if(wc(21) = '1' or delta_rate(7 downto 0) = x"00")then
1977  rate_pause <= '0';
1978 -- elsif((headerFIFO_eof = '1' and ClientEmacTxd_sel(0) = '0') or (dataFIFO_eof = '1' and ClientEmacTxd_sel(0) = '1'))then
1979  elsif(eof = '1')then
1980  rate_pause <= '1';
1981  end if;
1982  if(RxDout_type = "01" and en_RxDout = '1')then
1983  cs_out(28) <= '1';
1984  else
1985  cs_out(28) <= '0';
1986  end if;
1987  end if;
1988 end process;
1989 --cs_out(35 downto 32) <= (others => '0');
1990 --cs_out(31) <= eof;
1991 --cs_out(30) <= wc(21);
1992 --cs_out(29) <= headerFIFO_EMPTY;
1993 --cs_out(27) <= ClientEmacTxdVld(3);
1994 --cs_out(26) <= EmacClientTack;
1995 --cs_out(25) <= rd_headerFIFO;
1996 --cs_out(24) <= dataFIFO_eof;
1997 --cs_out(23) <= rate_pause;
1998 --cs_out(22 downto 21) <= ClientEmacTxd_sel;
1999 --cs_out(20 downto 0) <= wc(20 downto 0);
2000 delta_rate <= (others => '0') when and_reduce(rate_limit(6 downto 2)) = '1' else x"7c" - rate_limit;
2001 -- retransmission control
2002 i_ReTxQueue : BRAM_TDP_MACRO
2003  generic map (
2004  BRAM_SIZE => "36Kb", -- Target BRAM, "18Kb" or "36Kb"
2005  DEVICE => "7SERIES", -- Target Device: "VIRTEX5", "VIRTEX6", "7SERIES", "SPARTAN6"
2006  DOA_REG => 1, -- Optional port A output register (0 or 1)
2007  DOB_REG => 0, -- Optional port B output register (0 or 1)
2008  WRITE_MODE_A => "READ_FIRST", -- "WRITE_FIRST", "READ_FIRST" or "NO_CHANGE"
2009  WRITE_MODE_B => "READ_FIRST", -- "WRITE_FIRST", "READ_FIRST" or "NO_CHANGE"
2010  READ_WIDTH_A => 32, -- Valid values are 1-36 (19-36 only valid when BRAM_SIZE="36Kb")
2011  READ_WIDTH_B => 32, -- Valid values are 1-36 (19-36 only valid when BRAM_SIZE="36Kb")
2012  WRITE_WIDTH_A => 32, -- Valid values are 1-36 (19-36 only valid when BRAM_SIZE="36Kb")
2013  WRITE_WIDTH_B => 32) -- Valid values are 1-36 (19-36 only valid when BRAM_SIZE="36Kb")
2014  port map (
2015  DOA => open, -- Output port-A data, width defined by READ_WIDTH_A parameter
2016  DOB => ReTxQueue_DOBp , -- Output port-B data, width defined by READ_WIDTH_B parameter
2017  ADDRA => ReTxQueue_wp, -- Input port-A address, width defined by Port A depth
2018  ADDRB => ReTxQueue_ADDRB, -- Input port-B address, width defined by Port B depth
2019  CLKA => clk2x, -- 1-bit input port-A clock
2020  CLKB => clk2x, -- 1-bit input port-B clock
2021  DIA => ReTxQueue_DIA, -- Input port-A data, width defined by WRITE_WIDTH_A parameter
2022  DIB => ReTxQueue_DIB, -- Input port-B data, width defined by WRITE_WIDTH_B parameter
2023  ENA => ReTxQueue_WEA, -- 1-bit input port-A enable
2024  ENB => '1', -- 1-bit input port-B enable
2025  REGCEA => '1', -- 1-bit input port-A output register enable
2026  REGCEB => '1', -- 1-bit input port-B output register enable
2027  RSTA => '0', -- 1-bit input port-A reset
2028  RSTB => '0', -- 1-bit input port-B reset
2029  WEA => x"f", -- Input port-A write enable, width defined by Port A depth
2030  WEB => ReTxQueue_WEB -- Input port-B write enable, width defined by Port B depth
2031  );
2032 --ReTxQueue_DIB(15 downto 0) <= TSclock(27 downto 12);
2033 ReTxQueue_DIB(15 downto 0) <= TSclock(23 downto 8);
2034 ReTxQueue_WEB <= x"3" when save_ReTx = '1' else x"0";
2035 ReTxQueue_ADDRB(9 downto 2) <= ReTxQueue_rp;
2036 g_ReTx_ddr_wq: for i in 0 to 5 generate
2037  i_ReTx_ddr_wq : RAM32x6D PORT MAP(
2038  wclk => clk2x,
2039  rclk => clk2x,
2040  di => ReTx_ddr_wq_in (i*6+5 downto i*6),
2041  we => ReTx_ddr_wq_we ,
2042  wa => ReTx_ddr_wq_wa ,
2043  ra => ReTx_ddr_wq_ra ,
2044  ceReg => ReTx_ddr_wq_ceReg,
2045  do => ReTx_ddr_out_i (i*6+5 downto i*6)
2046  );
2047 end generate;
2048 ReTx_ddr_wq_ceReg <= '1' when ReTx_ddr_out_vld = '0' or RETX_ddr_wq_re = '1' else '0';
2049 --ReTx_ddr_wq_full <= ReTx_ddr_wq_wc(5);
2050 ReTx_ddr_wq_full <= ReTx_ddr_wq_wc(4);
2051 process(clk2x)
2052 begin
2053  if(clk2x'event and clk2x = '1')then
2054  ReTxQueue_DOB <= ReTxQueue_DOBp;
2055  if(IS_CONNECTED = '0')then
2056  ReTx_ddr_wq_wc <= (others => '0');
2057  elsif(ReTx_ddr_wq_we = '1' and RETX_ddr_wq_re = '0')then
2058  ReTx_ddr_wq_wc <= ReTx_ddr_wq_wc + 1;
2059  elsif(ReTx_ddr_wq_we = '0' and RETX_ddr_wq_re = '1')then
2060  ReTx_ddr_wq_wc <= ReTx_ddr_wq_wc - 1;
2061  end if;
2062  if(IS_CONNECTED = '0')then
2063  ReTx_ddr_wq_wa <= (others => '0');
2064  elsif(ReTx_ddr_wq_we = '1')then
2065  ReTx_ddr_wq_wa <= ReTx_ddr_wq_wa + 1;
2066  end if;
2067  if(IS_CONNECTED = '0')then
2068  ReTx_ddr_wq_ra <= (others => '0');
2069  elsif(ReTx_ddr_wq_wa /= ReTx_ddr_wq_ra and ReTx_ddr_wq_ceReg = '1')then
2070  ReTx_ddr_wq_ra <= ReTx_ddr_wq_ra + 1;
2071  end if;
2072  if(IS_CONNECTED = '0')then
2073  ReTx_ddr_out_vld <= '0';
2074  elsif(ReTx_ddr_wq_wa /= ReTx_ddr_wq_ra)then
2075  ReTx_ddr_out_vld <= '1';
2076  elsif(RETX_ddr_wq_re = '1')then
2077  ReTx_ddr_out_vld <= '0';
2078  end if;
2079  if(fifo_en = '0')then
2080  ReTx_ddr_wrqst_i <= '0';
2081  elsif(ReTx_ddr_wq_wc(5 downto 4) /= "00" and sel_ddr = '1' and ReTx_ddr_full = '0')then
2082  ReTx_ddr_wrqst_i <= '1';
2083  else
2084  ReTx_ddr_wrqst_i <= '0';
2085  end if;
2086  if(IS_CONNECTED = '0')then
2087  ddr_wptr <= (others => '0');
2088  elsif(TCP_wcount = '1')then
2089  ddr_wptr <= ddr_wptr + 1;
2090  end if;
2091  ReTx_ddr_rrqst_q <= ReTx_ddr_rrqst_i;
2092  if(IS_CONNECTED = '0')then
2093  ddr_rptr <= (others => '0');
2094  elsif(ReTx_ddr_rrqst_i = '1' and ReTx_ddr_rrqst_q = '0')then
2095  ddr_rptr <= ddr_rptr + ("00000000000000" & ReTx_ddr_LEN_i);
2096  end if;
2097  entry_in_ddr <= ddr_wptr - ddr_rptr;
2098  if(ReTx_ddr_rrqst_i = '0')then
2099  if(or_reduce(entry_in_ddr(18 downto 5)) = '1' or entry_in_ddr(4 downto 0) >= ReTx_ddr_LEN_max)then
2100  ReTx_ddr_LEN_i <= ReTx_ddr_LEN_max;
2101  else
2102  ReTx_ddr_LEN_i <= '0' & entry_in_ddr(3 downto 0);
2103  end if;
2104  end if;
2105  if(IS_CONNECTED = '0' or sel_ddr = '0' or (ReTx_ddr_data_we = '1' and DDR2TCPdata(32) = '1'))then
2106  ReTx_ddr_rrqst_i <= '0';
2107  elsif(ReTxQueue_entry(8 downto 7) = "00" and or_reduce(entry_in_ddr) = '1')then
2108  ReTx_ddr_rrqst_i <= '1';
2109  end if;
2110  if(IS_CONNECTED = '0' or sel_ddr = '0')then
2111  ReTx_ddr_cnt <= (others => '0');
2112  elsif(re_ReTx_ddr_wq = '1' and ReTx_ddr_data_we = '0')then
2113  ReTx_ddr_cnt <= ReTx_ddr_cnt + 1;
2114  elsif(re_ReTx_ddr_wq = '0' and ReTx_ddr_data_we = '1')then
2115  ReTx_ddr_cnt <= ReTx_ddr_cnt - 1;
2116  end if;
2117 -- ReTx_ddr_full <= and_reduce(ReTx_ddr_cnt(12 downto 4));
2118  ReTx_ddr_full <= and_reduce(ReTx_ddr_cnt(12 downto 5));
2119  ReTx_ddr_empty <= not (IS_CONNECTED and or_reduce(ReTx_ddr_cnt));
2120  if(IS_CONNECTED = '0')then
2121  ReTxQueue_entry <= (others => '0');
2122  elsif(ReTxQueue_wp(1 downto 0) = "01" and ReTxQueue_WEA = '1' and ce_ReTxQueue_rp = '0')then
2123  ReTxQueue_entry <= ReTxQueue_entry + 1;
2124  elsif((ReTxQueue_wp(1 downto 0) /= "01" or ReTxQueue_WEA = '0') and ce_ReTxQueue_rp = '1')then
2125  ReTxQueue_entry <= ReTxQueue_entry - 1;
2126  end if;
2127  if(IS_CONNECTED = '0')then
2128  ReTxQueue_wp <= (others => '0');
2129  elsif(ReTxQueue_WEA = '1')then
2130  ReTxQueue_wp <= ReTxQueue_wp + 1;
2131  end if;
2132  if(IS_CONNECTED = '0')then
2133  ReTxQueue_rp <= (others => '0');
2134  elsif(ce_ReTxQueue_rp = '1')then
2135  ReTxQueue_rp <= ReTxQueue_rp + 1;
2136  end if;
2137  if(IS_CONNECTED = '0')then
2138  ReTx_ddr_wq_re <= '0';
2139  elsif(sel_ddr = '1')then
2140  ReTx_ddr_wq_re <= re_RETX_ddr_wq;
2141  elsif(ReTx_ddr_wq_ra(1 downto 0) = "00")then
2142  ReTx_ddr_wq_re <= '0';
2143 -- elsif(or_reduce(ReTx_ddr_wq_wc(5 downto 2)) = '1' and or_reduce(ReTxQueue_entry(8 downto N)) = '0')then
2144  elsif(or_reduce(ReTx_ddr_wq_wc(5 downto 2)) = '1' and and_reduce(ReTxQueue_entry(7 downto 4)) = '0')then
2145  ReTx_ddr_wq_re <= '1';
2146  end if;
2147  if(sel_ddr = '1')then
2148  ReTxQueue_DIA <= DDR2TCPdata(31 downto 0);
2149  ReTxQueue_WEA <= ReTx_ddr_data_we;
2150  else
2151  ReTxQueue_DIA <= ReTx_ddr_out_i(31 downto 0);
2152  ReTxQueue_WEA <= ReTx_ddr_wq_re;
2153  end if;
2154  if(IS_CONNECTED = '0')then
2155  sel_ddr <= '0';
2156  elsif(ReTx_ddr_wq_wc(4) = '1' and or_reduce(ReTxQueue_entry(8 downto N)) = '1')then
2157  sel_ddr <= '1';
2158  elsif(ReTx_ddr_wq_wc(5 downto 4) = "00" and ReTx_ddr_wq_re = '0' and ReTx_ddr_empty = '1')then
2159  sel_ddr <= '0';
2160  end if;
2161  EoB_toggleSyncRegs <= EoB_toggleSyncRegs(2 downto 0) & EoB_toggle;
2162  KiloByte_toggleSyncRegs <= KiloByte_toggleSyncRegs(2 downto 0) & KiloByte_toggle;
2163 -- Written_MonBuf is the number of blocks not yet acknowleged.
2164  if(IS_CONNECTED = '0')then
2165  Written_MonBuf <= (others => '0');
2166  elsif(EoB_toggleSyncRegs(3) /= EoB_toggleSyncRegs(2) and (update_UNA_Buf = '0' or ReTxQueue_DOB(31) = '0'))then
2167  Written_MonBuf <= Written_MonBuf + 1;
2168  elsif(EoB_toggleSyncRegs(3) = EoB_toggleSyncRegs(2) and update_UNA_Buf = '1' and ReTxQueue_DOB(31) = '1')then
2169  Written_MonBuf <= Written_MonBuf - 1;
2170  end if;
2171  if(IS_CONNECTED = '0' or EoB_toggleSyncRegs(3) /= EoB_toggleSyncRegs(2))then
2172  Written_MonBlock <= ADDR_offset & "00000";
2173  elsif(KiloByte_toggleSyncRegs(3) /= KiloByte_toggleSyncRegs(2))then
2174  Written_MonBlock <= Written_MonBlock + 1;
2175  end if;
2176  if(TS_OPTION = '1')then
2177 -- RTT <= TS_RTT(27 downto 12);
2178  RTT <= TS_RTT(23 downto 8);
2179  else
2180  RTT <= STD_RTT;
2181  end if;
2182  if(IS_CONNECTED = '0')then
2183  ReTxEntry <= (others => '0');
2184  elsif(ReTx_ddr_wq_we = '1' and CTRLcntr(1 downto 0) = "01")then
2185  ReTxEntry <= ReTxEntry + 1;
2186  elsif(ce_ReTxQueue_rp = '1')then
2187  ReTxEntry <= ReTxEntry - 1;
2188  end if;
2189  if(FastRecovery = '0')then
2190  NewDataLimit <= ReTxEntry(11 downto 1);
2191  end if;
2192  if(FastRecovery = '0' or RTT_cycle = '1')then
2193  NewDataCntr <= NewDataLimit;
2194  elsif(ReTx_ddr_wq_we = '1' and CTRLcntr(1 downto 0) = "01")then
2195  NewDataCntr <= NewDataCntr - 1;
2196  end if;
2197  if(FastRecovery = '0')then
2198  SEGinFLIGHT <= '0' & ReTxEntry(11 downto 1);
2199  elsif(ReTx_ddr_wq_we = '1' and CTRLcntr(1 downto 0) = "01")then
2200  SEGinFLIGHT <= SEGinFLIGHT + 1;
2201  elsif(DupACK = '1' or NewDataACK = '1')then
2202  SEGinFLIGHT <= SEGinFLIGHT - 1;
2203  end if;
2204  if(FastRecovery = '0')then
2205  EnNewData <= '1';
2206  elsif(SEGinFLIGHT(11 downto 1) >= NewDataLimit)then
2207  EnNewData <= '0';
2208  end if;
2209  if(FastRecovery = '0')then
2210  RTT_cntr <= avg_RTT;
2211  elsif(strobe_us = '1')then
2212  if(or_reduce(RTT_cntr) = '0')then
2213  RTT_cntr <= avg_RTT;
2214  else
2215  RTT_cntr <= RTT_cntr - 1;
2216  end if;
2217  end if;
2218  if(FastRecovery = '0' or (strobe_us = '1' and or_reduce(RTT_cntr) = '0'))then
2219  RTT_cycle <= '1';
2220  else
2221  RTT_cycle <= '0';
2222  end if;
2223  end if;
2224 end process;
2225 i_RTO_CALC: RTO_CALC PORT MAP(
2226  clk => clk2x,
2227  RTT => RTT,
2228  RTOmin => RTOmin,
2229  LISTEN => LISTENing,
2230  RTO_backoff => set_ReTx_TO,
2231  sample_RTT => sample_RTT(2),
2232  RTO => RTO,
2233  debug => debug_RTO
2234  );
2235 i_TCP_CC: TCP_CC PORT MAP(
2236  clk => clk2x,
2237  reset => LISTENing,
2238  SYNRCVD => wasSYNRCVD,
2239  ReTx_TO => ReTx_TO,
2240  Save_ReTx => RTT_cycle,
2241  FastReTxStart => FastReTxStart,
2242  FR => FastRecovery,
2243  NewDataACK => NewDataACK,
2244  PartialACK => PartialACK(0),
2245  DupACK => DupACK,
2246  MSS => MSS(15 downto 0),
2247 -- CWND_max => CWND_max,
2248  SEG_WND => SEG_WND,
2249  SND_UNA => SND_UNA,
2250  SND_NXT => SND_NXT,
2251  SND_WND_UL => SND_WND_UL_CC,
2252  CWND => CWND,
2253  debug => debug_CC
2254  );
2255 process(clk2x)
2256 begin
2257  if(clk2x'event and clk2x = '1')then
2258  if(strobe_us = '1' and time_cntr = "11110100001000110")then
2259  time_sample <= '1';
2260  else
2261  time_sample <= '0';
2262  end if;
2263  if(time_sample = '1')then
2264  time_cntr <= (others => '0');
2265  elsif(strobe_us = '1')then
2266  time_cntr <= time_cntr + 1;
2267  end if;
2268  if(time_sample = '1')then
2269  rate_cntr <= (others => '0');
2270  rate <= rate_cntr;
2271  elsif(dataFIFO_WREN = '1')then
2272  rate_cntr <= rate_cntr + 1;
2273  end if;
2274  if(time_sample = '1')then
2275  deadtime_cntr <= (others => '0');
2276  deadtime <= deadtime_cntr(25 downto 10);
2277  elsif(CTRLstate = IDLE and Data2Send = '1' and SND_SPACE_OK = '0' and ClientEmacTxd_sel(1) = '0')then
2278  if(deadtime_cntr(9 downto 4) = "100111")then
2279  deadtime_cntr(9 downto 0) <= (others => '0');
2280  deadtime_cntr(25 downto 10) <= deadtime_cntr(25 downto 10) + 1;
2281  else
2282  deadtime_cntr(9 downto 0) <= deadtime_cntr(9 downto 0) + 1;
2283  end if;
2284  end if;
2285  if(sample_RTT(2) = '1')then
2286  sample_cntr <= sample_cntr + 1;
2287  if(sample_cntr = x"00")then
2288  avg_RTT <= sum_RTT(35 downto 8);
2289  sum_RTT <= (others => '0');
2290  else
2291  sum_RTT <= sum_RTT + TS_RTT;
2292  end if;
2293  end if;
2294  case TCPstate is
2295  when LISTEN => TCPstates <= "001";
2296  when SYNRCVD => TCPstates <= "010";
2297  when ESTAB => TCPstates <= "011";
2298  when LASTACK => TCPstates <= "100";
2299  when others => TCPstates <= "000";
2300  end case;
2301  case CTRLstate is
2302  when RCV_IPHDR => CTRLstates <= x"1";
2303  when RCV_TCPHDR => CTRLstates <= x"2";
2304  when RCV_PROCESS => CTRLstates <= x"3";
2305  when SND => CTRLstates <= x"4";
2306  when WAIT4SND2END => CTRLstates <= x"5";
2307  when RELEASE => CTRLstates <= x"6";
2308  when RETX => CTRLstates <= x"7";
2309  when SND_ARP_ICMP => CTRLstates <= x"8";
2310  when others => CTRLstates <= x"0";
2311  end case;
2312  case DATAstate is
2313  when ReadEventData => DATAstates <= "01";
2314  when Wait4Send => DATAstates <= "10";
2315  when others => DATAstates <= "00";
2316  end case;
2317  if(fifo_en = '0')then
2318  ReTx_FIFO_WrError <= '0';
2319  elsif(ReTx_FIFO_WrErr = '1')then
2320  ReTx_FIFO_WrError <= '1';
2321  end if;
2322  if(fifo_en = '0' or IS_CONNECTED = '0')then
2323  ReTx_FIFO_RdError <= '0';
2324  elsif(ReTxData_re = '1' and ReTx_FIFO_empty = '1')then
2325  ReTx_FIFO_RdError <= '1';
2326  end if;
2327  end if;
2328 end process;
2329 process(clk2x,rstCntr)
2330 begin
2331  if(rstCntr = '1')then
2332  ARP_rcvd_cntr <= (others => '0');
2333  ARP_sent_cntr <= (others => '0');
2334  ICMP_rcvd_cntr <= (others => '0');
2335  ICMP_sent_cntr <= (others => '0');
2336  ReTxData_wc <= (others => '0');
2337  en_RxDout_cntr <= (others => '0');
2338  Tack_cntr <= (others => '0');
2339  DataSeg_cntr <= (others => '0');
2340  ReTx_DataSeg_cntr <= (others => '0');
2341  FastReTx_cntr <= (others => '0');
2342  Save_ReTx_cntr <= (others => '0');
2343  ReTxDataACK_cntr <= (others => '0');
2344  ReTxNXT_cntr <= (others => '0');
2345  ReTx_DataErr_cntr <= (others => '0');
2346  bad_ReTx_LENCntr <= (others => '0');
2347  bad_ReTx_chksumCntr <= (others => '0');
2348  DupAckCntr <= (others => '0');
2349  NewAckCntr <= (others => '0');
2350  elsif(clk2x'event and clk2x = '1')then
2351  if(RxDout_type = "11" and en_RxDout = '1')then
2352  ARP_rcvd_cntr <= ARP_rcvd_cntr + 1;
2353  end if;
2354  if(RxDout_type = "01" and en_RxDout = '1')then
2355  ICMP_rcvd_cntr <= ICMP_rcvd_cntr + 1;
2356  end if;
2357  if(inc_ARP_sent = '1')then
2358  ARP_sent_cntr <= ARP_sent_cntr + 1;
2359  end if;
2360  if(inc_ICMP_sent = '1')then
2361  ICMP_sent_cntr <= ICMP_sent_cntr + 1;
2362  end if;
2363  if(ReTxData_we /= "00")then
2364  ReTxData_wc <= ReTxData_wc + 1;
2365  end if;
2366  if(en_RxDout = '1')then
2367  en_RxDout_cntr <= en_RxDout_cntr + 1;
2368  end if;
2369  if(EmacClientTack = '1')then
2370  Tack_cntr <= Tack_cntr + 1;
2371  end if;
2372  if(ClientEmacTxd_sel = "01" and sel_ReTx_DATA = '0')then
2373  DataSeg_cntr <= DataSeg_cntr + 1;
2374  end if;
2375  if(ClientEmacTxd_sel = "01" and sel_ReTx_DATA = '1')then
2376  ReTx_DataSeg_cntr <= ReTx_DataSeg_cntr + 1;
2377  end if;
2378  if(save_ReTx = '1' and FastReTx = '1')then
2379  FastReTx_cntr <= FastReTx_cntr + 1;
2380  end if;
2381  if(save_ReTx = '1')then
2382  save_ReTx_cntr <= save_ReTx_cntr + 1;
2383  end if;
2384  if(ReTxDataACK = '1')then
2385  ReTxDataACK_cntr <= ReTxDataACK_cntr + 1;
2386  end if;
2387  if(save_ReTx = '1' and ReTxNXT = '1')then
2388  ReTxNXT_cntr <= ReTxNXT_cntr + 1;
2389  end if;
2390  if(bad_ReTx_LEN = '1')then
2391  bad_ReTx_LENCntr <= bad_ReTx_LENCntr + 1;
2392  end if;
2393  if(bad_ReTx_chksum = '1')then
2394  bad_ReTx_chksumCntr <= bad_ReTx_chksumCntr + 1;
2395  end if;
2396  if(bad_ReTx_chksum = '1' or bad_ReTx_LEN = '1')then
2397  ReTx_DataErr_cntr <= ReTx_DataErr_cntr + 1;
2398  end if;
2399  if(DupACK = '1')then
2400  DupAckCntr <= DupAckCntr + 1;
2401  end if;
2402  if(NewDataACK = '1')then
2403  NewAckCntr <= NewAckCntr + 1;
2404  end if;
2405  end if;
2406 end process;
2407 process(ipb_addr)
2408 begin
2409  if(ipb_addr(9) = '0')then
2410  ipb_rdata <= EMAC_Rx_rdata;
2411  elsif(ipb_addr(5) = '0')then
2412  ipb_rdata <= status(conv_integer(ipb_addr(4 downto 0)));
2413  else
2414  ipb_rdata <= statusb(conv_integer(ipb_addr(4 downto 0)));
2415  end if;
2416 end process;
2417 --process(clk2x)
2418 --begin
2419 -- if(clk2x'event and clk2x = '1')then
2420 -- if(TSclock(15 downto 0) = x"0000")then
2421  statusb(0) <= en_RxDout_cntr;
2422  statusb(1) <= ARP_sent_cntr & ARP_rcvd_cntr;
2423  statusb(2) <= ICMP_sent_cntr & ICMP_rcvd_cntr;
2424  statusb(3) <= DupAckCntr;
2425  statusb(4) <= FastReTx_cntr;
2426  statusb(5) <= ReTx_DataSeg_cntr;
2427  statusb(6) <= DataSeg_cntr;
2428  statusb(7) <= NewAckCntr;
2429  statusb(8) <= ReTxNXT_Cntr;
2430  statusb(9) <= x"00000" & '0' & Written_MonBuf;
2431  statusb(10) <= "0000000" & ReTxDataLastAddr(15 downto 7) & "0000000" & Written_MonBlock;
2432  statusb(11) <= "000" & ReTxDataLEN_i & x"0" & CLOSE_flag & "000" & SEG_CTRL;
2433  statusb(12) <= "000000" & ReTxDataAddr_i;
2434  statusb(13) <= x"000" & '0' & ddr_wptr;
2435  statusb(14) <= x"000" & '0' & ddr_rptr;
2436  statusb(15) <= x"0000" & "000" & ReTx_ddr_cnt;
2437  statusb(16) <= input_SEG_WND1 & input_SEG_WND0;
2438  statusb(17) <= x"000" & SND_WND_SCALE & input_SEG_WND2;
2439  statusb(18) <= SEG_WND;
2440  statusb(19) <= SND_WL1;
2441  statusb(20) <= SND_WL2;
2442  statusb(21) <= Save_ReTX_cntr & ReTxDataACK_cntr;
2443  statusb(22) <= delta_rate & "00" & wc;
2444  status(0) <= SND_UNA;
2445  status(1) <= SND_NXT;
2446  status(2) <= SND_WND;
2447  status(3) <= CWND;
2448  status(4) <= SND_SEQ;
2449  status(5) <= SND_ACK;
2450  status(6) <= SEG_SEQ;
2451  status(7) <= SEG_ACK;
2452  status(8) <= ReTx_SEQ;
2453 -- end if;
2454  status(9) <= TSclock;
2455 -- if(TSclock(15 downto 0) = x"0000")then
2456  status(10) <= ReTxQueue_DOB;
2457  status(11) <= MSS;
2458  status(12) <= RTO_timer & RTO;
2459  status(13) <= "000" & ReTxQueue_entry & ReTxQueue_rp & ReTxQueue_wp & "00";
2460  status(14) <= SND_WND_UL;
2461  status(15) <= Tack_cntr;
2462  status(16) <= '0' & Rate & "000000";
2463  status(17) <= x"000" & deadtime & x"0";
2464  status(18) <= ISS;
2465  status(19) <= IRS;
2466  status(20) <= "000" & data_wc & DATA_SIZE(15 downto 0);
2467  status(21) <= SND_WND_UL_CC;
2468  status(22) <= ReTxData_wc;
2469  status(23) <= x"0" & avg_RTT;
2470  status(24) <= "00" & ReTxDataCntr & ReTx_DataErr_cntr;
2471  status(25) <= recover;
2472  status(26) <= bad_ReTx_chksumCntr & bad_ReTx_LENCntr;
2473  status(27) <= bad_LEN_pair;
2474  status(28) <= bad_chksum_pair;
2475  status(31) <= OPTION_rdy & "000000000" & ReTx_ddr_wq_wc & EventBufAddr_wa(1 downto 0) & EventBufAddr_ra(1 downto 0) & '0' & saved_data_wc;
2476 -- status(29)
2477  status(29)(31) <= save_ReTx;
2478  status(29)(30) <= ReTx_TO;
2479  status(29)(29) <= ReTx_FIFO_empty;
2480  status(29)(28) <= rate_pause;
2481 -- status(29)(27) <= ReTx_ddr_wq_full;
2482  status(29)(26) <= WaitReTxData;
2483  status(29)(25) <= SendReTxData;
2484  status(29)(22) <= ReTx_ddr_empty;
2485  status(29)(21) <= FastReTx;
2486  status(29)(20) <= sel_ddr;
2487  status(29)(19) <= ReleasePending;
2488  status(29)(18) <= ReTxentry_avl;
2489  status(29)(17) <= ReTx_ddr_full;
2490  status(29)(16) <= ReTxData_avl;
2491 -- status(29)(15) <= FastRecovery;
2492  status(29)(14) <= ReTx_FIFO_WrError;
2493  status(29)(13) <= ReTx_FIFO_RdError;
2494  status(29)(11) <= EnNewData;
2495  status(29)(10) <= SND_SPACE_OK;
2496  status(29)(9) <= SND_SPACE_CC_OK;
2497  status(29)(8) <= Data2Send;
2498  status(29)(7) <= headerFIFO_full;
2499  status(29)(6) <= ReTx_ddr_wq_full;
2500  status(29)(5) <= FastRecovery;
2501  status(29)(4) <= TO_Recovery;
2502  status(29)(2 downto 0) <= ReTx_cnt;
2503 -- status(30)
2504  status(30)(31 downto 29) <= ReTxDataRqst_i;
2505 -- status(30)(30) <= Data2Send;
2506 -- status(30)(29) <= SND_SPACE_CC_OK;
2507  status(30)(28) <= AttachData;
2508  status(30)(27) <= dataFIFO_empty;
2509  status(30)(26) <= headerFIFO_EMPTY;
2510 -- status(30)(25) <= headerFIFO_full;
2511  status(30)(24) <= dataFIFO_full;
2512  status(30)(23 downto 19) <= ReTx_CTRL;
2513  status(30)(18 downto 14) <= SND_CTRL(4 downto 0);
2514  status(30)(13 downto 12) <= ClientEmacTxd_sel;
2515  status(30)(11) <= rdy2send;
2516  status(30)(10) <= RxDout_avl;
2517  status(30)(9) <= EVENTdata_avl;
2518  status(30)(8 downto 7) <= DATAstates;
2519  status(30)(6 downto 4) <= TCPstates;
2520  status(30)(3 downto 0) <= CTRLstates;
2521 -- end if;
2522 -- end if;
2523 --end process;
2524 end Behavioral;
2525 
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