behavioral Architecture Reference

List of all members.

Processes
PROCESS_143	( LINKDown_s ,SYS_CLK )

Components
fed_itf	<Entity fed_itf>
Core_logic	<Entity Core_logic>
build_pckt_s_XGMII	<Entity build_pckt_s_XGMII>
xaui_wd_align	<Entity xaui_wd_align>
rcv_pckt_s_XGMII	<Entity rcv_pckt_s_XGMII>
reset_resync	<Entity reset_resync>

Signals
data_rcv	std_logic_vector ( 31 downto 0 )
ena_cmd	std_logic
sta_dt	std_logic_vector ( 63 downto 0 )
ena_ack	std_logic
seqnb_rcv	std_logic_vector ( 30 downto 0 )
idle_state	std_logic
end_snd_pckt	std_logic
rd_dt	std_logic
cmd_rcv	std_logic_vector ( 31 downto 0 )
cmd	std_logic_vector ( 63 downto 0 )
len_pckt	std_logic_vector ( 15 downto 0 )
Seq_nb	std_logic_vector ( 30 downto 0 )
card_ID_rcv	std_logic_vector ( 15 downto 0 )
card_ID_snd	std_logic_vector ( 15 downto 0 )
read_bck	std_logic_vector ( 63 downto 0 )
data_evt	std_logic_vector ( 63 downto 0 )
data_pckt	std_logic
ack_pckt	std_logic
init_pckt	std_logic
start_pckt	std_logic
end_blk_fed	std_logic
stop_evt	std_logic
start_evt	std_logic
wr_ena	std_logic
block_sz_fed	std_logic_vector ( 15 downto 0 )
data_fed	std_logic_vector ( 63 downto 0 )
block_free	std_logic
wr_cmd	std_logic
func	std_logic_vector ( 31 downto 0 )
data_wr	std_logic_vector ( 31 downto 0 )
data_rd	std_logic_vector ( 63 downto 0 )
cnt_pckt_rcv	std_logic_vector ( 31 downto 0 )
cnt_pckt_snd	std_logic_vector ( 31 downto 0 )
status_state_build_p	std_logic_vector ( 31 downto 0 )
status_state_core	std_logic_vector ( 31 downto 0 )
DATAo_unswapped	std_logic_vector ( 31 downto 0 )
CTRLo_unswapped	std_logic_vector ( 3 downto 0 )
DATAi_unswapped	std_logic_vector ( 31 downto 0 )
CTRLi_unswapped	std_logic_vector ( 3 downto 0 )
req_reset_resync	std_logic
retransmit	std_logic
reg_datai	std_logic_vector ( 63 downto 0 )
req_uctrli	std_logic
req_weni	std_logic
G_reset	std_logic
GRst_sysckl	std_logic
GRst_T_ckl	std_logic
GRst_R_ckl	std_logic
Rst_sysckl	std_logic
Rst_T_ckl	std_logic
Rst_R_ckl	std_logic
LINKDown_s	std_logic
datai_aligned	std_logic_vector ( 63 downto 0 )
k_byte_aligned	std_logic_vector ( 7 downto 0 )

Instantiations
Rst_sysckl_i1	reset_resync <Entity reset_resync>
Rst_T_ckl_i1	reset_resync <Entity reset_resync>
Rst_R_ckl_i1	reset_resync <Entity reset_resync>
GRst_sysckl_i1	reset_resync <Entity reset_resync>
GRst_T_ckl_i1	reset_resync <Entity reset_resync>
GRst_R_ckl_i1	reset_resync <Entity reset_resync>
i1	fed_itf <Entity fed_itf>
i2	Core_logic <Entity Core_logic>
i3	build_pckt_s_XGMII <Entity build_pckt_s_XGMII>
i0	xaui_wd_align <Entity xaui_wd_align>
i4	rcv_pckt_s_XGMII <Entity rcv_pckt_s_XGMII>

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Detailed Description

Definition at line 50 of file slink_opt.vhd.

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The documentation for this class was generated from the following files:

• src/CMS_DAQ_if/10Gb/slink/slink_opt.vhd