AMC13
Firmwares for the different applications of the AMC13 uTCA board made at Boston University
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slink_opt.vhd
1 ------------------------------------------------------
2 -- SLINK Optical interface sender
3 --
4 -- Ver 1.00
5 --
6 -- Dominique Gigi May 2015
7 ------------------------------------------------------
8 -- INstatiate the differents components for sender optical SLINK
9 -- Bit 31 of the "cmd" specifies if it is a write '1' or a read '0'
10 -- Command DAQON/DAQOFF cmd = 0x10006 Func(6) DT30 = 1 DAQ OFF =0 DAQON
11 -- DT31 = 1 TEST mode =0 No TEST mode
12 --
13 ------------------------------------------------------
14 LIBRARY ieee;
15 USE ieee.std_logic_1164.all;
16 use ieee.numeric_std.all;
17 use ieee.std_logic_unsigned.all;
18 
19 
20 entity SLINK_opt_XGMII is
21 port (
22  reset : in std_logic;
23  -- FED interface
24  SYS_CLK : in std_logic;
25  LINKWe : in std_logic;
26  LINKCtrl : in std_logic;
27  LINKData : in std_logic_vector(63 downto 0);
28  src_ID : in std_logic_vector(15 downto 0);
29  inject_err : in std_logic_vector(17 downto 0);
30  read_CE : in std_logic;
31  Addr : in std_logic_vector(15 downto 0);
32  status_data : out std_logic_vector(63 downto 0);
33  LINKDown : out std_logic;
34  LINK_LFF : out std_logic;
35 
36  -- interface SERDES
37  clock : in std_logic;
38  serdes_init : in std_logic;
39  SD_Data_o : out std_logic_vector(63 downto 0);
40  SD_Kb_o : out std_logic_vector(7 downto 0);
41  clock_r : in std_logic;
42  SD_Data_i : in std_logic_vector(63 downto 0);
43  SD_Kb_i : in std_logic_vector(7 downto 0);
44 
45  Serdes_status : in std_logic_vector(31 downto 0)
46 
47  );
48 end SLINK_opt_XGMII;
49 
50 architecture behavioral of SLINK_opt_XGMII is
51 
52 component fed_itf
53 generic (generator : boolean := true);
54 port (
55  reset_sysCLK : in std_logic;
56  Greset_sysCLK : in std_logic;
57  sys_clk : in std_logic;
58  LinkWe : in STD_LOGIC;
59  LinkCtrl : in STD_LOGIC;
60  LinkData : in STD_LOGIC_VECTOR (63 downto 0);
61  LinkAlmostFull : out STD_LOGIC;
62  LinkDown : out STD_LOGIC;
63  src_ID : in STD_LOGIC_VECTOR (15 downto 0);
64  inject_err : in STD_LOGIC_VECTOR (17 downto 0);
65  read_ce : in STD_LOGIC;
66  addr : in STD_LOGIC_VECTOR (15 downto 0);
67  status_data : out STD_LOGIC_VECTOR (63 downto 0);
68  reset_CLK : in std_logic;
69  Greset_CLK : in std_logic;
70  clock : in std_logic; -- clock from internal logic
71  block_free : in std_logic; -- almost one block is free
72  data_fed : out std_logic_vector(63 downto 0);
73  block_sz_fed : out std_logic_vector(15 downto 0);
74  wr_ena : out std_logic;
75  start_evt : out std_logic;
76  stop_evt : out std_logic;
77  end_blk_fed : out std_logic;
78  wr_cmd : in std_logic;
79  func : in std_logic_vector(31 downto 0);
80  data_wr : in std_logic_vector(31 downto 0);
81  data_rd : out std_logic_vector(63 downto 0);
82  cnt_evt : out std_logic; -- pulse for each event (on sys_clk)
83  cnt_pckt_rcv : in std_logic_vector(31 downto 0);
84  cnt_pckt_snd : in std_logic_vector(31 downto 0);
85  -- status
86  retransmit_ena : in std_logic;
87  status_state_build_p : in std_logic_vector(31 downto 0);
88  status_state_core : in std_logic_vector(31 downto 0);
89  Serdes_status : in std_logic_vector(31 downto 0)
90  );
91 end component;
92 
93 component Core_logic
94 port (
95  reset_clk : in std_logic;
96  Greset_clk : in std_logic;
97  clock : in std_logic;
98  -- interface from the FED block
99  data_fed : in std_logic_vector(63 downto 0);
100  wen : in std_logic;
101  start_evt : in std_logic;
102  stop_evt : in std_logic;
103  block_sz_fed : in std_logic_vector(15 downto 0);
104  end_blk_fed : in std_logic;
105  block_free : out std_logic;
106  src_ID : in std_logic_vector(15 downto 0);
107  req_reset_resync : out std_logic;
108  -- interface to the SERDES OUT (send part)
109  start_pckt : out std_logic; -- trigger the packet send
110  init_pckt : out std_logic; -- indicates that the packet is a Init packet
111  ack_pckt : out std_logic; -- indicates that the packet is a acknoldge packet
112  data_pckt : out std_logic; -- indicates that the packet is a data packet
113  data_evt : out std_logic_vector(63 downto 0); --data for data packet
114  status : out std_logic_vector(63 downto 0); --read_bck for acknowledge packet
115  card_ID : out std_logic_vector(15 downto 0); -- CARD_ID
116  Seq_nb : out std_logic_vector(30 downto 0); -- sequence number
117  len_pckt : out std_logic_vector(15 downto 0); -- length of the packet (for data packet only) other 0
118  cmd : out std_logic_vector(63 downto 0); -- command bit for data packet only
119  rd_dt : in std_logic;
120  end_snd_pckt : in std_logic;
121  idle_state : in std_logic;
122  serdes_init : in std_logic;
123  -- interface to the SERDES IN (receiver part)
124  cmd_rcv : in std_logic_vector(31 downto 0); -- command from MOL
125  data_rcv : in std_logic_vector(31 downto 0); -- data from MOL
126  ena_cmd : in std_logic; -- validate command
127  sta_dt : in std_logic_vector(63 downto 0); -- value return in an ack packet
128  ena_ack : in std_logic;
129  seqnb_rcv : in std_logic_vector(30 downto 0); -- seq numb from cmd (need an ack)
130  card_ID_rcv : in std_logic_vector(15 downto 0);
131  retransmit : out std_logic;
132  wr_cmd : out std_logic;
133  func : out std_logic_vector(31 downto 0);
134  data_wr : out std_logic_vector(31 downto 0);
135  data_rd : in std_logic_vector(63 downto 0);
136  status_state : out std_logic_vector(31 downto 0)
137  );
138 end component;
139 
140 component build_pckt_s_XGMII
141 port (
142  reset_CLK : in std_logic;
143  Greset_CLK : in std_logic;
144  clock : in std_logic;
145  start_pckt : in std_logic; -- trigger the packet send
146  init_pckt : in std_logic; -- indicates that the packet is a Init packet
147  ack_pckt : in std_logic; -- indicates that the packet is a acknoldge packet
148  data_pckt : in std_logic; -- indicates that the packet is a data packet
149  data_evt : in std_logic_vector(63 downto 0); --data for data packet
150  read_bck : in std_logic_vector(63 downto 0); --data back for acknowledge packet
151  card_ID : in std_logic_vector(15 downto 0); -- CARD_ID
152  Seq_nb : in std_logic_vector(30 downto 0); -- sequence number
153  len_pckt : in std_logic_vector(15 downto 0); -- length of the packet (for data packet only) other 0
154  cmd : in std_logic_vector(63 downto 0); -- command bit for data packet only
155  error_gen : in std_logic_vector(3 downto 0);
156  rd_dt : out std_logic; -- request data for data packet only
157  end_pckt : out std_logic;
158  datao : out std_logic_vector(63 downto 0); --- data and K bit send to SERDES
159  k_byte : out std_logic_vector( 7 downto 0);
160  idle_state : out std_logic;
161  cnt_pckt_snd : out std_logic_vector(31 downto 0);
162  status_state : out std_logic_vector(31 downto 0) );
163 end component;
164 
165 component xaui_wd_align is
166 port (
167  reset : in std_logic;
168  clock : in std_logic;
169 
170  data_i : in std_logic_vector(63 downto 0);
171  ctrl_i : in std_logic_vector(7 downto 0);
172  data_o : out std_logic_vector(63 downto 0);
173  ctrl_o : out std_logic_vector(7 downto 0)
174  );
175 end component;
176 
177 component rcv_pckt_s_XGMII
178 port (
179  reset_clk : in std_logic;
180  reset_clkT : in std_logic;
181  Greset_clk : in std_logic;
182  Greset_clkT : in std_logic;
183  clock : in std_logic;
184  clock_t : in std_logic;
185  datai : in std_logic_vector(63 downto 0); --- data and K bit send from SERDES
186  k_byte : in std_logic_vector( 7 downto 0);
187  error_gen : in std_logic;
188  cmd : out std_logic_vector(31 downto 0); -- command from MOL
189  data : out std_logic_vector(31 downto 0); -- data from MOL
190  ena_cmd : out std_logic; -- validate command
191  status : out std_logic_vector(63 downto 0); -- value return from read command request
192  seqnb : out std_logic_vector(30 downto 0); -- seq numb from cmd (need an ack)
193  ena_ack : out std_logic;
194  card_ID : out std_logic_vector(15 downto 0);
195  cnt_pckt_rcv : out std_logic_vector(31 downto 0) );
196 end component;
197 
198 component reset_resync
199 port (
200  reset : in std_logic;
201  clock : in std_logic;
202  Reset_sync : out std_logic
203  );
204 end component;
205 
206 SIGNAL data_rcv :std_logic_vector(31 downto 0);
207 SIGNAL ena_cmd :std_logic;
208 SIGNAL sta_dt :std_logic_vector(63 downto 0);
209 SIGNAL ena_ack :std_logic;
210 SIGNAL seqnb_rcv :std_logic_vector(30 downto 0);
211 SIGNAL idle_state :std_logic;
212 SIGNAL end_snd_pckt :std_logic;
213 SIGNAL rd_dt :std_logic;
214 SIGNAL cmd_rcv :std_logic_vector(31 downto 0);
215 SIGNAL cmd :std_logic_vector(63 downto 0);
216 SIGNAL len_pckt :std_logic_vector(15 downto 0);
217 SIGNAL Seq_nb :std_logic_vector(30 downto 0);
218 SIGNAL card_ID_rcv :std_logic_vector(15 downto 0);
219 SIGNAL card_ID_snd :std_logic_vector(15 downto 0);
220 SIGNAL read_bck :std_logic_vector(63 downto 0);
221 SIGNAL data_evt :std_logic_vector(63 downto 0);
222 SIGNAL data_pckt :std_logic;
223 SIGNAL ack_pckt :std_logic;
224 SIGNAL init_pckt :std_logic;
225 SIGNAL start_pckt :std_logic;
226 SIGNAL end_blk_fed :std_logic;
227 SIGNAL stop_evt :std_logic;
228 SIGNAL start_evt :std_logic;
229 SIGNAL wr_ena :std_logic;
230 SIGNAL block_sz_fed :std_logic_vector(15 downto 0);
231 SIGNAL data_fed :std_logic_vector(63 downto 0);
232 SIGNAL block_free :std_logic;
233  -- interface slave to read and write
234 SIGNAL wr_cmd : std_logic;
235 SIGNAL func : std_logic_vector(31 downto 0);
236 SIGNAL data_wr : std_logic_vector(31 downto 0);
237 SIGNAL data_rd : std_logic_vector(63 downto 0);
238 
239 SIGNAL cnt_pckt_rcv : std_logic_vector(31 downto 0);
240 SIGNAL cnt_pckt_snd : std_logic_vector(31 downto 0);
241 SIGNAL status_state_build_p : std_logic_vector(31 downto 0);
242 SIGNAL status_state_core : std_logic_vector(31 downto 0);
243 
244 SIGNAL DATAo_unswapped : std_logic_vector(31 downto 0);
245 SIGNAL CTRLo_unswapped : std_logic_vector( 3 downto 0);
246 SIGNAL DATAi_unswapped : std_logic_vector(31 downto 0);
247 SIGNAL CTRLi_unswapped : std_logic_vector( 3 downto 0);
248 SIGNAL req_reset_resync : std_logic;
249 SIGNAL retransmit : std_logic;
250 --
251 SIGNAL reg_datai : std_logic_vector(63 downto 0);
252 SIGNAL req_uctrli : std_logic;
253 SIGNAL req_weni : std_logic;
254 
255 SIGNAL G_reset : std_logic;
256 
257 
258 SIGNAL GRst_sysckl : std_logic;
259 SIGNAL GRst_T_ckl : std_logic;
260 SIGNAL GRst_R_ckl : std_logic;
261 SIGNAL Rst_sysckl : std_logic;
262 SIGNAL Rst_T_ckl : std_logic;
263 SIGNAL Rst_R_ckl : std_logic;
264 SIGNAL LINKDown_s : std_logic;
265 
266 signal datai_aligned : std_logic_vector(63 downto 0);
267 signal k_byte_aligned : std_logic_vector(7 downto 0);
268 
269 --******************************************************************
270 --******************* BEGIN **************************************
271 --******************************************************************
272 begin
273 --#################################################
274 -- reset resync
275 --#################################################
276 -- reset coming form FED
277 Rst_sysckl_i1:reset_resync
278 port map(
279  reset => reset,
280  clock => SYS_CLK,
281  Reset_sync => Rst_sysckl
282  );
283 
284 Rst_T_ckl_i1:reset_resync
285 port map(
286  reset => reset,
287  clock => clock,
288  Reset_sync => Rst_T_ckl
289  );
290 
291 Rst_R_ckl_i1:reset_resync
292 port map(
293  reset => reset,
294  clock => clock_r,
295  Reset_sync => Rst_R_ckl
296  );
297 -- reset coming form FED or from DAQ
298 G_reset <= '0' when reset = '0' or req_reset_resync = '0' else '1';
299 
300 GRst_sysckl_i1:reset_resync
301 port map(
302  reset => G_reset,
303  clock => SYS_CLK,
304  Reset_sync => GRst_sysckl
305  );
306 
307 GRst_T_ckl_i1:reset_resync
308 port map(
309  reset => G_reset,
310  clock => clock,
311  Reset_sync => GRst_T_ckl
312  );
313 
314 GRst_R_ckl_i1:reset_resync
315 port map(
316  reset => G_reset,
317  clock => clock_r,
318  Reset_sync => GRst_R_ckl
319  );
320 --#################################################
321 -- registers FED interface
322 --#################################################
323 process(LINKDown_s,SYS_CLK)
324 begin
325  if LINKDown_s = '0' then
326  req_weni <= '1';
327  elsif rising_edge(SYS_CLK) then
328  reg_datai <= LINKData;
329  req_uctrli <= LINKCtrl;
330  req_weni <= LINKWe;
331  end if;
332 end process;
333 
334 LINKDown <= LINKDown_s;
335 i1:fed_itf
336 port map(
337  reset_sysCLK => Rst_sysckl,
338  Greset_sysCLK => GRst_sysckl,
339  sys_clk => SYS_CLK,
340  LinkWe => req_weni,
341  LinkCtrl => req_uctrli,
342  LinkData => reg_datai,
343  LinkAlmostFull => LINK_LFF,
344  LinkDown => LINKDown_s,
345  src_ID => src_ID,
346  inject_err => inject_err,
347  read_ce => read_CE,
348  addr => Addr,
349  status_data => status_data,
350  reset_CLK => Rst_T_ckl,
351  Greset_CLK => GRst_T_ckl,
352  clock => clock,
353  block_free => block_free,
354  data_fed => data_fed,
355  block_sz_fed => block_sz_fed,
356  wr_ena => wr_ena,
357  start_evt => start_evt,
358  stop_evt => stop_evt,
359  end_blk_fed => end_blk_fed,
360  wr_cmd => wr_cmd,
361  func => func,
362  data_wr => data_wr,
363  data_rd => data_rd,
364  --cnt_evt => cnt_evt,
365  cnt_pckt_rcv => cnt_pckt_rcv,
366  cnt_pckt_snd => cnt_pckt_snd,
367  retransmit_ena => retransmit,
368  status_state_build_p => status_state_build_p,
369  status_state_core => status_state_core,
370  Serdes_status => Serdes_status );
371 
372 i2:Core_logic
373 port map(
374  reset_clk => Rst_T_ckl,
375  Greset_clk => GRst_T_ckl,
376  clock => clock,
377  -- interface from the FED block
378  data_fed => data_fed,
379  wen => wr_ena,
380  start_evt => start_evt,
381  stop_evt => stop_evt,
382  block_sz_fed => block_sz_fed,
383  end_blk_fed => end_blk_fed,
384  block_free => block_free,
385  src_ID => src_ID,
386  req_reset_resync => req_reset_resync,
387  -- interface to the SERDES OUT (send part)
388  start_pckt => start_pckt,
389  init_pckt => init_pckt,
390  ack_pckt => ack_pckt,
391  data_pckt => data_pckt,
392  data_evt => data_evt,
393  status => read_bck,
394  card_ID => card_ID_snd,
395  Seq_nb => Seq_nb,
396  len_pckt => len_pckt,
397  cmd => cmd,
398  rd_dt => rd_dt,
399  end_snd_pckt => end_snd_pckt,
400  idle_state => idle_state,
401  serdes_init => serdes_init,
402  -- interface to the SERDES IN (receiver part)
403  cmd_rcv => cmd_rcv,
404  data_rcv => data_rcv,
405  ena_cmd => ena_cmd,
406  sta_dt => sta_dt,
407  ena_ack => ena_ack,
408  seqnb_rcv => seqnb_rcv,
409  card_ID_rcv => card_ID_rcv,
410  retransmit => retransmit,
411  wr_cmd => wr_cmd,
412  func => func,
413  data_wr => data_wr,
414  data_rd => data_rd,
415  status_state => status_state_core);
416 
417 i3:build_pckt_s_XGMII
418 port map(
419  reset_CLK => Rst_T_ckl,
420  Greset_CLK => GRst_T_ckl,
421  clock => clock,
422  start_pckt => start_pckt,
423  init_pckt => init_pckt,
424  ack_pckt => ack_pckt,
425  data_pckt => data_pckt,
426  data_evt => data_evt,
427  read_bck => read_bck,
428  card_ID => card_ID_snd,
429  Seq_nb => Seq_nb,
430  len_pckt => len_pckt,
431  cmd => cmd,
432  error_gen => inject_err(4 downto 1),
433  rd_dt => rd_dt,
434  end_pckt => end_snd_pckt,
435 
436  datao => SD_Data_o,
437  k_byte => SD_Kb_o,
438  idle_state => idle_state,
439  status_state => status_state_build_p,
440  cnt_pckt_snd => cnt_pckt_snd);
441 
442 i0:xaui_wd_align
443 port map(
444  reset => GRst_T_ckl,
445  clock => clock,
446 
447  data_i => SD_Data_i,
448  ctrl_i => SD_Kb_i,
449  data_o => datai_aligned,
450  ctrl_o => k_byte_aligned
451  );
452 
453 i4:rcv_pckt_s_XGMII
454 port map(
455  reset_clk => Rst_R_ckl,
456  reset_clkT => Rst_T_ckl,
457  Greset_clk => GRst_R_ckl,
458  Greset_clkT => GRst_T_ckl,
459  clock => clock_r,
460  clock_t => clock,
461  datai => datai_aligned,
462  k_byte => k_byte_aligned,
463  error_gen => inject_err(5),
464  cmd => cmd_rcv,
465  data => data_rcv,
466  ena_cmd => ena_cmd,
467  status => sta_dt,
468  ena_ack => ena_ack,
469  seqnb => seqnb_rcv,
470  card_ID => card_ID_rcv,
471  cnt_pckt_rcv => cnt_pckt_rcv);
472 
473 
474 end behavioral;
475 
476 
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