Behavioral Architecture Reference

List of all members.

Processes
PROCESS_843	( DCLK )

Components
S6Link_adapt_starter	<Entity S6Link_adapt_starter>
S6Link_ctle_agc_comp	<Entity S6Link_ctle_agc_comp>
S6Link_agc_loop_fsm	<Entity S6Link_agc_loop_fsm>

Signals
rst	std_logic
start_done	std_logic
done_pre	std_logic
lock_done	std_logic
ctle3_done	std_logic
en_b	std_logic
daddr_starter	std_logic_vector ( 8 downto 0 )
den_starter	std_logic
dwe_starter	std_logic
daddr_lock	std_logic_vector ( 8 downto 0 )
den_lock	std_logic
dwe_lock	std_logic
di_lock	std_logic_vector ( 15 downto 0 )
daddr_ctle	std_logic_vector ( 8 downto 0 )
den_ctle	std_logic
dwe_ctle	std_logic
di_ctle	std_logic_vector ( 15 downto 0 )
holds	std_logic_vector ( 3 downto 0 )
rst_lock	std_logic
rst_ctle	std_logic
rst_ctle_b	std_logic
rst_ctle_pre	std_logic
lock_done_r	std_logic
lock_done_r2	std_logic
lock_state	std_logic_vector ( 3 downto 0 )
lock_count	std_logic_vector ( 31 downto 0 )
lock0	std_logic
lock1	std_logic
lock2	std_logic
lock3	std_logic
starter_state	std_logic_vector ( 3 downto 0 )
starter_count	std_logic_vector ( 2 downto 0 )
starter_rst_int	std_logic
ctle_state	std_logic_vector ( 3 downto 0 )
lock_done_rise	std_logic
done_reg	std_logic

Instantiations
i_starter	S6Link_adapt_starter <Entity S6Link_adapt_starter>
i_lock	S6Link_agc_loop_fsm <Entity S6Link_agc_loop_fsm>
i_ctle	S6Link_ctle_agc_comp <Entity S6Link_ctle_agc_comp>

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Detailed Description

Definition at line 106 of file s6link_adapt_top_dfe.vhd.

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The documentation for this class was generated from the following files:

• src/common/IPBUS/S6Link/s6link_adapt_top_dfe.vhd