S6Link_agc_loop_fsm Entity Reference

Inheritance diagram for S6Link_agc_loop_fsm:

List of all members.

Entities
Behavioral	architecture

Generics
usr_clk	integer range 0 to 4095 := 150

Ports
DCLK	in std_logic
reset	in std_logic
DRDY	in std_logic
D0	in STD_LOGIC_VECTOR ( 15 downto 0 )
DI	out STD_LOGIC_VECTOR ( 15 downto 0 )
holds	out STD_LOGIC_VECTOR ( 3 downto 0 )
DWE	out std_logic
DEN	out std_logic
DADDR	out STD_LOGIC_VECTOR ( 8 downto 0 )
kill	out std_logic
state	out STD_LOGIC_VECTOR ( 3 downto 0 )
count_lock_out	out STD_LOGIC_VECTOR ( 31 downto 0 )
lock0	out std_logic
lock1	out std_logic
lock2	out std_logic
lock3	out std_logic

---

Detailed Description

Definition at line 319 of file s6link_agc_loop_fsm.vhd.

---

The documentation for this class was generated from the following file:

• src/common/IPBUS/S6Link/s6link_agc_loop_fsm.vhd