behavioral Architecture Reference

List of all members.

Processes
PROCESS_65	( reset_clk ,clock )
PROCESS_66	( reset_clk ,clock )
PROCESS_67	( reset_clk ,clock )
PROCESS_68	( reset_clk ,clock )
PROCESS_69	( reset_clk ,clock )
PROCESS_70	( reset_clk ,clock )
PROCESS_71	( Greset_clk ,clock )
PROCESS_72	( Greset_clk ,clock )
PROCESS_73	( Greset_clk ,clock )
PROCESS_74	( Greset_clk ,clock )
PROCESS_75	( Greset_clk ,clock )
PROCESS_76	( Greset_clk ,clock )
PROCESS_77	( Greset_clk ,clock )
PROCESS_78	( reset_clk ,clock )
PROCESS_79	( req_ack_pckt ,blk_rd ,a ,b ,c ,d ,seq_nm_cmd )
PROCESS_80	( reset_clk ,clock )
PROCESS_81	( reset_clk ,clock )
PROCESS_82	( clock )
PROCESS_185	( reset_clk ,clock )
PROCESS_186	( reset_clk ,clock )
PROCESS_187	( reset_clk ,clock )
PROCESS_188	( reset_clk ,clock )
PROCESS_189	( reset_clk ,clock )
PROCESS_190	( reset_clk ,clock )
PROCESS_191	( Greset_clk ,clock )
PROCESS_192	( Greset_clk ,clock )
PROCESS_193	( Greset_clk ,clock )
PROCESS_194	( Greset_clk ,clock )
PROCESS_195	( Greset_clk ,clock )
PROCESS_196	( Greset_clk ,clock )
PROCESS_197	( Greset_clk ,clock )
PROCESS_198	( reset_clk ,clock )
PROCESS_199	( req_ack_pckt ,blk_rd ,a ,b ,c ,d ,seq_nm_cmd )
PROCESS_200	( reset_clk ,clock )
PROCESS_201	( reset_clk ,clock )
PROCESS_202	( clock )

Components
dist_mem_gen_0
	!!!!!!!!!!!!!!!!!!! XILINX VERSION Vivado
Memory	<Entity Memory>

Types
record: descript	seq_num : std_logic_vector ( 30 downto 0 ) time_out : std_logic_vector ( 15 downto 0 ) time_out_ON : std_logic command : std_logic_vector ( 31 downto 0 ) lenght : std_logic_vector ( 15 downto 0 ) blk_used : std_logic to_be_send : std_logic mem_ACK : std_logic

Signals
add_w_cnt	std_logic_vector ( 8 downto 0 )
block_w_add	std_logic_vector ( 1 downto 0 )
add_r_cnt	std_logic_vector ( 8 downto 0 )
block_r_add	std_logic_vector ( 1 downto 0 )
blk_wr	std_logic_vector ( 3 downto 0 )
blk_rd	std_logic_vector ( 3 downto 0 )
blk_time_out	std_logic_vector ( 3 downto 0 )
time_out_reach	std_logic_vector ( 3 downto 0 )
reset_bar	std_logic
FULL_block	std_logic
a	descript
b	descript
c	descript
d	descript
timer	std_logic_vector ( 15 downto 0 )
seq_number	std_logic_vector ( 31 downto 0 )
cmd_mem	std_logic
seq_nm_cmd	std_logic_vector ( 30 downto 0 )
req_send_pckt	std_logic
req_init_pckt	std_logic
req_ack_pckt	std_logic
req_data_pckt	std_logic
init_done	std_logic
pulse_gen_a	std_logic
retransmit_ena	std_logic_vector ( 3 downto 0 )
retrans_sig	std_logic
timer_sec	std_logic_vector ( 19 downto 0 )
resync_timer	std_logic_vector ( 3 downto 0 )
nb_retrans	std_logic_vector ( 7 downto 0 )
low_buffer	std_logic
buffer_a	std_logic_vector ( 31 downto 0 )
seq_cmd_mem	std_logic_vector ( 31 downto 0 )
execute_CMD	std_logic
gen_reset	std_logic_vector ( 2 downto 0 )
req_resync_slink	std_logic
del_end_send	std_logic_vector ( 3 downto 0 )
gen_reset	std_logic_vector ( rst_length downto 0 )

Instantiations
mem	Memory <Entity Memory>

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Detailed Description

Definition at line 68 of file core_logic.vhd.

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The documentation for this class was generated from the following files:

• src/CMS_DAQ_if/10Gb/slink/core_logic.vhd
• src/CMS_DAQ_if/5Gb/slink/core_logic.vhd