AMC13
Firmwares for the different applications of the AMC13 uTCA board made at Boston University
 All Classes Variables
ttc_if.vhd
1 -- TTCrx interface module
2 -- TTCrx register file occupies 128 bytes of memory space
3 -- to simplify the design, all accesses are 32 bit wide,
4 -- although only the LSB byte carries data.
5 -- according to TTCrx manual, its SCL line is input only.
6 -- So no arbitration and no wait holding are assumed in this design.
7 -- TTC Hamming encoding (short)
8 -- hmg[0] = d[0]^d[1]^d[2]^d[3];
9 -- hmg[1] = d[0]^d[4]^d[5]^d[6];
10 -- hmg[2] = d[1]^d[2]^d[4]^d[5]^d[7];
11 -- hmg[3] = d[1]^d[3]^d[4]^d[6]^d[7];
12 -- hmg[4] = d[0]^d[2]^d[3]^d[5]^d[6]^d[7];
13 -- TTC Hamming encoding (long)
14 -- hmg(0) <= xor_reduce(d(5 downto 0));
15 -- hmg(1) <= xor_reduce(d(20 downto 6));
16 -- hmg(2) <= xor_reduce(d(27 downto 21)) xor xor_reduce(d(13 downto 6));
17 -- hmg(3) <= xor_reduce(d(30 downto 28)) xor xor_reduce(d(24 downto 21)) xor xor_reduce(d(17 downto 14)) xor xor_reduce(d(9 downto 6)) xor xor_reduce(d(2 downto 0));
18 -- hmg(4) <= d(31) xor d(29) xor d(28) xor d(26) xor d(25) xor d(22) xor d(21) xor d(19) xor d(18) xor d(15) xor d(14) xor d(11) xor d(10) xor d(7) xor d(6) xor d(4) xor d(3) xor d(0);
19 -- hmg(5) <= d(31) xor d(30) xor d(28) xor d(27) xor d(25) xor d(23) xor d(21) xor d(20) xor d(18) xor d(16) xor d(14) xor d(12) xor d(10) xor d(8) xor d(6) xor d(5) xor d(3) xor d(1);
20 -- hmg(6) <= d(31) xor d(30) xor d(29) xor d(27) xor d(26) xor d(24) xor d(21) xor d(20) xor d(19) xor d(17) xor d(14) xor d(13) xor d(10) xor d(8) xor d(7) xor d(5) xor d(4) xor d(2);
21 -- hmg(6) <= xor_reduce(d) xor xor_reduce(hmg(5 downto 0));
22 -- reset orbit counter command 001x1xxx
23 library IEEE;
24 use IEEE.STD_LOGIC_1164.ALL;
25 use IEEE.STD_LOGIC_ARITH.ALL;
26 use IEEE.STD_LOGIC_UNSIGNED.ALL;
27 use IEEE.std_logic_misc.all;
28 use work.amc13_pack.all;
29 library UNISIM;
30 use UNISIM.VComponents.all;
31 Library UNIMACRO;
32 use UNIMACRO.vcomponents.all;
33 entity ttc_if is
34  Port (
35  clk : in std_logic;
36  refclk : in std_logic;
37  reset : in std_logic;
38  rst_PLL : in std_logic;
39  run : in std_logic;
40  DB_cmd_in : in std_logic;
41  DB_cmd_out : out std_logic;
42 -- IsG2 : in std_logic;
43  BC0 : out std_logic;
44  TTC_strobe : out std_logic;
45  sys_lock : in std_logic;
46  local_TTC : in STD_LOGIC; --! Controls TTS output (for fake TTC output)
47  local_TTCcmd : in STD_LOGIC;
48  single_TTCcmd : in STD_LOGIC;
49  TTS_clk : out std_logic;
50 -- CDR signals
51  DIV4 : out STD_LOGIC;
52  DIV_nRST : out STD_LOGIC;
53  CDRclk_p : in STD_LOGIC;
54  CDRclk_n : in STD_LOGIC;
55  CDRclk_out : out STD_LOGIC;
56  CDRdata_p : in STD_LOGIC;
57  CDRdata_n : in STD_LOGIC;
58  TTCdata_p : out STD_LOGIC;
59  TTCdata_n : out STD_LOGIC;
60  TTC_LOS : in STD_LOGIC;
61  TTC_LOL : in STD_LOGIC;
62 -- bcn offset
63  BCN_off : in std_logic_vector(12 downto 0);
64  OC_off : in std_logic_vector(3 downto 0);
65  en_cal_win : in std_logic;
66  cal_win_high : in std_logic_vector(11 downto 0); -- five MSB is constant = "110110"
67  cal_win_low : in std_logic_vector(11 downto 0); -- five MSB is constant = "110110"
68  CalType : out std_logic_vector(3 downto 0);
69  TTC_Brcst : out std_logic_vector(3 downto 0);
70 -- Local L1A control
71  en_localL1A : in std_logic;
72  LocalL1A_cfg : in std_logic_vector(31 downto 0);
73  trig_BX : in std_logic_vector(12 downto 0);
74  localL1A_s : in std_logic;
75  localL1A_r : in std_logic;
76  HCAL_trigger : in std_logic;
77  T3_trigger : in std_logic;
78  EvnRSt_l : in std_logic;
79  OcnRSt_l : in std_logic;
80  localL1A_periodic : out std_logic;
81  ovfl_warning : in std_logic;
82 -- ipbus signals
83  ipb_clk : in STD_LOGIC;
84  ipb_write : in STD_LOGIC;
85  ipb_strobe : in STD_LOGIC;
86  ipb_addr : in STD_LOGIC_VECTOR(31 downto 0);
87  ipb_wdata : in STD_LOGIC_VECTOR(31 downto 0);
88  ipb_rdata : out STD_LOGIC_VECTOR(31 downto 0);
89 -- TTCrx status : ready, single error and double error
90  en_brcst : in std_logic;
91  ttc_start : out std_logic;
92  ttc_stop : out std_logic;
93  ttc_soft_reset : out std_logic; -- TTC ReSync
94  ttc_ready : out std_logic;
95  ttc_serr : out std_logic;
96  ttc_derr : out std_logic;
97  ttc_bcnt_err : out std_logic;
98  rate_OFW : out std_logic;
99  sync_lost : out std_logic;
100  inc_oc : out std_logic;
101  inc_l1ac : out std_logic;
102  inc_bcnterr : out std_logic;
103  inc_serr : out std_logic;
104  inc_derr : out std_logic;
105  state : in std_logic_vector(3 downto 0);
106  evn_fifo_full : in std_logic;
107  IgnoreDAQ : in std_logic;
108  ttc_evcnt_reset : out std_logic;
109  event_number_avl : out std_logic;
110  event_number : out std_logic_vector(59 downto 0)
111  );
112 end ttc_if;
113 
114 architecture ttc_arch of ttc_if is
115  COMPONENT SCRAMBLER
116  generic
117  (
118  TX_DATA_WIDTH : integer := 32
119  );
120  PORT(
121  UNSCRAMBLED_DATA_IN : IN std_logic_vector((TX_DATA_WIDTH-1) downto 0);
122  DATA_VALID_IN : IN std_logic;
123  USER_CLK : IN std_logic;
124  SYSTEM_RESET : IN std_logic;
125  SCRAMBLED_DATA_OUT : OUT std_logic_vector((TX_DATA_WIDTH-1) downto 0)
126  );
127  END COMPONENT;
128  COMPONENT Threshold
129  PORT(
130  clk : IN std_logic;
131  din : IN std_logic_vector(15 downto 0);
132  nongap_size : IN std_logic_vector(11 downto 0);
133  dout : OUT std_logic_vector(31 downto 0)
134  );
135  END COMPONENT;
136  function hemming_s(d : std_logic_vector(7 downto 0)) return std_logic_vector is
137  variable hmg : std_logic_vector(4 downto 0);
138  begin
139  hmg(0) := d(0) xor d(1) xor d(2) xor d(3);
140  hmg(1) := d(0) xor d(4) xor d(5) xor d(6);
141  hmg(2) := d(1) xor d(2) xor d(4) xor d(5) xor d(7);
142  hmg(3) := d(1) xor d(3) xor d(4) xor d(6) xor d(7);
143  hmg(4) := d(0) xor d(2) xor d(3) xor d(5) xor d(6) xor d(7);
144  return hmg;
145  end hemming_s;
146  function hemming_l(d : std_logic_vector(31 downto 0)) return std_logic_vector is
147  variable hmg : std_logic_vector(6 downto 0);
148  begin
149  hmg(0) := d(5) xor d(4) xor d(3) xor d(2) xor d(1) xor d(0);
150  hmg(1) := d(20) xor d(19) xor d(18) xor d(17) xor d(16) xor d(15) xor d(14) xor d(13) xor d(12) xor d(11) xor d(10) xor d(9) xor d(8) xor d(7) xor d(6);
151  hmg(2) := d(27) xor d(26) xor d(25) xor d(24) xor d(23) xor d(22) xor d(21) xor d(13) xor d(12) xor d(11) xor d(10) xor d(9) xor d(8) xor d(7) xor d(6);
152  hmg(3) := d(30) xor d(29) xor d(28) xor d(24) xor d(23) xor d(22) xor d(21) xor d(17) xor d(16) xor d(15) xor d(14) xor d(9) xor d(8) xor d(7) xor d(6) xor d(2) xor d(1) xor d(0);
153  hmg(4) := d(31) xor d(29) xor d(28) xor d(26) xor d(25) xor d(22) xor d(21) xor d(19) xor d(18) xor d(15) xor d(14) xor d(11) xor d(10) xor d(7) xor d(6) xor d(4) xor d(3) xor d(0);
154  hmg(5) := d(31) xor d(30) xor d(28) xor d(27) xor d(25) xor d(23) xor d(21) xor d(20) xor d(18) xor d(16) xor d(14) xor d(12) xor d(10) xor d(8) xor d(6) xor d(5) xor d(3) xor d(1);
155  hmg(6) := d(31) xor d(30) xor d(29) xor d(27) xor d(26) xor d(24) xor d(21) xor d(20) xor d(19) xor d(17) xor d(14) xor d(13) xor d(10) xor d(8) xor d(7) xor d(5) xor d(4) xor d(2);
156  return hmg;
157  end hemming_l;
158  function CDRclk_period (A : string) return real is
159  begin
160  if(A = "G2")then
161  return 6.25;
162  else
163  return 6.237;
164  end if;
165  end CDRclk_period;
166  constant TTCclk_pol : std_logic := '1';
167  constant TTCdata_pol : std_logic := '1';
168  constant Coarse_Delay: std_logic_vector(3 downto 0) := x"0";
169 -- constant BX500: std_logic_vector(11 downto 0) := x"1f1";
170  signal BX500: std_logic_vector(12 downto 0);
171  signal ovfl_warning_SyncRegs : std_logic_vector(3 downto 0) := (others =>'0');
172  signal en_periodic : std_logic := '0';
173  signal en_burst : std_logic := '0';
174 -- signal every_orbit : std_logic := '0';
175  signal NextL1A : std_logic := '0';
176  signal periodicL1A_a : std_logic := '0';
177  signal periodicL1A_b : std_logic := '0';
178  signal periodicL1A_bp : std_logic := '0';
179  signal periodicL1A : std_logic := '0';
180  signal Burst_cntr : std_logic_vector(11 downto 0) := (others =>'0');
181  signal L1A_dl : std_logic := '0';
182  signal L1A_dl24 : std_logic_vector(21 downto 0) := (others =>'0');
183  signal L1A_dl99 : std_logic_vector(74 downto 0) := (others =>'0');
184  signal L1A_dl239 : std_logic_vector(139 downto 0) := (others =>'0');
185  signal random_th : std_logic_vector(32 downto 0) := (others =>'0');
186  signal lfsr : std_logic_vector(31 downto 0) := (others =>'0');
187  signal lfsr_s : std_logic_vector(32 downto 0) := (others =>'0');
188  signal rules : std_logic_vector(4 downto 0) := (others =>'0');
189  signal rule1_cntr : std_logic := '0';
190  signal rule2_cntr : std_logic_vector(1 downto 0) := (others =>'0');
191  signal rule3_cntr : std_logic_vector(1 downto 0) := (others =>'0');
192  signal OrbitCntr : std_logic_vector(15 downto 0) := (others =>'0');
193  signal BXCntr : std_logic_vector(11 downto 0) := (others =>'0');
194  signal BXCntr_b : std_logic_vector(15 downto 0) := (others =>'0');
195  signal localL1A_s_SyncRegs : std_logic_vector(3 downto 0) := (others =>'0');
196  signal localL1A_r_SyncRegs : std_logic_vector(3 downto 0) := (others =>'0');
197  signal T3_triggerSyncRegs : std_logic_vector(3 downto 0) := (others =>'0');
198  signal EvnRst_SyncRegs : std_logic_vector(3 downto 0) := (others =>'0');
199  signal OcnRst_SyncRegs : std_logic_vector(3 downto 0) := (others =>'0');
200  signal reset_SyncRegs : std_logic_vector(3 downto 0) := (others =>'0');
201  signal SendEvnRst : std_logic := '0';
202  signal SendOcnRst : std_logic := '0';
203  signal SendBC0 : std_logic := '0';
204  signal en_SendBC0 : std_logic := '0';
205  signal TTC_cmd_avl : std_logic := '0';
206  signal busy_l : std_logic := '0';
207  signal start_l : std_logic := '0';
208  signal stop_l : std_logic := '0';
209  signal Bcnt_l : std_logic_vector(11 downto 0) := (others => '0');
210  signal sr_l : std_logic_vector(40 downto 0) := (others => '0');
211 --signal TTC_cmd : std_logic_vector(3 downto 0) := (others => '0');
212  signal TTC_clkfb : std_logic := '0';
213  signal TTC_clk_dcm : std_logic := '0';
214  signal TTC_clk_lock : std_logic := '0';
215  signal TTC_clk_lock_n : std_logic := '0';
216  signal clkfb : std_logic := '0';
217  signal clk160_dcm : std_logic := '0';
218  signal clk200_dcm : std_logic := '0';
219  signal sys_lock_n : std_logic := '0';
220  signal local_TTC_n : std_logic := '0';
221  signal rst_CDR : std_logic := '0';
222  signal CDRclk_in : std_logic := '0';
223  signal PllCDRclk_in : std_logic := '0';
224  signal CDRclk_dcm : std_logic := '0';
225  signal CDRclkFB_dcm : std_logic := '0';
226  signal CDRclkFB : std_logic := '0';
227  signal CDRclk : std_logic := '0';
228  signal CDR_lock : std_logic := '0';
229  signal TTCdata : std_logic := '0';
230  signal CDRdata_in : std_logic := '0';
231  signal TTCclk_q : std_logic_vector(1 downto 0) := (others =>'0');
232  signal CDRdata : std_logic := '0';
233  signal CDRdata_q : std_logic_vector(2 downto 0) := (others =>'0');
234  signal div8 : std_logic_vector(2 downto 0) := (others =>'0');
235  signal toggle_cnt : std_logic_vector(1 downto 0) := (others =>'0');
236  signal toggle_channel : std_logic := '1';
237  signal a_channel : std_logic := '1';
238  signal L1A : std_logic := '0';
239  signal strng_length : std_logic_vector(3 downto 0) := (others =>'0');
240  signal div_rst_cnt : std_logic_vector(4 downto 0) := (others =>'0');
241  signal TTC_str : std_logic := '0';
242  signal L1Accept : std_logic := '0';
243  signal sr : std_logic_vector(12 downto 0) := (others => '0');
244  signal rec_cntr : std_logic_vector(5 downto 0) := (others => '0');
245  signal rec_cmd : std_logic := '0';
246  signal FMT : std_logic := '0';
247  signal TTC_data : std_logic_vector(2 downto 0) := (others => '0');
248  signal brcst_str : std_logic_vector(3 downto 0) := (others => '0');
249  signal brcst_data : std_logic_vector(7 downto 0) := (others => '0');
250  signal brcst_syn : std_logic_vector(4 downto 0) := (others => '0');
251  signal frame_err : std_logic := '0';
252  signal single_err : std_logic := '0';
253  signal double_err : std_logic := '0';
254  signal EvCntReset : std_logic := '0';
255  signal BCntReset : std_logic := '0';
256  signal SinErrStr : std_logic := '0';
257  signal DbErrStr : std_logic := '0';
258  signal BrcstStr : std_logic := '0';
259  signal EvCntRes : std_logic := '0';
260  signal BCntRes : std_logic := '0';
261  signal OcRes : std_logic := '0';
262  signal ReSync : std_logic := '0';
263  signal BrcstCmd : std_logic_vector(3 downto 0) := (others => '0');
264  signal Brcst : std_logic_vector(7 downto 0) := (others => '0');
265  signal TTC_tune_cnt : std_logic_vector(7 downto 0) := (others =>'0');
266  signal ttc_brcst_i : std_logic_vector(3 downto 0) := (others => '0');
267  signal ttc_sinerrstr : std_logic := '0';
268  signal ttc_dberrstr : std_logic := '0';
269  signal ttc_l1accept : std_logic := '0';
270  signal ttc_evcntres : std_logic := '0';
271  signal ttc_l1accept_dl : std_logic := '0';
272  signal ttc_bcntres_dl : std_logic := '0';
273  signal ttc_OCres_dl : std_logic := '0';
274  signal ttc_soft_reset_i : std_logic := '0';
275  signal dl_a : std_logic_vector(3 downto 0) := (others => '0');
276  signal dl_b : std_logic_vector(3 downto 0) := (others => '0');
277  signal bcnt : std_logic_vector(11 downto 0) := (others => '0');
278  signal LastBcnt : std_logic_vector(11 downto 0) := (others => '0');
279  signal oc : std_logic_vector(31 downto 0) := (others => '0');
280  signal en_bcnt_res : std_logic := '0';
281  signal en_bcnt_err : std_logic_vector(1 downto 0) := (others => '0');
282  signal brcst_GapTrig : std_logic := '0';
283  signal brcst_GapPed : std_logic := '0';
284  signal brcst_GapLaser : std_logic := '0';
285  signal rst_bcnt : std_logic := '0';
286  signal cal_win : std_logic := '0';
287  signal Laser_TO : std_logic_vector(13 downto 0) := (others => '0');
288  signal bcn_offs1 : std_logic_vector(11 downto 0) := (others => '0');
289  signal cal_type : std_logic_vector(3 downto 0) := (others => '0');
290  signal rst_cnt : std_logic_vector(1 downto 0) := (others => '0');
291  signal event_number_avl_i : std_logic := '0';
292  signal dec_rate_cntr : std_logic := '0';
293  signal rate_div : std_logic_vector(7 downto 0) := (others => '0');
294  signal rate_cntr : std_logic_vector(5 downto 0) := (others => '0');
295  signal ttc_sync_wa : std_logic_vector(1 downto 0) := (others => '0');
296  signal ttc_sync_ra : std_logic_vector(1 downto 0) := (others => '0');
297  signal ttc_sync_din : std_logic_vector(11 downto 0) := (others => '0');
298  signal ttc_sync_dout : std_logic_vector(11 downto 0) := (others => '0');
299  signal ttc_sync_wa1_SyncRegs : std_logic_vector(1 downto 0) := (others => '0');
300  signal ttc_sync_wa0_SyncRegs : std_logic_vector(1 downto 0) := (others => '0');
301  signal ttc_sync_do : std_logic_vector(11 downto 0) := (others => '0');
302  signal ttc_sync_do_val : std_logic := '0';
303  type array4X16 is array(0 to 3) of std_logic_vector(15 downto 0);
304  type array4X32 is array(0 to 3) of std_logic_vector(31 downto 0);
305  signal ttc_cmd : array4x32 := (others => (others => '0'));
306  signal ttc_cmd_cfg : array4x32 := (others => (others => '0'));
307  signal single_TTCcmd_SyncRegs : std_logic_vector(3 downto 0) := (others =>'0');
308  signal OcPrescal : array4x16 := (others => x"ffff");
309  signal NoPrescale : std_logic_vector(3 downto 0) := (others => '0');
310  signal L1A_delay : std_logic_vector(11 downto 0) := (others => '0');
311  signal SendTTC_cmd : std_logic_vector(3 downto 0) := (others => '0');
312  signal TTC_cmd_done : std_logic_vector(3 downto 0) := (others => '0');
313  signal TTC_L1A_Do : std_logic_vector(3 downto 0) := (others => '0');
314  signal TTC_L1A_Di : std_logic_vector(3 downto 0) := (others => '0');
315  signal TTC_L1A_wa : std_logic_vector(11 downto 0) := (others => '0');
316  signal TTC_L1A_ra : std_logic_vector(11 downto 0) := (others => '0');
317  signal en_TTC_L1A : std_logic := '0';
318  signal ld_sr_l : std_logic := '0';
319  signal SendFMT : std_logic := '0';
320  signal SendCmdData : std_logic_vector(31 downto 0) := (others => '0');
321  signal hmg_s : std_logic_vector(4 downto 0) := (others => '0');
322  signal hmg_l : std_logic_vector(6 downto 0) := (others => '0');
323  signal cmd_cntr : std_logic_vector(5 downto 0) := (others => '0');
324  signal bcnt_cmd : std_logic_vector(11 downto 0) := x"000";
325  signal gap_begin : std_logic_vector(11 downto 0) := x"000";
326  signal gap_end : std_logic_vector(11 downto 0) := x"000";
327  signal gap_beginp : std_logic_vector(11 downto 0) := x"000";
328  signal gap_endp : std_logic_vector(11 downto 0) := x"000";
329  signal nongap_size : std_logic_vector(11 downto 0) := x"000";
330  signal in_gap : std_logic := '0';
331  signal random_cnt : std_logic_vector(5 downto 0) := (others => '0');
332  signal OcNresetCmd : std_logic_vector(15 downto 0) := x"1728";
333  signal ReSyncCmd : std_logic_vector(15 downto 0) := x"1748";
334  signal DBCmd : std_logic_vector(15 downto 0) := x"1768";
335  signal second : std_logic_vector(25 downto 0) := (others => '0');
336  signal L1A_rate : std_logic_vector(24 downto 0) := (others => '0');
337  signal L1A_rate_q : std_logic_vector(24 downto 0) := (others => '0');
338  signal L1A_cntr : std_logic_vector(24 downto 0) := (others => '0');
339  signal L1AToggle : std_logic := '0';
340  signal L1AToggleSync : std_logic_vector(3 downto 0) := (others => '0');
341  signal DB : std_logic := '0';
342  signal DB_cmd_i : std_logic := '0';
343  signal DBSync : std_logic_vector(3 downto 0) := (others => '0');
344 component icon1
345  PORT (
346  CONTROL0 : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0));
347 
348 end component;
349 component ila36x1024
350  PORT (
351  CONTROL : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0);
352  CLK : IN STD_LOGIC;
353  DATA : IN STD_LOGIC_VECTOR(35 DOWNTO 0);
354  TRIG0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0));
355 
356 end component;
357 signal CONTROL0 : std_logic_vector(35 downto 0) := (others => '0');
358 signal cs_data : std_logic_vector(35 downto 0) := (others => '0');
359 signal cs_trig : std_logic_vector(7 downto 0) := (others => '0');
360 begin
361 --i_icon1 : icon1
362 -- port map (
363 -- CONTROL0 => CONTROL0);
364 --i_ila36x1024 : ila36x1024
365 -- port map (
366 -- CONTROL => CONTROL0,
367 -- CLK => CDRclk,
368 -- DATA => cs_data,
369 -- TRIG0 => cs_trig);
370 --cs_trig(7 downto 5) <= sr(2 downto 0);
371 --cs_trig(4) <= BCntRes;
372 --cs_trig(3) <= a_channel;
373 --cs_trig(2 downto 0) <= TTC_data;
374 --cs_data(26 downto 14) <= sr;
375 --cs_data(13) <= double_err;
376 --cs_data(12) <= single_err;
377 --cs_data(11) <= brcst_str(1);
378 --cs_data(10) <= BCntRes;
379 --cs_data(9) <= local_TTCcmd;
380 --cs_data(8) <= en_localL1A;
381 --cs_data(7) <= a_channel;
382 --cs_data(6) <= toggle_channel;
383 --cs_data(5) <= TTC_str;
384 --cs_data(4 downto 2) <= TTC_data;
385 --cs_data(1 downto 0) <= CDRdata_q(2 downto 1);
386 --cs_trig(7 downto 1) <= bcnt(11 downto 5);
387 ----cs_trig(0) <= inc_bcnterr;
388 --cs_data(33) <= local_TTC;
389 --cs_data(32 downto 30) <= ttc_sync_do(10 downto 8);
390 --cs_data(29) <= ttc_sync_do(6);
391 --cs_data(28) <= cs_trig(0);
392 --cs_data(27) <= ttc_sync_do_val;
393 --cs_data(26) <= ttc_bcntres_dl;
394 --cs_data(25 downto 24) <= en_bcnt_err;
395 --cs_data(23 downto 12) <= bcn_offs1;
396 --cs_data(11 downto 0) <= bcnt;
397 ------------------------------------------
398  LastBcnt <= x"fff" when flavor = "G2" else x"deb";
399 -- new code starts here
400  ttc_soft_reset <= ttc_soft_reset_i;
401  localL1A_periodic <= en_periodic;
402  CDRclk_out <= CDRclk;
403  TTC_strobe <= TTC_str;
404  rst_CDR <= TTC_LOL or TTC_LOS or rst_PLL;
405  DB_cmd_out <= DB_cmd_i;
406  i_CDRclk_in: ibufgds generic map(DIFF_TERM => TRUE,IOSTANDARD => "LVDS_25") port map(i => CDRclk_p, ib => CDRclk_n, o => CDRclk_in);
407  i_MMCM_CDRclk : PLLE2_BASE
408 -- generic map(CLKFBOUT_MULT => 10,CLKOUT0_DIVIDE => 8,CLKIN1_PERIOD => 6.237)
409  generic map(CLKFBOUT_MULT => 10,CLKOUT0_DIVIDE => 8,CLKIN1_PERIOD => CDRclk_period(flavor))
410  port map (
411  CLKOUT0 => clk200_dcm,
412 -- CLKOUT1 => CDRclk_dcm,
413  -- Feedback Clocks: 1-bit (each) Clock feedback ports
414 -- CLKFBOUT => CDRclkFB_dcm, -- 1-bit Feedback clock output
415  CLKFBOUT => CDRclk_dcm, -- 1-bit Feedback clock output
416  -- Clock Inputs: 1-bit (each) Clock inputs
417  CLKIN1 => CDRclk_in, -- 1-bit Clock input
418  -- Control Ports: 1-bit (each) MMCM control ports
419  PWRDWN => '0', -- 1-bit Power-down input
420  RST => rst_CDR, -- 1-bit Reset input
421  LOCKED => CDR_lock, -- 1-bit LOCK output
422  -- Feedback Clocks: 1-bit (each) Clock feedback ports
423  CLKFBIN => CDRclk -- 1-bit Feedback clock input
424  );
425  i_CDRclk_buf: bufg port map(i => CDRclk_dcm, o => CDRclk );
426 --i_CDRclkFB_buf: bufg port map(i => CDRclkFB_dcm, o => CDRclkFB);
427 g_TTCCLK: if (flavor /= "G2") generate
428  i_MMCM_TTC_clk : MMCME2_BASE
429  generic map(DIVCLK_DIVIDE => 10, CLKFBOUT_MULT_F => 64.0,CLKOUT0_DIVIDE_F => 63.875,CLKIN1_PERIOD => 5.0)
430  port map (
431  -- Feedback Clocks: 1-bit (each) Clock feedback ports
432  CLKFBOUT => TTC_clkfb, -- 1-bit Feedback clock output
433  CLKOUT0 => TTC_clk_dcm, -- 1-bit CLKOUT0 output 400MHz
434  -- Clock Inputs: 1-bit (each) Clock inputs
435  CLKIN1 => refclk, -- 1-bit Clock input
436  -- Control Ports: 1-bit (each) MMCM control ports
437  PWRDWN => '0', -- 1-bit Power-down input
438  RST => sys_lock_n, -- 1-bit Reset input
439  LOCKED => TTC_clk_lock, -- 1-bit LOCK output
440  -- Feedback Clocks: 1-bit (each) Clock feedback ports
441  CLKFBIN => TTC_clkfb -- 1-bit Feedback clock input
442  );
443  sys_lock_n <= not sys_lock;
444  i_PLL_TTC_clk : PLLE2_BASE
445  generic map(CLKFBOUT_MULT => 64,CLKOUT0_DIVIDE => 8,CLKIN1_PERIOD => 49.902)
446  port map (
447  CLKOUT0 => clk160_dcm,
448  CLKFBOUT => clkfb, -- 1-bit Feedback clock output
449  -- Clock Inputs: 1-bit (each) Clock inputs
450  CLKIN1 => TTC_clk_dcm, -- 1-bit Clock input
451  -- Control Ports: 1-bit (each) MMCM control ports
452  PWRDWN => '0', -- 1-bit Power-down input
453  RST => TTC_clk_lock_n , -- 1-bit Reset input
454  LOCKED => open, -- 1-bit LOCK output
455  -- Feedback Clocks: 1-bit (each) Clock feedback ports
456  CLKFBIN => clkfb -- 1-bit Feedback clock input
457  );
458  TTC_clk_lock_n <= not TTC_clk_lock;
459 end generate g_TTCCLK;
460 g_TTCCLK160: if (flavor = "G2") generate
461  i_TTCclk160 : PLLE2_BASE
462  generic map(CLKFBOUT_MULT => 8,CLKOUT0_DIVIDE => 10,CLKIN1_PERIOD => 5.0)
463  port map (
464  CLKOUT0 => clk160_dcm,
465  CLKFBOUT => clkfb, -- 1-bit Feedback clock output
466  -- Clock Inputs: 1-bit (each) Clock inputs
467  CLKIN1 => refclk, -- 1-bit Clock input
468  -- Control Ports: 1-bit (each) MMCM control ports
469  PWRDWN => '0', -- 1-bit Power-down input
470  RST => sys_lock_n, -- 1-bit Reset input
471  LOCKED => open, -- 1-bit LOCK output
472  -- Feedback Clocks: 1-bit (each) Clock feedback ports
473  CLKFBIN => clkfb -- 1-bit Feedback clock input
474  );
475 end generate g_TTCCLK160;
476  i_TTS_clk_buf : BUFGCTRL
477  generic map (
478  INIT_OUT => 0, -- Initial value of BUFGCTRL output (0/1)
479  PRESELECT_I0 => FALSE, -- BUFGCTRL output uses I0 input (TRUE/FALSE)
480  PRESELECT_I1 => FALSE -- BUFGCTRL output uses I1 input (TRUE/FALSE)
481  )
482  port map (
483  O => TTS_clk, -- 1-bit output: Clock Output pin
484  CE0 => '1', -- 1-bit input: Clock enable input for I0 input
485  CE1 => '1', -- 1-bit input: Clock enable input for I1 input
486  I0 => clk200_dcm, -- 1-bit input: Primary clock input
487  I1 => clk160_dcm, -- 1-bit input: Secondary clock input
488  IGNORE0 => '1', -- 1-bit input: Clock ignore input for I0
489  IGNORE1 => '1', -- 1-bit input: Clock ignore input for I1
490  S0 => local_TTC_n, -- 1-bit input: Clock select input for I0
491  S1 => local_TTC -- 1-bit input: Clock select input for I1
492  );
493  local_TTC_n <= not local_TTC;
494  i_CDRdata: ibufds generic map(DIFF_TERM => TRUE,IOSTANDARD => "LVDS_25") port map(i => CDRdata_p, ib => CDRdata_n, o => CDRdata);
495  i_TTCdata: obufds generic map(IOSTANDARD => "LVDS_25") port map(o => TTCdata_p, ob => TTCdata_n, i => TTCdata);
496  DIV4 <= '1';
497  process(CDRclk)
498  begin
499  if(CDRclk'event and CDRclk = '0')then
500  CDRdata_q(0) <= CDRdata;
501  end if;
502  end process;
503  process(CDRclk)
504  begin
505  if(CDRclk'event and CDRclk = '1')then
506  ovfl_warning_SyncRegs <= ovfl_warning_SyncRegs(2 downto 0) & ovfl_warning;
507 -- CDRdata_q <= CDRdata_q(0) & CDRdata;
508  CDRdata_q(2 downto 1) <= CDRdata_q(1 downto 0);
509  if(toggle_channel = '1')then
510  if(a_channel = '1' and en_localL1A = '1')then
511  TTCdata <= TTCdata_pol xor (not ovfl_warning_SyncRegs(3) and periodicL1A);
512  elsif(a_channel = '0' and local_TTCcmd = '1')then
513  TTCdata <= TTCdata_pol xor sr_l(40);
514  else
515  TTCdata <= TTCdata_pol xor (CDRdata_q(1) xor CDRdata_q(2));
516  end if;
517  end if;
518  if(toggle_channel = '0')then
519  div8 <= div8 + 1;
520  end if;
521  if(div8 = "111" or toggle_cnt = "11")then
522  toggle_cnt <= (others => '0');
523 -- TTC signal should always toggle at a/b channel crossing, otherwise toggle_channel is at wrong position
524  elsif(CDRdata_q(1) = CDRdata_q(2) and toggle_channel = '0')then
525  toggle_cnt <= toggle_cnt + 1;
526  end if;
527  if(toggle_cnt /= "11")then
528  toggle_channel <= not toggle_channel;
529  end if;
530 -- if illegal L1A='1'/data = '0' sequence reaches 11, resync the phase
531  if(toggle_channel = '1' and (a_channel = '1' or strng_length /= x"b"))then
532  a_channel <= not a_channel;
533  end if;
534  if(a_channel = '1' and toggle_channel = '1')then
535  if(CDRdata_q(1) /= CDRdata_q(2))then
536  L1A <= '1';
537  else
538  L1A <= '0';
539  end if;
540  end if;
541  if(a_channel = '0' and toggle_channel = '1')then
542 -- L1A = '1' and b_channel data = '0' can not repeat 11 times
543  if(L1A = '0' or CDRdata_q(1) /= CDRdata_q(2) or strng_length = x"b")then
544  strng_length <= (others => '0');
545  else
546  strng_length <= strng_length + 1;
547  end if;
548  end if;
549  end if;
550  end process;
551 -- To get the right phase of TTC clock, we do not directly look at the divided clock signal.
552 -- Instead, phase of the divided TTC clock is determined by the time of release of the signal div_nrst
553  process(CDRclk,CDR_lock)
554  begin
555  if(CDR_lock = '0')then
556  div_nrst <= '0';
557  div_rst_cnt <= (others => '0');
558  elsif(CDRclk'event and CDRclk = '1')then
559  if(TTC_str = '1')then
560  div_nrst <= div_rst_cnt(4);
561  end if;
562  if(toggle_cnt = "11" or strng_length = x"b")then
563  div_rst_cnt <= (others => '0');
564  elsif(TTC_str = '1' and div_rst_cnt(4) = '0')then
565  div_rst_cnt <= div_rst_cnt + 1;
566  end if;
567  end if;
568  end process;
569  process(CDRclk)
570  begin
571  if(CDRclk'event and CDRclk = '0')then
572  for i in 0 to 3 loop
573  NoPrescale(i) <= not or_reduce(TTC_cmd_cfg(i)(15 downto 0));
574  end loop;
575  end if;
576  end process;
577  process(CDRclk,reset)
578  begin
579  if(reset = '1')then
580  TTC_tune_cnt <= (others => '0');
581  OcPrescal <= (others => x"ffff");
582  SendTTC_cmd <= x"0";
583  elsif(CDRclk'event and CDRclk = '1')then
584  if(toggle_cnt = "11" or strng_length = x"b")then
585  TTC_tune_cnt <= TTC_tune_cnt + 1;
586  end if;
587  if(TTC_str = '1')then
588  for i in 0 to 3 loop
589  if(TTC_cmd_done(i) = '1')then
590  SendTTC_cmd(i) <= '0';
591  elsif(single_TTCcmd_SyncRegs(3 downto 2) = "01" and TTC_cmd_cfg(i)(30) = '1')then
592  SendTTC_cmd(i) <= '1';
593  elsif(Bcnt_l = x"002" and TTC_cmd_cfg(i)(29) = '1')then
594  if(OcPrescal(i) = x"ffff" or NoPrescale(i) = '1')then
595  OcPrescal(i) <= not TTC_cmd_cfg(i)(15 downto 0);
596  SendTTC_cmd(i) <= TTC_cmd_cfg(i)(29);
597  else
598  OcPrescal(i) <= OcPrescal(i) + 1;
599  end if;
600  end if;
601  end loop;
602  end if;
603  end if;
604  end process;
605  i_SCRAMBLER: SCRAMBLER PORT MAP(
606  UNSCRAMBLED_DATA_IN => lfsr,
607  SCRAMBLED_DATA_OUT => lfsr_s(31 downto 0),
608  DATA_VALID_IN => TTC_str,
609  USER_CLK => CDRclk,
610  SYSTEM_RESET => reset_SyncRegs (3)
611  );
612  process(CDRclk)
613  begin
614  if(CDRclk'event and CDRclk = '1')then
615 -- 2 1 3 2 1 4 1 3 6 1 1 13 8 5 1 1 1
616 --TTC_debug <= "000000000" & CDRdata_q & toggle_channel & div8 & toggle_cnt & a_channel & strng_length & TTC_str & TTC_data & rec_cntr & rec_cmd & FMT & sr & brcst_data & brcst_syn & frame_err & single_err & double_err;
617  if(toggle_channel = '1' and a_channel = '0')then
618  TTC_data(2) <= CDRdata_q(1) xor CDRdata_q(2);
619  end if;
620  TTC_str <= not toggle_channel and a_channel;
621  if(TTC_str = '1')then
622 -- locally generated TTC commands
623  reset_SyncRegs <= reset_SyncRegs(2 downto 0) & reset;
624  EvnRst_SyncRegs <= EvnRst_SyncRegs(2 downto 0) & EvnRst_l;
625  OcnRst_SyncRegs <= OcnRst_SyncRegs(2 downto 0) & OcnRst_l;
626 -- if(Bcnt_l = x"deb")then
627  if(Bcnt_l = LastBcnt)then
628  Bcnt_l <= (others => '0');
629  else
630  Bcnt_l <= Bcnt_l + 1;
631  end if;
632 -- if(Bcnt_l = x"de8")then
633  if(Bcnt_l = (LastBcnt - x"003"))then
634  Bcnt_cmd <= (others => '0');
635  else
636  Bcnt_cmd <= Bcnt_cmd + 1;
637  end if;
638  if(busy_l = '0' and SendBC0 = '1')then
639  busy_l <= '1';
640  ld_sr_l <= '1';
641  SendFMT <= '0';
642  cmd_cntr <= "110010";
643  SendCmdData(7 downto 0) <= "000000" & SendEvnRst & SendBC0;
644  elsif(busy_l = '0' and SendOcnRst = '1' and Bcnt_l(9) = '1')then -- this keeps OcNreset away from BC0
645  busy_l <= '1';
646  ld_sr_l <= '1';
647  SendFMT <= '0';
648  cmd_cntr <= "110010";
649 -- SendCmdData <= x"000000" & OcNresetCmd(7 downto 2) & '0' & SendBC0;
650  SendCmdData(7 downto 0) <= OcNresetCmd(7 downto 2) & "00";
651  elsif(busy_l = '0')then
652  for i in 0 to 3 loop
653  if(SendTTC_cmd(i) = '1' and Bcnt_cmd = TTC_cmd_cfg(i)(27 downto 16))then
654  busy_l <= '1';
655  ld_sr_l <= '1';
656  SendFMT <= TTC_cmd_cfg(i)(28);
657  if(TTC_cmd_cfg(i)(28) = '0')then
658  cmd_cntr <= "110010";
659  else
660  cmd_cntr <= "011000";
661  end if;
662  SendCmdData <= TTC_cmd(i);
663  TTC_cmd_done(i) <= '1';
664  end if;
665  end loop;
666  else
667  if(stop_l = '1')then
668  busy_l <= '0';
669  end if;
670  ld_sr_l <= '0';
671  TTC_cmd_done <= (others => '0');
672  cmd_cntr <= cmd_cntr + 1;
673  end if;
674 -- if(busy_l = '0')then
675 -- if(SendFMT = '0')then
676 -- cmd_cntr <= "110010";
677 -- else
678 -- cmd_cntr <= "011000";
679 -- end if;
680 -- else
681 -- cmd_cntr <= cmd_cntr + 1;
682 -- end if;
683  if(cmd_cntr = "111111")then
684  stop_l <= '1';
685  else
686  stop_l <= '0';
687  end if;
688  if(flavor /= "G2" or reset_SyncRegs(3) = '1')then
689  en_SendBc0 <= '1';
690  elsif(stop_l = '1' and SendFMT = '0' and SendCmdData(0) = '1')then
691  en_SendBc0 <= '0';
692  end if;
693 -- if(Bcnt_l = x"dd2")then
694 -- if(Bcnt_l = (LastBcnt - x"019") and flavor /= "G2")then
695  if(Bcnt_l = (LastBcnt - x"019") and en_SendBC0 = '1')then
696  SendBC0 <= '1';
697  else
698  SendBC0 <= '0';
699  end if;
700  if(reset_SyncRegs(3 downto 2) = "10" or EvnRst_SyncRegs(3 downto 2) = "01")then
701  SendEvnRst <= '1';
702  elsif(busy_l = '0' and SendBC0 = '1')then
703  SendEvnRst <= '0';
704  end if;
705 -- if(reset_SyncRegs(3 downto 2) = "10" or OcnRst_SyncRegs(3 downto 2) = "01")then
706  if(OcnRst_SyncRegs(3 downto 2) = "01")then
707  SendOcnRst <= '1';
708 -- elsif(busy_l = '0' and SendBC0 = '1')then
709  elsif(busy_l = '0' and Bcnt_l(9) = '1')then -- this keeps OcNreset away from BC0
710  SendOcnRst <= '0';
711  end if;
712  if(ld_sr_l = '1')then
713  start_l <= '1';
714  if(SendFMT = '0')then
715  sr_l(40 downto 26) <= "00" & SendCmdData(7 downto 0) & hemming_s(SendCmdData(7 downto 0));
716  sr_l(25 downto 0) <= (others => '1');
717  else
718  sr_l <= "01" & SendCmdData & hemming_l(SendCmdData);
719  end if;
720  else
721  start_l <= '0';
722  sr_l <= sr_l(39 downto 0) & '1';
723  end if;
724 -- locally generated TTC commands
725  localL1A_s_SyncRegs <= localL1A_s_SyncRegs(2 downto 0) & localL1A_s;
726  localL1A_r_SyncRegs <= localL1A_r_SyncRegs(2 downto 0) & localL1A_r;
727  T3_triggerSyncRegs <= T3_triggerSyncRegs(2 downto 0) & T3_trigger;
728  single_TTCcmd_SyncRegs <= single_TTCcmd_SyncRegs(2 downto 0) & single_TTCcmd;
729 -- if(local_TTC = '0')then
730 -- BC0 <= BCntRes;
731 -- elsif(Bcnt_l = x"deb")then
732 -- BC0 <= '1';
733 -- else
734 -- BC0 <= '0';
735 -- end if;
736 -- TTC_data(1) <= TTC_data(2) or not div_rst_cnt(4);
737  BC0 <= BCntRes;
738  if(div_rst_cnt(4) = '0')then
739  TTC_data(0) <= '0';
740  elsif(en_localL1A = '0')then
741  TTC_data(0) <= CDRdata_q(1) xor CDRdata_q(2);
742  else
743  TTC_data(0) <= not ovfl_warning_SyncRegs(3) and periodicL1A;
744  end if;
745  if(div_rst_cnt(4) = '0')then
746  TTC_data(1) <= '1';
747  elsif(local_TTCcmd = '0')then
748  TTC_data(1) <= TTC_data(2);
749  else
750  TTC_data(1) <= sr_l(40);
751  end if;
752  if(rec_cmd = '0')then
753  rec_cntr <= (others => '0');
754  else
755  rec_cntr <= rec_cntr + 1;
756  end if;
757  if(div_rst_cnt(4) = '0' or rec_cntr(5 downto 3) = "101" or (FMT = '0' and rec_cntr(3 downto 0) = x"d"))then
758  rec_cmd <= '0';
759  elsif(TTC_data(1) = '0')then
760  rec_cmd <= '1';
761  end if;
762  if(or_reduce(rec_cntr) = '0')then
763  FMT <= TTC_data(1);
764  end if;
765  sr <= sr(11 downto 0) & TTC_data(1);
766  if(FMT = '0' and rec_cntr(3 downto 0) = x"e")then
767  brcst_data <= sr(12 downto 5);
768  brcst_syn(0) <= sr(0) xor sr(5) xor sr(6) xor sr(7) xor sr(8);
769  brcst_syn(1) <= sr(1) xor sr(5) xor sr(9) xor sr(10) xor sr(11);
770  brcst_syn(2) <= sr(2) xor sr(6) xor sr(7) xor sr(9) xor sr(10) xor sr(12);
771  brcst_syn(3) <= sr(3) xor sr(6) xor sr(8) xor sr(9) xor sr(11) xor sr(12);
772  brcst_syn(4) <= xor_reduce(sr);
773  frame_err <= not TTC_data(1);
774  brcst_str(0) <= '1';
775  else
776  brcst_str(0) <= '0';
777  end if;
778  single_err <= xor_reduce(brcst_syn) and not frame_err;
779  if((or_reduce(brcst_syn) = '1' and xor_reduce(brcst_syn) = '0') or frame_err = '1')then
780  double_err <= '1';
781  else
782  double_err <= '0';
783  end if;
784  SinErrStr <= single_err and brcst_str(1);
785  DbErrStr <= double_err and brcst_str(1);
786  brcst_str(2) <= brcst_str(1) and not double_err;
787  if(brcst_syn(3 downto 0) = x"c")then
788  Brcst(7) <= not brcst_data(7);
789  else
790  Brcst(7) <= brcst_data(7);
791  end if;
792  if(brcst_syn(3 downto 0) = x"a")then
793  Brcst(6) <= not brcst_data(6);
794  else
795  Brcst(6) <= brcst_data(6);
796  end if;
797  if(brcst_syn(3 downto 0) = x"6")then
798  Brcst(5) <= not brcst_data(5);
799  else
800  Brcst(5) <= brcst_data(5);
801  end if;
802  if(brcst_syn(3 downto 0) = x"e")then
803  Brcst(4) <= not brcst_data(4);
804  else
805  Brcst(4) <= brcst_data(4);
806  end if;
807  if(brcst_syn(3 downto 0) = x"9")then
808  Brcst(3) <= not brcst_data(3);
809  else
810  Brcst(3) <= brcst_data(3);
811  end if;
812  if(brcst_syn(3 downto 0) = x"5")then
813  Brcst(2) <= not brcst_data(2);
814  else
815  Brcst(2) <= brcst_data(2);
816  end if;
817  if(brcst_syn(3 downto 0) = x"d")then
818  Brcst(1) <= not brcst_data(1);
819  else
820  Brcst(1) <= brcst_data(1);
821  end if;
822  if(brcst_syn(3 downto 0) = x"3")then
823  Brcst(0) <= not brcst_data(0);
824  else
825  Brcst(0) <= brcst_data(0);
826  end if;
827  if(en_burst = '0' or reset = '1')then
828  Burst_cntr <= LocalL1A_cfg(27 downto 16);
829  elsif(periodicL1A = '1')then
830  Burst_cntr <= Burst_cntr - 1;
831  end if;
832  if(en_localL1A = '0' or reset = '1')then
833  en_periodic <= '0';
834  elsif(localL1A_s_SyncRegs(3 downto 2) = "01")then
835  en_periodic <= '1';
836  elsif(localL1A_r_SyncRegs(3 downto 2) = "01")then
837  en_periodic <= '0';
838  end if;
839  if(en_localL1A = '0' or en_periodic = '1')then
840  en_burst <= '0';
841  elsif(localL1A_r_SyncRegs(3 downto 2) = "01")then
842  en_burst <= '1';
843  elsif(periodicL1A = '1' and or_reduce(Burst_cntr) = '0')then
844  en_burst <= '0';
845  end if;
846  if(BCntRes = '1')then
847  BXCntr <= (others => '0');
848  else
849  BXCntr <= BXCntr + 1;
850  end if;
851  if(en_periodic = '0' and en_burst = '0')then
852  BXCntr_b <= LocalL1A_cfg(15 downto 0);
853  elsif(BXCntr_b = LocalL1A_cfg(15 downto 0) or LocalL1A_cfg(31 downto 30) /= "10")then
854  BXCntr_b <= (others => '0');
855  else
856  BXCntr_b <= BXCntr_b + 1;
857  end if;
858  if(BXCntr_b = LocalL1A_cfg(15 downto 0) and LocalL1A_cfg(31 downto 30) = "10" and (en_periodic = '1' or en_burst = '1'))then
859  periodicL1A_a <= '1';
860  else
861  periodicL1A_a <= '0';
862  end if;
863  if(random_th > lfsr_s and LocalL1A_cfg(31 downto 30) = "11" and (en_periodic = '1' or en_burst = '1'))then
864  periodicL1A_b <= '1';
865  else
866  periodicL1A_b <= '0';
867  end if;
868  if(reset_SyncRegs(3) = '1' or in_gap = '1')then
869  random_cnt <= (others => '0');
870  elsif(and_reduce(random_cnt) = '0' and periodicL1A_b = '1' and (and_reduce(rules) = '0' or or_reduce(random_cnt) = '0'))then
871  random_cnt <= random_cnt + 1;
872  elsif(or_reduce(random_cnt) = '1' and periodicL1A_b = '0' and and_reduce(rules) = '1')then
873  random_cnt <= random_cnt - 1;
874  end if;
875 -- every_orbit <= not or_reduce(LocalL1A_cfg(15 downto 0));
876 -- if(BCntRes = '1')then
877 -- if(NextL1A = '1' or every_orbit = '1' or (en_periodic = '0' and en_burst = '0'))then
878 -- orbitCntr <= LocalL1A_cfg(15 downto 0);
879 -- else
880 -- orbitCntr <= orbitCntr - 1;
881 -- end if;
882 -- end if;
883  if(en_periodic = '0' and en_burst = '0')then
884  orbitCntr <= (others => '0');
885  elsif(BXCntr = BX500(11 downto 0))then
886  if(NextL1A = '1')then
887  orbitCntr <= LocalL1A_cfg(15 downto 0);
888  else
889  orbitCntr <= orbitCntr - 1;
890  end if;
891  end if;
892 -- if(orbitCntr = LocalL1A_cfg(15 downto 0) and LocalL1A_cfg(31) = '0' and (en_periodic = '1' or en_burst = '1'))then
893  if(or_reduce(orbitCntr) = '0' and LocalL1A_cfg(31) = '0' and (en_periodic = '1' or en_burst = '1'))then
894  NextL1A <= '1';
895  else
896  NextL1A <= '0';
897  end if;
898  if(gap_beginp = gap_endp or BXCntr = gap_endp)then
899  in_gap <= '0';
900  elsif(BXCntr = gap_beginp)then
901  in_gap <= '1';
902  end if;
903 -- if(T3_triggerSyncRegs(3 downto 2) = "01" or (HCAL_trigger = '1' and en_localL1A = '1'))then
904  if(T3_triggerSyncRegs(3 downto 2) = "01")then
905  periodicL1A <= '1';
906 -- elsif(en_periodic = '0' and en_burst = '0')then
907 -- periodicL1A <= '0';
908 -- elsif(((BXCntr = BX500 and NextL1A = '1') or periodicL1A_a = '1' or periodicL1A_bp = '1') and and_reduce(rules) = '1')then
909  elsif(((BXCntr = BX500(11 downto 0) and NextL1A = '1') or periodicL1A_a = '1' or periodicL1A_bp = '1' or ((HCAL_trigger = '1' or TTC_L1A_Do(0) = '1') and en_localL1A = '1')) and and_reduce(rules) = '1')then
910  periodicL1A <= '1';
911  else
912  periodicL1A <= '0';
913  end if;
914  L1A_dl <= periodicL1A;
915  if(L1A_dl = '1' or (en_periodic = '0' and en_burst = '0'))then
916  rules(0) <= '1';
917 -- elsif((periodicL1A_a = '1' or periodicL1A_bp = '1') and and_reduce(rules) = '1')then
918  elsif((periodicL1A_a = '1' or periodicL1A_bp = '1' or (HCAL_trigger = '1' and en_localL1A = '1')) and and_reduce(rules) = '1')then
919  rules(0) <= '0';
920  end if;
921  rule1_cntr <= rule1_cntr xor periodicL1A xor L1A_dl24(21);
922  if(L1A_dl24(21) = '1' or (en_periodic = '0' and en_burst = '0') or LocalL1A_cfg(29 downto 28) = "11")then
923  rules(1) <= '1';
924 -- elsif(((periodicL1A_a = '1' or periodicL1A_bp = '1') and and_reduce(rules) = '1') and rule1_cntr = '1')then
925  elsif(((periodicL1A_a = '1' or periodicL1A_bp = '1' or (HCAL_trigger = '1' and en_localL1A = '1')) and and_reduce(rules) = '1') and rule1_cntr = '1')then
926  rules(1) <= '0';
927  end if;
928  if(periodicL1A = '1' and L1A_dl99(74) = '0')then
929  rule2_cntr(1) <= rule2_cntr(1) xor rule2_cntr(0);
930  rule2_cntr(0) <= not rule2_cntr(0);
931  elsif(periodicL1A = '0' and L1A_dl99(74) = '1')then
932  rule2_cntr(1) <= rule2_cntr(1) xnor rule2_cntr(0);
933  rule2_cntr(0) <= not rule2_cntr(0);
934  end if;
935  if(L1A_dl99(74) = '1' or (en_periodic = '0' and en_burst = '0') or LocalL1A_cfg(28) = '1')then
936  rules(2) <= '1';
937 -- elsif(((periodicL1A_a = '1' or periodicL1A_bp = '1') and and_reduce(rules) = '1') and rule2_cntr(1) = '1')then
938  elsif(((periodicL1A_a = '1' or periodicL1A_bp = '1' or (HCAL_trigger = '1' and en_localL1A = '1')) and and_reduce(rules) = '1') and rule2_cntr(1) = '1')then
939  rules(2) <= '0';
940  end if;
941  if(periodicL1A = '1' and L1A_dl239(139) = '0')then
942  rule3_cntr(1) <= rule3_cntr(1) xor rule3_cntr(0);
943  rule3_cntr(0) <= not rule3_cntr(0);
944  elsif(periodicL1A = '0' and L1A_dl239(139) = '1')then
945  rule3_cntr(1) <= rule3_cntr(1) xnor rule3_cntr(0);
946  rule3_cntr(0) <= not rule3_cntr(0);
947  end if;
948  if(L1A_dl239(139) = '1' or (en_periodic = '0' and en_burst = '0') or LocalL1A_cfg(29 downto 28) /= "00")then
949  rules(3) <= '1';
950 -- elsif(((periodicL1A_a = '1' or periodicL1A_bp = '1') and and_reduce(rules) = '1') and rule3_cntr = "11")then
951  elsif(((periodicL1A_a = '1' or periodicL1A_bp = '1' or (HCAL_trigger = '1' and en_localL1A = '1')) and and_reduce(rules) = '1') and rule3_cntr = "11")then
952  rules(3) <= '0';
953  end if;
954  rules(4) <= not in_gap;
955  L1A_dl24 <= L1A_dl24(20 downto 0) & L1A_dl;
956  L1A_dl99 <= L1A_dl99(73 downto 0) & L1A_dl24(21);
957  L1A_dl239 <= L1A_dl239(138 downto 0) & L1A_dl99(74);
958  BCntRes <= brcst_str(3) and Brcst(0);
959  EvCntRes <= brcst_str(3) and Brcst(1);
960  BrcstStr <= brcst_str(3) and or_reduce(Brcst);
961  OcRes <= brcst_str(3) and and_reduce((Brcst xnor OcNresetCmd(7 downto 0)) or OcNresetCmd(15 downto 8));
962  ReSync <= brcst_str(3) and and_reduce((Brcst xnor ReSyncCmd(7 downto 0)) or ReSyncCmd(15 downto 8));
963  DB <= DB xor (brcst_str(3) and and_reduce((Brcst xnor DBCmd(7 downto 0)) or DBCmd(15 downto 8)));
964  if(brcst_str(3) = '1')then
965  BrcstCmd <= Brcst(7 downto 5) & Brcst(3);
966  end if;
967  if(LocalL1A_cfg(31 downto 30) /= "11")then
968  lfsr <= (others => '0');
969  else
970  lfsr <= lfsr(30 downto 0) & not(lfsr(31) xor lfsr(21) xor lfsr(1) xor lfsr(0));
971  end if;
972  if(L1Accept = '1')then
973  L1AToggle <= not L1AToggle;
974  end if;
975  end if;
976  end if;
977  end process;
978  periodicL1A_bp <= or_reduce(random_cnt);
979 --rules(4) <= not in_gap;
980  i_Threshold: Threshold PORT MAP(
981  clk => ipb_clk,
982  din => LocalL1A_cfg(15 downto 0),
983  nongap_size => nongap_size,
984  dout => random_th(31 downto 0)
985  );
986  nongap_size <= gap_begin - gap_end when gap_end < gap_begin else gap_begin - gap_end + x"dec";
987  i_L1Accept : SRL16E
988  port map (
989  Q => L1Accept, -- SRL data output
990  A0 => Coarse_Delay(0), -- Select[0] input
991  A1 => Coarse_Delay(1), -- Select[1] input
992  A2 => Coarse_Delay(2), -- Select[2] input
993  A3 => Coarse_Delay(3), -- Select[3] input
994  CE => TTC_str, -- Clock enable input
995  CLK => CDRclk, -- Clock input
996  D => TTC_data(0) -- SRL data input
997  );
998  i_brcst_str1 : SRL16E
999  port map (
1000  Q => brcst_str(1), -- SRL data output
1001  A0 => '1', -- Select[0] input
1002  A1 => '0', -- Select[1] input
1003  A2 => '0', -- Select[2] input
1004  A3 => '0', -- Select[3] input
1005  CE => TTC_str, -- Clock enable input
1006  CLK => CDRclk, -- Clock input
1007  D => brcst_str(0) -- SRL data input
1008  );
1009  i_brcst_str3 : SRL16E
1010  port map (
1011  Q => brcst_str(3), -- SRL data output
1012  A0 => Coarse_Delay(0), -- Select[0] input
1013  A1 => Coarse_Delay(1), -- Select[1] input
1014  A2 => Coarse_Delay(2), -- Select[2] input
1015  A3 => Coarse_Delay(3), -- Select[3] input
1016  CE => TTC_str, -- Clock enable input
1017  CLK => CDRclk, -- Clock input
1018  D => brcst_str(2) -- SRL data input
1019  );
1020 -- old ttc_if code
1021  event_number_avl <= event_number_avl_i;
1022  inc_l1ac <= ttc_l1accept_dl;
1023  inc_serr <= ttc_sinerrstr;
1024  inc_derr <= ttc_dberrstr;
1025  ttc_ready <= CDR_lock;
1026  TTC_brcst <= ttc_brcst_i;
1027  CalType <= cal_type;
1028  process(CDRclk)
1029  begin
1030  if(CDRclk'event and CDRclk = '1')then
1031 -- ttc_sync_din(10) <= BrcstStr and not Brcst(7) and not Brcst(6) and Brcst(5) and Brcst(3);
1032  if(TTC_str = '1')then
1033 -- if(and_reduce((Brcst xnor OcNresetCmd(7 downto 0)) or OcNresetCmd(15 downto 8)) = '1' and BrcstStr = '1')then
1034 -- ttc_sync_din(10) <= '1';
1035 -- else
1036 -- ttc_sync_din(10) <= '0';
1037 -- end if;
1038  ttc_sync_din(11) <= ReSync;
1039  ttc_sync_din(10) <= OcRes;
1040  ttc_sync_din(9) <= SinErrStr;
1041  ttc_sync_din(8) <= DbErrStr;
1042  ttc_sync_din(7) <= L1Accept;
1043  ttc_sync_din(6) <= BCntRes;
1044  ttc_sync_din(5) <= EvCntRes;
1045  ttc_sync_din(4) <= BrcstStr;
1046  ttc_sync_din(3 downto 0) <= BrcstCmd;
1047  ttc_sync_wa(1 downto 0) <= ttc_sync_wa(0) & not ttc_sync_wa(1);
1048  end if;
1049  end if;
1050  end process;
1051  g_ttc_sync : for i in 0 to 11 generate
1052  i_ttc_sync : RAM32X1D
1053  port map (
1054  DPO => ttc_sync_dout(i), -- Read-only 1-bit data output
1055  A0 => ttc_sync_wa(0), -- R/W address[0] input bit
1056  A1 => ttc_sync_wa(1), -- R/W address[1] input bit
1057  A2 => '0', -- R/W address[2] input bit
1058  A3 => '0', -- R/W address[3] input bit
1059  A4 => '0', -- R/W address[4] input bit
1060  D => ttc_sync_din(i), -- Write 1-bit data input
1061  DPRA0 => ttc_sync_ra(0), -- Read-only address[0] input bit
1062  DPRA1 => ttc_sync_ra(1), -- Read-only address[1] input bit
1063  DPRA2 => '0', -- Read-only address[2] input bit
1064  DPRA3 => '0', -- Read-only address[3] input bit
1065  DPRA4 => '0', -- Read-only address[4] input bit
1066  WCLK => CDRclk, -- Write clock input
1067  WE => TTC_str -- Write enable input
1068  );
1069  end generate;
1070  process(clk)
1071  begin
1072  if(clk'event and clk = '1')then
1073  ttc_sync_wa1_SyncRegs <= ttc_sync_wa1_SyncRegs(0) & ttc_sync_wa(1);
1074  ttc_sync_wa0_SyncRegs <= ttc_sync_wa0_SyncRegs(0) & ttc_sync_wa(0);
1075  if(ttc_sync_wa1_SyncRegs(1) /= ttc_sync_ra(1) or ttc_sync_wa0_SyncRegs(1) /= ttc_sync_ra(0))then
1076  ttc_sync_ra(1 downto 0) <= ttc_sync_ra(0) & not ttc_sync_ra(1);
1077  ttc_sync_do_val <= '1';
1078  else
1079  ttc_sync_do_val <= '0';
1080  end if;
1081  ttc_sync_do <= ttc_sync_dout;
1082  end if;
1083  end process;
1084  process(clk)
1085  begin
1086  if(clk'event and clk = '1')then
1087  if(ttc_sync_do_val = '0')then
1088  ttc_soft_reset_i <= '0';
1089  ttc_OCres_dl <= '0';
1090  ttc_sinerrstr <= '0';
1091  ttc_dberrstr <= '0';
1092  ttc_l1accept_dl <= '0';
1093  ttc_evcnt_reset <= '0';
1094  ttc_brcst_i <= x"0";
1095  else
1096  ttc_soft_reset_i <= ttc_sync_do(11);
1097  ttc_OCres_dl <= ttc_sync_do(10);
1098  ttc_sinerrstr <= ttc_sync_do(9);
1099  ttc_dberrstr <= ttc_sync_do(8);
1100  ttc_l1accept_dl <= ttc_sync_do(7);
1101  ttc_evcnt_reset <= ttc_sync_do(5);
1102  if(ttc_sync_do(4) = '1')then
1103  ttc_brcst_i <= ttc_sync_do(3 downto 0);
1104  else
1105  ttc_brcst_i <= x"0";
1106  end if;
1107  end if;
1108  if(ttc_sync_do_val = '1')then
1109  if(flavor /= "G2" or local_TTC = '1')then
1110  ttc_bcntres_dl <= ttc_sync_do(6);
1111  else
1112  ttc_bcntres_dl <= ttc_sync_do(10);
1113  end if;
1114  if(bcnt = (LastBcnt - 1))then
1115  rst_bcnt <= '1';
1116 -- elsif(flavor = "G2" and bcnt = x"ffe")then
1117 -- rst_bcnt <= '1';
1118  else
1119  rst_bcnt <= '0';
1120  end if;
1121  end if;
1122  if(ttc_sync_do_val = '1')then
1123  if(ttc_bcntres_dl = '1' and en_bcnt_res = '1')then
1124  if(flavor = "G2")then
1125  bcnt <= x"000";
1126  else
1127  bcnt <= bcn_off(11 downto 0);
1128  end if;
1129 -- elsif(rst_bcnt = '1')then
1130  elsif(bcnt = LastBcnt)then
1131  bcnt <= x"000";
1132  else
1133  bcnt <= bcnt + 1;
1134  end if;
1135  end if;
1136  if(ttc_OCres_dl = '1')then
1137  oc <= x"0000000" & OC_off;
1138  elsif(rst_bcnt = '1' and ttc_sync_do_val = '1')then
1139  oc <= oc + 1;
1140  end if;
1141  inc_oc <= ttc_bcntres_dl and ttc_sync_do_val;
1142  if(bcnt = cal_win_low and en_cal_win = '1')then
1143  cal_win <= '1';
1144  elsif(bcnt(5 downto 0) = cal_win_high(5 downto 0))then
1145  cal_win <= '0';
1146  end if;
1147  if(bcn_off(11 downto 0) = x"000" or flavor = "G2")then
1148  bcn_offs1 <= LastBcnt;
1149  else
1150  bcn_offs1 <= bcn_off(11 downto 0) - 1;
1151  end if;
1152  if(reset = '1' or CDR_lock = '0')then -- modified for dsp_chip301f
1153  en_bcnt_err <= "00";
1154  elsif(rst_bcnt = '1' and ttc_sync_do_val = '1')then
1155  en_bcnt_err <= en_bcnt_err(0) & '1';
1156  end if;
1157  if(reset = '1')then
1158  inc_bcnterr <= '0';
1159  ttc_bcnt_err <= '0';
1160 -- cs_trig(0) <= '0';
1161  elsif(((ttc_bcntres_dl = '1' and bcnt /= bcn_offs1) or (ttc_bcntres_dl = '0' and bcnt = bcn_offs1 and flavor /= "G2")) and en_bcnt_err(1) = '1' and ttc_sync_do_val = '1')then
1162  inc_bcnterr <= '1';
1163  ttc_bcnt_err <= '1';
1164 -- cs_trig(0) <= '1';
1165  else
1166  inc_bcnterr <= '0';
1167 -- cs_trig(0) <= '0';
1168  end if;
1169 -- if(ttc_brcst_i = x"7" or ttc_brcst_i = x"5")then
1170 -- ttc_soft_reset <= en_brcst;
1171 -- else
1172 -- ttc_soft_reset <= '0';
1173 -- end if;
1174  if(ttc_brcst_i = x"9")then
1175  ttc_start <= en_brcst;
1176  else
1177  ttc_start <= '0';
1178  end if;
1179  if(ttc_brcst_i = x"b")then
1180  ttc_stop <= en_brcst;
1181  else
1182  ttc_stop <= '0';
1183  end if;
1184  if(ttc_brcst_i = x"4")then
1185  brcst_GapTrig <= '1';
1186  elsif(rst_bcnt = '1')then
1187  brcst_GapTrig <= '0';
1188  end if;
1189  if(ttc_brcst_i = x"6")then
1190  brcst_GapPed <= '1';
1191  elsif(rst_bcnt = '1')then
1192  brcst_GapPed <= '0';
1193  end if;
1194  if(ttc_brcst_i = x"8")then
1195  brcst_GapLaser <= '1';
1196  else
1197  brcst_GapLaser <= '0';
1198  end if;
1199  if(ttc_OCres_dl = '1')then
1200  cal_type <= x"0";
1201  elsif(brcst_GapLaser = '1')then
1202  if(Laser_TO(13) = '1')then
1203  cal_type <= x"1";
1204  elsif(cal_type /= x"f")then
1205  cal_type <= cal_type + 1;
1206  end if;
1207  end if;
1208  if(brcst_GapLaser = '1')then
1209  Laser_To <= (others => '0');
1210  elsif(Laser_TO(13) = '0' and ttc_bcntres_dl = '1' and ttc_sync_do_val = '1')then
1211  Laser_To <= Laser_To + 1;
1212  end if;
1213  end if;
1214  end process;
1215  process(clk)
1216  begin
1217  if(clk'event and clk = '1')then
1218  if(reset = '1')then
1219  en_bcnt_res <= '1';
1220  elsif(ttc_bcntres_dl = '1' and bcn_off(12) = '1' and ttc_sync_do_val = '1')then
1221  en_bcnt_res <= '0';
1222  end if;
1223  end if;
1224  end process;
1225  process(clk)
1226  begin
1227  if(clk'event and clk = '1')then
1228  if(reset = '1')then
1229  ttc_serr <= '0';
1230  ttc_derr <= '0';
1231  rate_div <= (others => '0');
1232  rate_cntr <= "000010";
1233  rate_OFW <= '0';
1234  else
1235  if(ttc_sinerrstr = '1')then
1236  ttc_serr <= '1';
1237  end if;
1238  if(ttc_dberrstr = '1')then
1239  ttc_derr <= '1';
1240  end if;
1241  if(ttc_sync_do_val = '1')then
1242  if(rate_div(7 downto 6) = "11" and rate_div(3) = '1')then
1243  dec_rate_cntr <= '1';
1244  rate_div <= (others => '0');
1245  else
1246  dec_rate_cntr <= '0';
1247  rate_div <= rate_div + 1;
1248  end if;
1249  if(dec_rate_cntr /= ttc_sync_do(7))then
1250  if(ttc_sync_do(7) = '1')then
1251  rate_cntr <= rate_cntr + 1;
1252  elsif(rate_cntr /= "000010")then
1253  rate_cntr <= rate_cntr - 1;
1254  end if;
1255  end if;
1256  end if;
1257  if(rate_cntr(5) = '1')then
1258  rate_OFW <= '1';
1259  elsif(rate_cntr(4) = '0')then
1260  rate_OFW <= '0';
1261  end if;
1262  end if;
1263  end if;
1264  end process;
1265  process(clk)
1266  begin
1267  if(clk'event and clk = '1')then
1268  if(reset = '1')then
1269  event_number_avl_i <= '0';
1270  else
1271  event_number_avl_i <= ttc_l1accept_dl and run and not IgnoreDAQ;
1272  end if;
1273 -- if(en_cal_win = '0')then
1274 -- event_number(51 downto 48) <= x"0";
1275 -- event_number(44) <= '0';
1276 -- else
1277  event_number(51) <= cal_win and brcst_GapTrig and cal_type(3) and not brcst_GapPed;
1278  event_number(50) <= cal_win and brcst_GapTrig and cal_type(2) and not brcst_GapPed;
1279  event_number(49) <= cal_win and brcst_GapTrig and cal_type(1) and not brcst_GapPed;
1280  event_number(48) <= cal_win and ((brcst_GapTrig and cal_type(0)) or brcst_GapPed);
1281  event_number(44) <= cal_win and (brcst_GapTrig or brcst_GapPed);
1282 -- end if;
1283  event_number(59 downto 56) <= cal_type;
1284  event_number(55 downto 52) <= state;
1285  event_number(47) <= brcst_GapTrig;
1286  event_number(46) <= brcst_GapPed;
1287  event_number(45) <= cal_win;
1288  event_number(43 downto 0) <= oc & bcnt;
1289  end if;
1290  end process;
1291  process(clk)
1292  begin
1293  if(clk'event and clk = '1')then
1294 -- if(reset = '1' or ttc_soft_reset_i = '1')then
1295  if(reset = '1')then
1296  sync_lost <= '0';
1297  elsif(evn_fifo_full = '1' and event_number_avl_i = '1')then
1298  sync_lost <= '1';
1299  end if;
1300  end if;
1301  end process;
1302  process(ipb_clk)
1303  begin
1304  if(ipb_clk'event and ipb_clk = '1')then
1305  DBSync <= DBSync(2 downto 0) & DB;
1306  if(flavor = "G2")then
1307  DB_cmd_i <= '0';
1308  elsif(DBSync(3) /= DBSync(2) or DB_cmd_in = '1')then
1309  DB_cmd_i <= '1';
1310  else
1311  DB_cmd_i <= '0';
1312  end if;
1313  if(DB_cmd_i = '1')then
1314  L1A_rate_q <= L1A_rate;
1315  end if;
1316  if(ipb_strobe = '1' and ipb_write = '1' and ipb_addr(15 downto 4) = x"002" and ipb_addr(27) = '0')then
1317  case ipb_addr(3 downto 0) is
1318  when x"0" => ttc_cmd(0) <= ipb_wdata(31 downto 0);
1319  when x"1" => ttc_cmd(1) <= ipb_wdata(31 downto 0);
1320  when x"2" => ttc_cmd(2) <= ipb_wdata(31 downto 0);
1321  when x"3" => ttc_cmd(3) <= ipb_wdata(31 downto 0);
1322  when x"4" => ttc_cmd_cfg(0) <= ipb_wdata(31 downto 0);
1323  when x"5" => ttc_cmd_cfg(1) <= ipb_wdata(31 downto 0);
1324  when x"6" => ttc_cmd_cfg(2) <= ipb_wdata(31 downto 0);
1325  when x"7" => ttc_cmd_cfg(3) <= ipb_wdata(31 downto 0);
1326  when x"8" => gap_begin <= ipb_wdata(11 downto 0);
1327  when x"9" => gap_end <= ipb_wdata(11 downto 0);
1328  when x"a" => OcNresetCmd <= ipb_wdata(15 downto 0);
1329  when x"b" => ReSyncCmd <= ipb_wdata(15 downto 0);
1330  when x"d" => DBCmd <= ipb_wdata(15 downto 0);
1331  when x"e" => L1A_delay <= ipb_wdata(11 downto 0);
1332  when others => NULL;
1333  end case;
1334  end if;
1335  L1AToggleSync <= L1AToggleSync(2 downto 0) & L1AToggle;
1336  if(second(25) = '1')then
1337  L1A_cntr <= (others => '0');
1338  second <= "00001000110010100110101111";
1339  L1A_rate <= L1A_cntr;
1340  else
1341  if(L1AToggleSync(3) /= L1AToggleSync(2))then
1342  L1A_cntr <= L1A_cntr + 1;
1343  end if;
1344  second <= second + 1;
1345  end if;
1346  BX500 <= trig_BX - 3;
1347  if(BX500(12) = '1')then
1348  BX500 <= BX500 + x"dec";
1349  end if;
1350  end if;
1351  end process;
1352 --ipb_ack <= '0' when ipb_addr(27) = '1' or ipb_addr(15 downto 4) /= x"002" or ipb_write = '1' else ipb_strobe;
1353  process(ipb_addr)
1354  begin
1355  if(ipb_addr(14 downto 4) /= "00000000010")then
1356  ipb_rdata <= (others => '0');
1357  else
1358  case ipb_addr(3 downto 0) is
1359  when x"0" => ipb_rdata <= ttc_cmd(0);
1360  when x"1" => ipb_rdata <= ttc_cmd(1);
1361  when x"2" => ipb_rdata <= ttc_cmd(2);
1362  when x"3" => ipb_rdata <= ttc_cmd(3);
1363  when x"4" => ipb_rdata <= ttc_cmd_cfg(0);
1364  when x"5" => ipb_rdata <= ttc_cmd_cfg(1);
1365  when x"6" => ipb_rdata <= ttc_cmd_cfg(2);
1366  when x"7" => ipb_rdata <= ttc_cmd_cfg(3);
1367  when x"8" => ipb_rdata <= x"00000" & gap_begin;
1368  when x"9" => ipb_rdata <= x"00000" & gap_end;
1369  when x"a" => ipb_rdata <= x"0000" & OcNresetCmd;
1370  when x"b" => ipb_rdata <= x"0000" & ReSyncCmd;
1371  when x"c" =>
1372  if(ipb_addr(15) = '0')then
1373  ipb_rdata <= "0000000" & L1A_rate;
1374  else
1375  ipb_rdata <= "0000000" & L1A_rate_q;
1376  end if;
1377  when x"d" => ipb_rdata <= x"0000" & DBCmd;
1378  when x"e" => ipb_rdata <= x"00000" & L1A_delay;
1379  when others => ipb_rdata <= (others => '0');
1380  end case;
1381  end if;
1382  end process;
1383  gap_beginp <= gap_begin - 5 when gap_begin > 4 else gap_begin + x"de7";
1384  gap_endp <= gap_end - 5 when gap_end > 4 else gap_end + x"de7";
1385  process(CDRclk)
1386  begin
1387  if(CDRclk'event and CDRclk = '1')then
1388  if(TTC_str = '1')then
1389  TTC_L1A_wa <= TTC_L1A_wa + 1;
1390  if(TTC_L1A_wa = L1A_delay)then
1391  TTC_L1A_ra <= (others => '0');
1392  else
1393  TTC_L1A_ra <= TTC_L1A_ra + 1;
1394  end if;
1395  if(cmd_cntr = "111100")then
1396  en_TTC_L1A <= '0';
1397  TTC_L1A_Di(0) <= en_TTC_L1A;
1398  else
1399  for i in 0 to 3 loop
1400  if(TTC_cmd_cfg(i)(31) = '1' and TTC_cmd_done(i) = '1')then
1401  en_TTC_L1A <= '1';
1402  end if;
1403  end loop;
1404  TTC_L1A_Di(0) <= '0';
1405  end if;
1406  end if;
1407  end if;
1408  end process;
1409 i_TTC_L1A : BRAM_SDP_MACRO
1410  generic map (
1411  BRAM_SIZE => "18Kb", -- Target BRAM, "18Kb" or "36Kb"
1412  DEVICE => "7SERIES", -- Target device: "VIRTEX5", "VIRTEX6", "7SERIES", "SPARTAN6"
1413  WRITE_WIDTH => 4, -- Valid values are 1-72 (37-72 only valid when BRAM_SIZE="36Kb")
1414  READ_WIDTH => 4) -- Valid values are 1-72 (37-72 only valid when BRAM_SIZE="36Kb")
1415  port map (
1416  DO => TTC_L1A_Do, -- Output read data port, width defined by READ_WIDTH parameter
1417  DI => TTC_L1A_Di, -- Input write data port, width defined by WRITE_WIDTH parameter
1418  RDADDR => TTC_L1A_ra, -- Input read address, width defined by read port depth
1419  RDCLK => CDRclk, -- 1-bit input read clock
1420  RDEN => TTC_str, -- 1-bit input read port enable
1421  REGCE => '1', -- 1-bit input read output register enable
1422  RST => '0', -- 1-bit input reset
1423  WE => "1", -- Input write enable, width defined by write port depth
1424  WRADDR => TTC_L1A_wa, -- Input write address, width defined by write port depth
1425  WRCLK => CDRclk, -- 1-bit input write clock
1426  WREN => TTC_str -- 1-bit input write port enable
1427  );
1428 end ttc_arch;
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