ttc_arch Architecture Reference

List of all members.

Functions
std_logic_vector	hemming_s ( d: in std_logic_vector ( 7 downto 0 ) )
std_logic_vector	hemming_l ( d: in std_logic_vector ( 31 downto 0 ) )
real	CDRclk_period ( A: in string )

Processes
PROCESS_879	( CDRclk )
PROCESS_880	( CDRclk )
PROCESS_881	( CDRclk ,CDR_lock )
PROCESS_882	( CDRclk )
PROCESS_883	( CDRclk ,reset )
PROCESS_884	( CDRclk )
PROCESS_885	( CDRclk )
PROCESS_886	( clk )
PROCESS_887	( clk )
PROCESS_888	( clk )
PROCESS_889	( clk )
PROCESS_890	( clk )
PROCESS_891	( clk )
PROCESS_892	( ipb_clk )
PROCESS_893	( ipb_addr )
PROCESS_894	( CDRclk )

Components
SCRAMBLER	<Entity SCRAMBLER>
Threshold	<Entity Threshold>
icon1
ila36x1024

Constants
TTCclk_pol	std_logic := ' 1 '
TTCdata_pol	std_logic := ' 1 '
Coarse_Delay	std_logic_vector ( 3 downto 0 ) := x " 0 "

Types
array4X16	array ( 0 to 3 ) of std_logic_vector ( 15 downto 0 )
array4X32	array ( 0 to 3 ) of std_logic_vector ( 31 downto 0 )

Signals
BX500	std_logic_vector ( 12 downto 0 )
ovfl_warning_SyncRegs	std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
en_periodic	std_logic := ' 0 '
en_burst	std_logic := ' 0 '
NextL1A	std_logic := ' 0 '
periodicL1A_a	std_logic := ' 0 '
periodicL1A_b	std_logic := ' 0 '
periodicL1A_bp	std_logic := ' 0 '
periodicL1A	std_logic := ' 0 '
Burst_cntr	std_logic_vector ( 11 downto 0 ) := ( others = > ' 0 ' )
L1A_dl	std_logic := ' 0 '
L1A_dl24	std_logic_vector ( 21 downto 0 ) := ( others = > ' 0 ' )
L1A_dl99	std_logic_vector ( 74 downto 0 ) := ( others = > ' 0 ' )
L1A_dl239	std_logic_vector ( 139 downto 0 ) := ( others = > ' 0 ' )
random_th	std_logic_vector ( 32 downto 0 ) := ( others = > ' 0 ' )
lfsr	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
lfsr_s	std_logic_vector ( 32 downto 0 ) := ( others = > ' 0 ' )
rules	std_logic_vector ( 4 downto 0 ) := ( others = > ' 0 ' )
rule1_cntr	std_logic := ' 0 '
rule2_cntr	std_logic_vector ( 1 downto 0 ) := ( others = > ' 0 ' )
rule3_cntr	std_logic_vector ( 1 downto 0 ) := ( others = > ' 0 ' )
OrbitCntr	std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
BXCntr	std_logic_vector ( 11 downto 0 ) := ( others = > ' 0 ' )
BXCntr_b	std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
localL1A_s_SyncRegs	std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
localL1A_r_SyncRegs	std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
T3_triggerSyncRegs	std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
EvnRst_SyncRegs	std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
OcnRst_SyncRegs	std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
reset_SyncRegs	std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
SendEvnRst	std_logic := ' 0 '
SendOcnRst	std_logic := ' 0 '
SendBC0	std_logic := ' 0 '
en_SendBC0	std_logic := ' 0 '
TTC_cmd_avl	std_logic := ' 0 '
busy_l	std_logic := ' 0 '
start_l	std_logic := ' 0 '
stop_l	std_logic := ' 0 '
Bcnt_l	std_logic_vector ( 11 downto 0 ) := ( others = > ' 0 ' )
sr_l	std_logic_vector ( 40 downto 0 ) := ( others = > ' 0 ' )
TTC_clkfb	std_logic := ' 0 '
TTC_clk_dcm	std_logic := ' 0 '
TTC_clk_lock	std_logic := ' 0 '
TTC_clk_lock_n	std_logic := ' 0 '
clkfb	std_logic := ' 0 '
clk160_dcm	std_logic := ' 0 '
clk200_dcm	std_logic := ' 0 '
sys_lock_n	std_logic := ' 0 '
local_TTC_n	std_logic := ' 0 '
rst_CDR	std_logic := ' 0 '
CDRclk_in	std_logic := ' 0 '
PllCDRclk_in	std_logic := ' 0 '
CDRclk_dcm	std_logic := ' 0 '
CDRclkFB_dcm	std_logic := ' 0 '
CDRclkFB	std_logic := ' 0 '
CDRclk	std_logic := ' 0 '
CDR_lock	std_logic := ' 0 '
TTCdata	std_logic := ' 0 '
CDRdata_in	std_logic := ' 0 '
TTCclk_q	std_logic_vector ( 1 downto 0 ) := ( others = > ' 0 ' )
CDRdata	std_logic := ' 0 '
CDRdata_q	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
div8	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
toggle_cnt	std_logic_vector ( 1 downto 0 ) := ( others = > ' 0 ' )
toggle_channel	std_logic := ' 1 '
a_channel	std_logic := ' 1 '
L1A	std_logic := ' 0 '
strng_length	std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
div_rst_cnt	std_logic_vector ( 4 downto 0 ) := ( others = > ' 0 ' )
TTC_str	std_logic := ' 0 '
L1Accept	std_logic := ' 0 '
sr	std_logic_vector ( 12 downto 0 ) := ( others = > ' 0 ' )
rec_cntr	std_logic_vector ( 5 downto 0 ) := ( others = > ' 0 ' )
rec_cmd	std_logic := ' 0 '
FMT	std_logic := ' 0 '
TTC_data	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
brcst_str	std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
brcst_data	std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
brcst_syn	std_logic_vector ( 4 downto 0 ) := ( others = > ' 0 ' )
frame_err	std_logic := ' 0 '
single_err	std_logic := ' 0 '
double_err	std_logic := ' 0 '
EvCntReset	std_logic := ' 0 '
BCntReset	std_logic := ' 0 '
SinErrStr	std_logic := ' 0 '
DbErrStr	std_logic := ' 0 '
BrcstStr	std_logic := ' 0 '
EvCntRes	std_logic := ' 0 '
BCntRes	std_logic := ' 0 '
OcRes	std_logic := ' 0 '
ReSync	std_logic := ' 0 '
BrcstCmd	std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
Brcst	std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
TTC_tune_cnt	std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
ttc_brcst_i	std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
ttc_sinerrstr	std_logic := ' 0 '
ttc_dberrstr	std_logic := ' 0 '
ttc_l1accept	std_logic := ' 0 '
ttc_evcntres	std_logic := ' 0 '
ttc_l1accept_dl	std_logic := ' 0 '
ttc_bcntres_dl	std_logic := ' 0 '
ttc_OCres_dl	std_logic := ' 0 '
ttc_soft_reset_i	std_logic := ' 0 '
dl_a	std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
dl_b	std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
bcnt	std_logic_vector ( 11 downto 0 ) := ( others = > ' 0 ' )
LastBcnt	std_logic_vector ( 11 downto 0 ) := ( others = > ' 0 ' )
oc	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
en_bcnt_res	std_logic := ' 0 '
en_bcnt_err	std_logic_vector ( 1 downto 0 ) := ( others = > ' 0 ' )
brcst_GapTrig	std_logic := ' 0 '
brcst_GapPed	std_logic := ' 0 '
brcst_GapLaser	std_logic := ' 0 '
rst_bcnt	std_logic := ' 0 '
cal_win	std_logic := ' 0 '
Laser_TO	std_logic_vector ( 13 downto 0 ) := ( others = > ' 0 ' )
bcn_offs1	std_logic_vector ( 11 downto 0 ) := ( others = > ' 0 ' )
cal_type	std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
rst_cnt	std_logic_vector ( 1 downto 0 ) := ( others = > ' 0 ' )
event_number_avl_i	std_logic := ' 0 '
dec_rate_cntr	std_logic := ' 0 '
rate_div	std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
rate_cntr	std_logic_vector ( 5 downto 0 ) := ( others = > ' 0 ' )
ttc_sync_wa	std_logic_vector ( 1 downto 0 ) := ( others = > ' 0 ' )
ttc_sync_ra	std_logic_vector ( 1 downto 0 ) := ( others = > ' 0 ' )
ttc_sync_din	std_logic_vector ( 11 downto 0 ) := ( others = > ' 0 ' )
ttc_sync_dout	std_logic_vector ( 11 downto 0 ) := ( others = > ' 0 ' )
ttc_sync_wa1_SyncRegs	std_logic_vector ( 1 downto 0 ) := ( others = > ' 0 ' )
ttc_sync_wa0_SyncRegs	std_logic_vector ( 1 downto 0 ) := ( others = > ' 0 ' )
ttc_sync_do	std_logic_vector ( 11 downto 0 ) := ( others = > ' 0 ' )
ttc_sync_do_val	std_logic := ' 0 '
ttc_cmd	array4x32 := ( others = > ( others = > ' 0 ' ) )
ttc_cmd_cfg	array4x32 := ( others = > ( others = > ' 0 ' ) )
single_TTCcmd_SyncRegs	std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
OcPrescal	array4x16 := ( others = >x " ffff " )
NoPrescale	std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
L1A_delay	std_logic_vector ( 11 downto 0 ) := ( others = > ' 0 ' )
SendTTC_cmd	std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
TTC_cmd_done	std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
TTC_L1A_Do	std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
TTC_L1A_Di	std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
TTC_L1A_wa	std_logic_vector ( 11 downto 0 ) := ( others = > ' 0 ' )
TTC_L1A_ra	std_logic_vector ( 11 downto 0 ) := ( others = > ' 0 ' )
en_TTC_L1A	std_logic := ' 0 '
ld_sr_l	std_logic := ' 0 '
SendFMT	std_logic := ' 0 '
SendCmdData	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
hmg_s	std_logic_vector ( 4 downto 0 ) := ( others = > ' 0 ' )
hmg_l	std_logic_vector ( 6 downto 0 ) := ( others = > ' 0 ' )
cmd_cntr	std_logic_vector ( 5 downto 0 ) := ( others = > ' 0 ' )
bcnt_cmd	std_logic_vector ( 11 downto 0 ) := x " 000 "
gap_begin	std_logic_vector ( 11 downto 0 ) := x " 000 "
gap_end	std_logic_vector ( 11 downto 0 ) := x " 000 "
gap_beginp	std_logic_vector ( 11 downto 0 ) := x " 000 "
gap_endp	std_logic_vector ( 11 downto 0 ) := x " 000 "
nongap_size	std_logic_vector ( 11 downto 0 ) := x " 000 "
in_gap	std_logic := ' 0 '
random_cnt	std_logic_vector ( 5 downto 0 ) := ( others = > ' 0 ' )
OcNresetCmd	std_logic_vector ( 15 downto 0 ) := x " 1728 "
ReSyncCmd	std_logic_vector ( 15 downto 0 ) := x " 1748 "
DBCmd	std_logic_vector ( 15 downto 0 ) := x " 1768 "
second	std_logic_vector ( 25 downto 0 ) := ( others = > ' 0 ' )
L1A_rate	std_logic_vector ( 24 downto 0 ) := ( others = > ' 0 ' )
L1A_rate_q	std_logic_vector ( 24 downto 0 ) := ( others = > ' 0 ' )
L1A_cntr	std_logic_vector ( 24 downto 0 ) := ( others = > ' 0 ' )
L1AToggle	std_logic := ' 0 '
L1AToggleSync	std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
DB	std_logic := ' 0 '
DB_cmd_i	std_logic := ' 0 '
DBSync	std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
CONTROL0	std_logic_vector ( 35 downto 0 ) := ( others = > ' 0 ' )
cs_data	std_logic_vector ( 35 downto 0 ) := ( others = > ' 0 ' )
cs_trig	std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )

Instantiations
i_SCRAMBLER	SCRAMBLER <Entity SCRAMBLER>
i_Threshold	Threshold <Entity Threshold>

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Detailed Description

Definition at line 114 of file ttc_if.vhd.

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The documentation for this class was generated from the following files:

• src/common/TTC/ttc_if.vhd