AMC13
Firmwares for the different applications of the AMC13 uTCA board made at Boston University
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sfp3_v2_7_init.vhd
1 ------------------------------------------------------------------------------
2 -- ____ ____
3 -- / /\/ /
4 -- /___/ \ / Vendor: Xilinx
5 -- \ \ \/ Version : 2.7
6 -- \ \ Application : 7 Series FPGAs Transceivers Wizard
7 -- / / Filename : sfp3_v2_7_init.vhd
8 -- /___/ /\
9 -- \ \ / \
10 -- \___\/\___\
11 --
12 -- Description : This module instantiates the modules required for
13 -- reset and initialisation of the Transceiver
14 --
15 -- Module SFP3_v2_7_init
16 -- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
17 --
18 --
19 -- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
20 --
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64 
65 
66 library ieee;
67 use ieee.std_logic_1164.all;
68 use ieee.numeric_std.all;
69 use ieee.std_logic_unsigned.all;
70 use work.amc13_pack.all;
71 library UNISIM;
72 use UNISIM.VCOMPONENTS.ALL;
73 
74 --***********************************Entity Declaration************************
75 
76 entity SFP3_v2_7_init is
77 generic
78 (
79  EXAMPLE_SIM_GTRESET_SPEEDUP : string := "TRUE"; -- simulation setting for GT SecureIP model
80  EXAMPLE_SIMULATION : integer := 0; -- Set to 1 for simulation
81  STABLE_CLOCK_PERIOD : integer := 20; --Period of the stable clock driving this state-machine, unit is [ns]
82  EXAMPLE_USE_CHIPSCOPE : integer := 0 -- Set to 1 to use Chipscope to drive resets
83 
84 );
85 port
86 (
87  SYSCLK_IN : in std_logic;
88  SOFT_RESET_IN : in std_logic;
89  DONT_RESET_ON_DATA_ERROR_IN : in std_logic;
90  GT0_TX_FSM_RESET_DONE_OUT : out std_logic;
91  GT0_RX_FSM_RESET_DONE_OUT : out std_logic;
92  GT0_DATA_VALID_IN : in std_logic;
93  GT1_TX_FSM_RESET_DONE_OUT : out std_logic;
94  GT1_RX_FSM_RESET_DONE_OUT : out std_logic;
95  GT1_DATA_VALID_IN : in std_logic;
96  GT2_TX_FSM_RESET_DONE_OUT : out std_logic;
97  GT2_RX_FSM_RESET_DONE_OUT : out std_logic;
98  GT2_DATA_VALID_IN : in std_logic;
99 
100  --_________________________________________________________________________
101  --GT0 (X1Y12)
102  --____________________________CHANNEL PORTS________________________________
103  ---------------------------- Channel - DRP Ports --------------------------
104  GT0_DRPADDR_IN : in std_logic_vector(8 downto 0);
105  GT0_DRPCLK_IN : in std_logic;
106  GT0_DRPDI_IN : in std_logic_vector(15 downto 0);
107  GT0_DRPDO_OUT : out std_logic_vector(15 downto 0);
108  GT0_DRPEN_IN : in std_logic;
109  GT0_DRPRDY_OUT : out std_logic;
110  GT0_DRPWE_IN : in std_logic;
111  ------------------------------- Loopback Ports -----------------------------
112  GT0_LOOPBACK_IN : in std_logic_vector(2 downto 0);
113  ------------------------------ Power-Down Ports ----------------------------
114  GT0_RXPD_IN : in std_logic_vector(1 downto 0);
115  GT0_TXPD_IN : in std_logic_vector(1 downto 0);
116  --------------------- RX Initialization and Reset Ports --------------------
117  GT0_RXUSERRDY_IN : in std_logic;
118  -------------------------- RX Margin Analysis Ports ------------------------
119  GT0_EYESCANDATAERROR_OUT : out std_logic;
120  ------------------------- Receive Ports - CDR Ports ------------------------
121  GT0_RXCDRLOCK_OUT : out std_logic;
122  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
123  GT0_RXUSRCLK_IN : in std_logic;
124  GT0_RXUSRCLK2_IN : in std_logic;
125  ------------------ Receive Ports - FPGA RX interface Ports -----------------
126  GT0_RXDATA_OUT : out std_logic_vector(31 downto 0);
127  ------------------- Receive Ports - Pattern Checker Ports ------------------
128  GT0_RXPRBSERR_OUT : out std_logic;
129  GT0_RXPRBSSEL_IN : in std_logic_vector(2 downto 0);
130  ------------------- Receive Ports - Pattern Checker ports ------------------
131  GT0_RXPRBSCNTRESET_IN : in std_logic;
132  --------------------------- Receive Ports - RX AFE -------------------------
133  GT0_GTXRXP_IN : in std_logic;
134  ------------------------ Receive Ports - RX AFE Ports ----------------------
135  GT0_GTXRXN_IN : in std_logic;
136  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
137  GT0_RXBUFRESET_IN : in std_logic;
138  GT0_RXBUFSTATUS_OUT : out std_logic_vector(2 downto 0);
139  --------------- Receive Ports - RX Fabric Output Control Ports -------------
140  GT0_RXOUTCLK_OUT : out std_logic;
141  ---------------------- Receive Ports - RX Gearbox Ports --------------------
142  GT0_RXDATAVALID_OUT : out std_logic;
143  GT0_RXHEADER_OUT : out std_logic_vector(1 downto 0);
144  GT0_RXHEADERVALID_OUT : out std_logic;
145  --------------------- Receive Ports - RX Gearbox Ports --------------------
146  GT0_RXGEARBOXSLIP_IN : in std_logic;
147  ------------- Receive Ports - RX Initialization and Reset Ports ------------
148  GT0_GTRXRESET_IN : in std_logic;
149  GT0_RXPMARESET_IN : in std_logic;
150  ------------------ Receive Ports - RX Margin Analysis ports ----------------
151  GT0_RXLPMEN_IN : in std_logic;
152  -------------- Receive Ports -RX Initialization and Reset Ports ------------
153  GT0_RXRESETDONE_OUT : out std_logic;
154  --------------------- TX Initialization and Reset Ports --------------------
155  GT0_GTTXRESET_IN : in std_logic;
156  GT0_TXUSERRDY_IN : in std_logic;
157  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
158  GT0_TXUSRCLK_IN : in std_logic;
159  GT0_TXUSRCLK2_IN : in std_logic;
160  --------------- Transmit Ports - TX Configurable Driver Ports --------------
161  GT0_TXDIFFCTRL_IN : in std_logic_vector(3 downto 0);
162  GT0_TXINHIBIT_IN : in std_logic;
163  GT0_TXMAINCURSOR_IN : in std_logic_vector(6 downto 0);
164  ------------------ Transmit Ports - TX Data Path interface -----------------
165  GT0_TXDATA_IN : in std_logic_vector(31 downto 0);
166  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
167  GT0_GTXTXN_OUT : out std_logic;
168  GT0_GTXTXP_OUT : out std_logic;
169  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
170  GT0_TXOUTCLK_OUT : out std_logic;
171  GT0_TXOUTCLKFABRIC_OUT : out std_logic;
172  GT0_TXOUTCLKPCS_OUT : out std_logic;
173  --------------------- Transmit Ports - TX Gearbox Ports --------------------
174  GT0_TXHEADER_IN : in std_logic_vector(1 downto 0);
175  GT0_TXSEQUENCE_IN : in std_logic_vector(6 downto 0);
176  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
177  GT0_TXRESETDONE_OUT : out std_logic;
178  ------------------ Transmit Ports - pattern Generator Ports ----------------
179  GT0_TXPRBSSEL_IN : in std_logic_vector(2 downto 0);
180 
181  --GT1 (X1Y13)
182  --____________________________CHANNEL PORTS________________________________
183  ---------------------------- Channel - DRP Ports --------------------------
184  GT1_DRPADDR_IN : in std_logic_vector(8 downto 0);
185  GT1_DRPCLK_IN : in std_logic;
186  GT1_DRPDI_IN : in std_logic_vector(15 downto 0);
187  GT1_DRPDO_OUT : out std_logic_vector(15 downto 0);
188  GT1_DRPEN_IN : in std_logic;
189  GT1_DRPRDY_OUT : out std_logic;
190  GT1_DRPWE_IN : in std_logic;
191  ------------------------------- Loopback Ports -----------------------------
192  GT1_LOOPBACK_IN : in std_logic_vector(2 downto 0);
193  ------------------------------ Power-Down Ports ----------------------------
194  GT1_RXPD_IN : in std_logic_vector(1 downto 0);
195  GT1_TXPD_IN : in std_logic_vector(1 downto 0);
196  --------------------- RX Initialization and Reset Ports --------------------
197  GT1_RXUSERRDY_IN : in std_logic;
198  -------------------------- RX Margin Analysis Ports ------------------------
199  GT1_EYESCANDATAERROR_OUT : out std_logic;
200  ------------------------- Receive Ports - CDR Ports ------------------------
201  GT1_RXCDRLOCK_OUT : out std_logic;
202  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
203  GT1_RXUSRCLK_IN : in std_logic;
204  GT1_RXUSRCLK2_IN : in std_logic;
205  ------------------ Receive Ports - FPGA RX interface Ports -----------------
206  GT1_RXDATA_OUT : out std_logic_vector(31 downto 0);
207  ------------------- Receive Ports - Pattern Checker Ports ------------------
208  GT1_RXPRBSERR_OUT : out std_logic;
209  GT1_RXPRBSSEL_IN : in std_logic_vector(2 downto 0);
210  ------------------- Receive Ports - Pattern Checker ports ------------------
211  GT1_RXPRBSCNTRESET_IN : in std_logic;
212  --------------------------- Receive Ports - RX AFE -------------------------
213  GT1_GTXRXP_IN : in std_logic;
214  ------------------------ Receive Ports - RX AFE Ports ----------------------
215  GT1_GTXRXN_IN : in std_logic;
216  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
217  GT1_RXBUFRESET_IN : in std_logic;
218  GT1_RXBUFSTATUS_OUT : out std_logic_vector(2 downto 0);
219  --------------- Receive Ports - RX Fabric Output Control Ports -------------
220  GT1_RXOUTCLK_OUT : out std_logic;
221  ---------------------- Receive Ports - RX Gearbox Ports --------------------
222  GT1_RXDATAVALID_OUT : out std_logic;
223  GT1_RXHEADER_OUT : out std_logic_vector(1 downto 0);
224  GT1_RXHEADERVALID_OUT : out std_logic;
225  --------------------- Receive Ports - RX Gearbox Ports --------------------
226  GT1_RXGEARBOXSLIP_IN : in std_logic;
227  ------------- Receive Ports - RX Initialization and Reset Ports ------------
228  GT1_GTRXRESET_IN : in std_logic;
229  GT1_RXPMARESET_IN : in std_logic;
230  ------------------ Receive Ports - RX Margin Analysis ports ----------------
231  GT1_RXLPMEN_IN : in std_logic;
232  -------------- Receive Ports -RX Initialization and Reset Ports ------------
233  GT1_RXRESETDONE_OUT : out std_logic;
234  --------------------- TX Initialization and Reset Ports --------------------
235  GT1_GTTXRESET_IN : in std_logic;
236  GT1_TXUSERRDY_IN : in std_logic;
237  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
238  GT1_TXUSRCLK_IN : in std_logic;
239  GT1_TXUSRCLK2_IN : in std_logic;
240  --------------- Transmit Ports - TX Configurable Driver Ports --------------
241  GT1_TXDIFFCTRL_IN : in std_logic_vector(3 downto 0);
242  GT1_TXINHIBIT_IN : in std_logic;
243  GT1_TXMAINCURSOR_IN : in std_logic_vector(6 downto 0);
244  ------------------ Transmit Ports - TX Data Path interface -----------------
245  GT1_TXDATA_IN : in std_logic_vector(31 downto 0);
246  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
247  GT1_GTXTXN_OUT : out std_logic;
248  GT1_GTXTXP_OUT : out std_logic;
249  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
250  GT1_TXOUTCLK_OUT : out std_logic;
251  GT1_TXOUTCLKFABRIC_OUT : out std_logic;
252  GT1_TXOUTCLKPCS_OUT : out std_logic;
253  --------------------- Transmit Ports - TX Gearbox Ports --------------------
254  GT1_TXHEADER_IN : in std_logic_vector(1 downto 0);
255  GT1_TXSEQUENCE_IN : in std_logic_vector(6 downto 0);
256  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
257  GT1_TXRESETDONE_OUT : out std_logic;
258  ------------------ Transmit Ports - pattern Generator Ports ----------------
259  GT1_TXPRBSSEL_IN : in std_logic_vector(2 downto 0);
260 
261  --GT2 (X1Y14)
262  --____________________________CHANNEL PORTS________________________________
263  ---------------------------- Channel - DRP Ports --------------------------
264  GT2_DRPADDR_IN : in std_logic_vector(8 downto 0);
265  GT2_DRPCLK_IN : in std_logic;
266  GT2_DRPDI_IN : in std_logic_vector(15 downto 0);
267  GT2_DRPDO_OUT : out std_logic_vector(15 downto 0);
268  GT2_DRPEN_IN : in std_logic;
269  GT2_DRPRDY_OUT : out std_logic;
270  GT2_DRPWE_IN : in std_logic;
271  ------------------------------- Loopback Ports -----------------------------
272  GT2_LOOPBACK_IN : in std_logic_vector(2 downto 0);
273  ------------------------------ Power-Down Ports ----------------------------
274  GT2_RXPD_IN : in std_logic_vector(1 downto 0);
275  GT2_TXPD_IN : in std_logic_vector(1 downto 0);
276  --------------------- RX Initialization and Reset Ports --------------------
277  GT2_RXUSERRDY_IN : in std_logic;
278  -------------------------- RX Margin Analysis Ports ------------------------
279  GT2_EYESCANDATAERROR_OUT : out std_logic;
280  ------------------------- Receive Ports - CDR Ports ------------------------
281  GT2_RXCDRLOCK_OUT : out std_logic;
282  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
283  GT2_RXUSRCLK_IN : in std_logic;
284  GT2_RXUSRCLK2_IN : in std_logic;
285  ------------------ Receive Ports - FPGA RX interface Ports -----------------
286  GT2_RXDATA_OUT : out std_logic_vector(31 downto 0);
287  ------------------- Receive Ports - Pattern Checker Ports ------------------
288  GT2_RXPRBSERR_OUT : out std_logic;
289  GT2_RXPRBSSEL_IN : in std_logic_vector(2 downto 0);
290  ------------------- Receive Ports - Pattern Checker ports ------------------
291  GT2_RXPRBSCNTRESET_IN : in std_logic;
292  --------------------------- Receive Ports - RX AFE -------------------------
293  GT2_GTXRXP_IN : in std_logic;
294  ------------------------ Receive Ports - RX AFE Ports ----------------------
295  GT2_GTXRXN_IN : in std_logic;
296  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
297  GT2_RXBUFRESET_IN : in std_logic;
298  GT2_RXBUFSTATUS_OUT : out std_logic_vector(2 downto 0);
299  --------------- Receive Ports - RX Fabric Output Control Ports -------------
300  GT2_RXOUTCLK_OUT : out std_logic;
301  ---------------------- Receive Ports - RX Gearbox Ports --------------------
302  GT2_RXDATAVALID_OUT : out std_logic;
303  GT2_RXHEADER_OUT : out std_logic_vector(1 downto 0);
304  GT2_RXHEADERVALID_OUT : out std_logic;
305  --------------------- Receive Ports - RX Gearbox Ports --------------------
306  GT2_RXGEARBOXSLIP_IN : in std_logic;
307  ------------- Receive Ports - RX Initialization and Reset Ports ------------
308  GT2_GTRXRESET_IN : in std_logic;
309  GT2_RXPMARESET_IN : in std_logic;
310  ------------------ Receive Ports - RX Margin Analysis ports ----------------
311  GT2_RXLPMEN_IN : in std_logic;
312  -------------- Receive Ports -RX Initialization and Reset Ports ------------
313  GT2_RXRESETDONE_OUT : out std_logic;
314  --------------------- TX Initialization and Reset Ports --------------------
315  GT2_GTTXRESET_IN : in std_logic;
316  GT2_TXUSERRDY_IN : in std_logic;
317  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
318  GT2_TXUSRCLK_IN : in std_logic;
319  GT2_TXUSRCLK2_IN : in std_logic;
320  --------------- Transmit Ports - TX Configurable Driver Ports --------------
321  GT2_TXDIFFCTRL_IN : in std_logic_vector(3 downto 0);
322  GT2_TXINHIBIT_IN : in std_logic;
323  GT2_TXMAINCURSOR_IN : in std_logic_vector(6 downto 0);
324  ------------------ Transmit Ports - TX Data Path interface -----------------
325  GT2_TXDATA_IN : in std_logic_vector(31 downto 0);
326  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
327  GT2_GTXTXN_OUT : out std_logic;
328  GT2_GTXTXP_OUT : out std_logic;
329  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
330  GT2_TXOUTCLK_OUT : out std_logic;
331  GT2_TXOUTCLKFABRIC_OUT : out std_logic;
332  GT2_TXOUTCLKPCS_OUT : out std_logic;
333  --------------------- Transmit Ports - TX Gearbox Ports --------------------
334  GT2_TXHEADER_IN : in std_logic_vector(1 downto 0);
335  GT2_TXSEQUENCE_IN : in std_logic_vector(6 downto 0);
336  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
337  GT2_TXRESETDONE_OUT : out std_logic;
338  ------------------ Transmit Ports - pattern Generator Ports ----------------
339  GT2_TXPRBSSEL_IN : in std_logic_vector(2 downto 0);
340 
341 
342  --____________________________COMMON PORTS________________________________
343  ---------------------- Common Block - Ref Clock Ports ---------------------
344  GT0_GTREFCLK0_COMMON_IN : in std_logic;
345  ------------------------- Common Block - QPLL Ports ------------------------
346  GT0_QPLLLOCK_OUT : out std_logic;
347  GT0_QPLLLOCKDETCLK_IN : in std_logic;
348  GT0_QPLLRESET_IN : in std_logic
349 
350 
351 );
352 
353 end SFP3_v2_7_init;
354 
355 architecture RTL of SFP3_v2_7_init is
356 
357 --**************************Component Declarations*****************************
358 
359 
360 component SFP3_v2_7
361 generic
362 (
363  -- Simulation attributes
364  WRAPPER_SIM_GTRESET_SPEEDUP : string := "FALSE" -- Set to 1 to speed up sim reset
365 
366 );
367 port
368 (
369 
370  --_________________________________________________________________________
371  --_________________________________________________________________________
372  --GT0 (X1Y12)
373  --____________________________CHANNEL PORTS________________________________
374  ---------------------------- Channel - DRP Ports --------------------------
375  GT0_DRPADDR_IN : in std_logic_vector(8 downto 0);
376  GT0_DRPCLK_IN : in std_logic;
377  GT0_DRPDI_IN : in std_logic_vector(15 downto 0);
378  GT0_DRPDO_OUT : out std_logic_vector(15 downto 0);
379  GT0_DRPEN_IN : in std_logic;
380  GT0_DRPRDY_OUT : out std_logic;
381  GT0_DRPWE_IN : in std_logic;
382  ------------------------------- Loopback Ports -----------------------------
383  GT0_LOOPBACK_IN : in std_logic_vector(2 downto 0);
384  ------------------------------ Power-Down Ports ----------------------------
385  GT0_RXPD_IN : in std_logic_vector(1 downto 0);
386  GT0_TXPD_IN : in std_logic_vector(1 downto 0);
387  --------------------- RX Initialization and Reset Ports --------------------
388  GT0_RXUSERRDY_IN : in std_logic;
389  -------------------------- RX Margin Analysis Ports ------------------------
390  GT0_EYESCANDATAERROR_OUT : out std_logic;
391  ------------------------- Receive Ports - CDR Ports ------------------------
392  GT0_RXCDRLOCK_OUT : out std_logic;
393  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
394  GT0_RXUSRCLK_IN : in std_logic;
395  GT0_RXUSRCLK2_IN : in std_logic;
396  ------------------ Receive Ports - FPGA RX interface Ports -----------------
397  GT0_RXDATA_OUT : out std_logic_vector(31 downto 0);
398  ------------------- Receive Ports - Pattern Checker Ports ------------------
399  GT0_RXPRBSERR_OUT : out std_logic;
400  GT0_RXPRBSSEL_IN : in std_logic_vector(2 downto 0);
401  ------------------- Receive Ports - Pattern Checker ports ------------------
402  GT0_RXPRBSCNTRESET_IN : in std_logic;
403  --------------------------- Receive Ports - RX AFE -------------------------
404  GT0_GTXRXP_IN : in std_logic;
405  ------------------------ Receive Ports - RX AFE Ports ----------------------
406  GT0_GTXRXN_IN : in std_logic;
407  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
408  GT0_RXBUFRESET_IN : in std_logic;
409  GT0_RXBUFSTATUS_OUT : out std_logic_vector(2 downto 0);
410  --------------------- Receive Ports - RX Equalizer Ports -------------------
411  GT0_RXDFEAGCHOLD_IN : in std_logic;
412  GT0_RXDFELFHOLD_IN : in std_logic;
413  --------------- Receive Ports - RX Fabric Output Control Ports -------------
414  GT0_RXOUTCLK_OUT : out std_logic;
415  ---------------------- Receive Ports - RX Gearbox Ports --------------------
416  GT0_RXDATAVALID_OUT : out std_logic;
417  GT0_RXHEADER_OUT : out std_logic_vector(1 downto 0);
418  GT0_RXHEADERVALID_OUT : out std_logic;
419  --------------------- Receive Ports - RX Gearbox Ports --------------------
420  GT0_RXGEARBOXSLIP_IN : in std_logic;
421  ------------- Receive Ports - RX Initialization and Reset Ports ------------
422  GT0_GTRXRESET_IN : in std_logic;
423  GT0_RXPCSRESET_IN : in std_logic;
424  GT0_RXPMARESET_IN : in std_logic;
425  ------------------ Receive Ports - RX Margin Analysis ports ----------------
426  GT0_RXLPMEN_IN : in std_logic;
427  -------------- Receive Ports -RX Initialization and Reset Ports ------------
428  GT0_RXRESETDONE_OUT : out std_logic;
429  --------------------- TX Initialization and Reset Ports --------------------
430  GT0_GTTXRESET_IN : in std_logic;
431  GT0_TXUSERRDY_IN : in std_logic;
432  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
433  GT0_TXUSRCLK_IN : in std_logic;
434  GT0_TXUSRCLK2_IN : in std_logic;
435  --------------- Transmit Ports - TX Configurable Driver Ports --------------
436  GT0_TXDIFFCTRL_IN : in std_logic_vector(3 downto 0);
437  GT0_TXINHIBIT_IN : in std_logic;
438  GT0_TXMAINCURSOR_IN : in std_logic_vector(6 downto 0);
439  ------------------ Transmit Ports - TX Data Path interface -----------------
440  GT0_TXDATA_IN : in std_logic_vector(31 downto 0);
441  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
442  GT0_GTXTXN_OUT : out std_logic;
443  GT0_GTXTXP_OUT : out std_logic;
444  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
445  GT0_TXOUTCLK_OUT : out std_logic;
446  GT0_TXOUTCLKFABRIC_OUT : out std_logic;
447  GT0_TXOUTCLKPCS_OUT : out std_logic;
448  --------------------- Transmit Ports - TX Gearbox Ports --------------------
449  GT0_TXHEADER_IN : in std_logic_vector(1 downto 0);
450  GT0_TXSEQUENCE_IN : in std_logic_vector(6 downto 0);
451  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
452  GT0_TXPCSRESET_IN : in std_logic;
453  GT0_TXRESETDONE_OUT : out std_logic;
454  ------------------ Transmit Ports - pattern Generator Ports ----------------
455  GT0_TXPRBSSEL_IN : in std_logic_vector(2 downto 0);
456 
457  --_________________________________________________________________________
458  --_________________________________________________________________________
459  --GT1 (X1Y13)
460  --____________________________CHANNEL PORTS________________________________
461  ---------------------------- Channel - DRP Ports --------------------------
462  GT1_DRPADDR_IN : in std_logic_vector(8 downto 0);
463  GT1_DRPCLK_IN : in std_logic;
464  GT1_DRPDI_IN : in std_logic_vector(15 downto 0);
465  GT1_DRPDO_OUT : out std_logic_vector(15 downto 0);
466  GT1_DRPEN_IN : in std_logic;
467  GT1_DRPRDY_OUT : out std_logic;
468  GT1_DRPWE_IN : in std_logic;
469  ------------------------------- Loopback Ports -----------------------------
470  GT1_LOOPBACK_IN : in std_logic_vector(2 downto 0);
471  ------------------------------ Power-Down Ports ----------------------------
472  GT1_RXPD_IN : in std_logic_vector(1 downto 0);
473  GT1_TXPD_IN : in std_logic_vector(1 downto 0);
474  --------------------- RX Initialization and Reset Ports --------------------
475  GT1_RXUSERRDY_IN : in std_logic;
476  -------------------------- RX Margin Analysis Ports ------------------------
477  GT1_EYESCANDATAERROR_OUT : out std_logic;
478  ------------------------- Receive Ports - CDR Ports ------------------------
479  GT1_RXCDRLOCK_OUT : out std_logic;
480  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
481  GT1_RXUSRCLK_IN : in std_logic;
482  GT1_RXUSRCLK2_IN : in std_logic;
483  ------------------ Receive Ports - FPGA RX interface Ports -----------------
484  GT1_RXDATA_OUT : out std_logic_vector(31 downto 0);
485  ------------------- Receive Ports - Pattern Checker Ports ------------------
486  GT1_RXPRBSERR_OUT : out std_logic;
487  GT1_RXPRBSSEL_IN : in std_logic_vector(2 downto 0);
488  ------------------- Receive Ports - Pattern Checker ports ------------------
489  GT1_RXPRBSCNTRESET_IN : in std_logic;
490  --------------------------- Receive Ports - RX AFE -------------------------
491  GT1_GTXRXP_IN : in std_logic;
492  ------------------------ Receive Ports - RX AFE Ports ----------------------
493  GT1_GTXRXN_IN : in std_logic;
494  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
495  GT1_RXBUFRESET_IN : in std_logic;
496  GT1_RXBUFSTATUS_OUT : out std_logic_vector(2 downto 0);
497  --------------------- Receive Ports - RX Equalizer Ports -------------------
498  GT1_RXDFEAGCHOLD_IN : in std_logic;
499  GT1_RXDFELFHOLD_IN : in std_logic;
500  --------------- Receive Ports - RX Fabric Output Control Ports -------------
501  GT1_RXOUTCLK_OUT : out std_logic;
502  ---------------------- Receive Ports - RX Gearbox Ports --------------------
503  GT1_RXDATAVALID_OUT : out std_logic;
504  GT1_RXHEADER_OUT : out std_logic_vector(1 downto 0);
505  GT1_RXHEADERVALID_OUT : out std_logic;
506  --------------------- Receive Ports - RX Gearbox Ports --------------------
507  GT1_RXGEARBOXSLIP_IN : in std_logic;
508  ------------- Receive Ports - RX Initialization and Reset Ports ------------
509  GT1_GTRXRESET_IN : in std_logic;
510  GT1_RXPCSRESET_IN : in std_logic;
511  GT1_RXPMARESET_IN : in std_logic;
512  ------------------ Receive Ports - RX Margin Analysis ports ----------------
513  GT1_RXLPMEN_IN : in std_logic;
514  -------------- Receive Ports -RX Initialization and Reset Ports ------------
515  GT1_RXRESETDONE_OUT : out std_logic;
516  --------------------- TX Initialization and Reset Ports --------------------
517  GT1_GTTXRESET_IN : in std_logic;
518  GT1_TXUSERRDY_IN : in std_logic;
519  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
520  GT1_TXUSRCLK_IN : in std_logic;
521  GT1_TXUSRCLK2_IN : in std_logic;
522  --------------- Transmit Ports - TX Configurable Driver Ports --------------
523  GT1_TXDIFFCTRL_IN : in std_logic_vector(3 downto 0);
524  GT1_TXINHIBIT_IN : in std_logic;
525  GT1_TXMAINCURSOR_IN : in std_logic_vector(6 downto 0);
526  ------------------ Transmit Ports - TX Data Path interface -----------------
527  GT1_TXDATA_IN : in std_logic_vector(31 downto 0);
528  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
529  GT1_GTXTXN_OUT : out std_logic;
530  GT1_GTXTXP_OUT : out std_logic;
531  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
532  GT1_TXOUTCLK_OUT : out std_logic;
533  GT1_TXOUTCLKFABRIC_OUT : out std_logic;
534  GT1_TXOUTCLKPCS_OUT : out std_logic;
535  --------------------- Transmit Ports - TX Gearbox Ports --------------------
536  GT1_TXHEADER_IN : in std_logic_vector(1 downto 0);
537  GT1_TXSEQUENCE_IN : in std_logic_vector(6 downto 0);
538  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
539  GT1_TXPCSRESET_IN : in std_logic;
540  GT1_TXRESETDONE_OUT : out std_logic;
541  ------------------ Transmit Ports - pattern Generator Ports ----------------
542  GT1_TXPRBSSEL_IN : in std_logic_vector(2 downto 0);
543 
544  --_________________________________________________________________________
545  --_________________________________________________________________________
546  --GT2 (X1Y14)
547  --____________________________CHANNEL PORTS________________________________
548  ---------------------------- Channel - DRP Ports --------------------------
549  GT2_DRPADDR_IN : in std_logic_vector(8 downto 0);
550  GT2_DRPCLK_IN : in std_logic;
551  GT2_DRPDI_IN : in std_logic_vector(15 downto 0);
552  GT2_DRPDO_OUT : out std_logic_vector(15 downto 0);
553  GT2_DRPEN_IN : in std_logic;
554  GT2_DRPRDY_OUT : out std_logic;
555  GT2_DRPWE_IN : in std_logic;
556  ------------------------------- Loopback Ports -----------------------------
557  GT2_LOOPBACK_IN : in std_logic_vector(2 downto 0);
558  ------------------------------ Power-Down Ports ----------------------------
559  GT2_RXPD_IN : in std_logic_vector(1 downto 0);
560  GT2_TXPD_IN : in std_logic_vector(1 downto 0);
561  --------------------- RX Initialization and Reset Ports --------------------
562  GT2_RXUSERRDY_IN : in std_logic;
563  -------------------------- RX Margin Analysis Ports ------------------------
564  GT2_EYESCANDATAERROR_OUT : out std_logic;
565  ------------------------- Receive Ports - CDR Ports ------------------------
566  GT2_RXCDRLOCK_OUT : out std_logic;
567  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
568  GT2_RXUSRCLK_IN : in std_logic;
569  GT2_RXUSRCLK2_IN : in std_logic;
570  ------------------ Receive Ports - FPGA RX interface Ports -----------------
571  GT2_RXDATA_OUT : out std_logic_vector(31 downto 0);
572  ------------------- Receive Ports - Pattern Checker Ports ------------------
573  GT2_RXPRBSERR_OUT : out std_logic;
574  GT2_RXPRBSSEL_IN : in std_logic_vector(2 downto 0);
575  ------------------- Receive Ports - Pattern Checker ports ------------------
576  GT2_RXPRBSCNTRESET_IN : in std_logic;
577  --------------------------- Receive Ports - RX AFE -------------------------
578  GT2_GTXRXP_IN : in std_logic;
579  ------------------------ Receive Ports - RX AFE Ports ----------------------
580  GT2_GTXRXN_IN : in std_logic;
581  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
582  GT2_RXBUFRESET_IN : in std_logic;
583  GT2_RXBUFSTATUS_OUT : out std_logic_vector(2 downto 0);
584  --------------------- Receive Ports - RX Equalizer Ports -------------------
585  GT2_RXDFEAGCHOLD_IN : in std_logic;
586  GT2_RXDFELFHOLD_IN : in std_logic;
587  --------------- Receive Ports - RX Fabric Output Control Ports -------------
588  GT2_RXOUTCLK_OUT : out std_logic;
589  ---------------------- Receive Ports - RX Gearbox Ports --------------------
590  GT2_RXDATAVALID_OUT : out std_logic;
591  GT2_RXHEADER_OUT : out std_logic_vector(1 downto 0);
592  GT2_RXHEADERVALID_OUT : out std_logic;
593  --------------------- Receive Ports - RX Gearbox Ports --------------------
594  GT2_RXGEARBOXSLIP_IN : in std_logic;
595  ------------- Receive Ports - RX Initialization and Reset Ports ------------
596  GT2_GTRXRESET_IN : in std_logic;
597  GT2_RXPCSRESET_IN : in std_logic;
598  GT2_RXPMARESET_IN : in std_logic;
599  ------------------ Receive Ports - RX Margin Analysis ports ----------------
600  GT2_RXLPMEN_IN : in std_logic;
601  -------------- Receive Ports -RX Initialization and Reset Ports ------------
602  GT2_RXRESETDONE_OUT : out std_logic;
603  --------------------- TX Initialization and Reset Ports --------------------
604  GT2_GTTXRESET_IN : in std_logic;
605  GT2_TXUSERRDY_IN : in std_logic;
606  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
607  GT2_TXUSRCLK_IN : in std_logic;
608  GT2_TXUSRCLK2_IN : in std_logic;
609  --------------- Transmit Ports - TX Configurable Driver Ports --------------
610  GT2_TXDIFFCTRL_IN : in std_logic_vector(3 downto 0);
611  GT2_TXINHIBIT_IN : in std_logic;
612  GT2_TXMAINCURSOR_IN : in std_logic_vector(6 downto 0);
613  ------------------ Transmit Ports - TX Data Path interface -----------------
614  GT2_TXDATA_IN : in std_logic_vector(31 downto 0);
615  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
616  GT2_GTXTXN_OUT : out std_logic;
617  GT2_GTXTXP_OUT : out std_logic;
618  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
619  GT2_TXOUTCLK_OUT : out std_logic;
620  GT2_TXOUTCLKFABRIC_OUT : out std_logic;
621  GT2_TXOUTCLKPCS_OUT : out std_logic;
622  --------------------- Transmit Ports - TX Gearbox Ports --------------------
623  GT2_TXHEADER_IN : in std_logic_vector(1 downto 0);
624  GT2_TXSEQUENCE_IN : in std_logic_vector(6 downto 0);
625  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
626  GT2_TXPCSRESET_IN : in std_logic;
627  GT2_TXRESETDONE_OUT : out std_logic;
628  ------------------ Transmit Ports - pattern Generator Ports ----------------
629  GT2_TXPRBSSEL_IN : in std_logic_vector(2 downto 0);
630 
631 
632  --____________________________COMMON PORTS________________________________
633  ---------------------- Common Block - Ref Clock Ports ---------------------
634  GT0_GTREFCLK0_COMMON_IN : in std_logic;
635  ------------------------- Common Block - QPLL Ports ------------------------
636  GT0_QPLLLOCK_OUT : out std_logic;
637  GT0_QPLLLOCKDETCLK_IN : in std_logic;
638  GT0_QPLLREFCLKLOST_OUT : out std_logic;
639  GT0_QPLLRESET_IN : in std_logic
640 
641 
642 );
643 end component;
644 
645 component SFP3_v2_7_TX_STARTUP_FSM
646  Generic(
647  GT_TYPE : string := "GTX";
648  STABLE_CLOCK_PERIOD : integer range 4 to 250 := 8; --Period of the stable clock driving this state-machine, unit is [ns]
649  RETRY_COUNTER_BITWIDTH : integer range 2 to 8 := 8;
650  TX_QPLL_USED : boolean := False; -- the TX and RX Reset FSMs must
651  RX_QPLL_USED : boolean := False; -- share these two generic values
652  PHASE_ALIGNMENT_MANUAL : boolean := True -- Decision if a manual phase-alignment is necessary or the automatic
653  -- is enough. For single-lane applications the automatic alignment is
654  -- sufficient
655  );
656  Port ( STABLE_CLOCK : in STD_LOGIC; --Stable Clock, either a stable clock from the PCB
657  --or reference-clock present at startup.
658  TXUSERCLK : in STD_LOGIC; --TXUSERCLK as used in the design
659  SOFT_RESET : in STD_LOGIC; --User Reset, can be pulled any time
660  QPLLREFCLKLOST : in STD_LOGIC; --QPLL Reference-clock for the GT is lost
661  CPLLREFCLKLOST : in STD_LOGIC; --CPLL Reference-clock for the GT is lost
662  QPLLLOCK : in STD_LOGIC; --Lock Detect from the QPLL of the GT
663  CPLLLOCK : in STD_LOGIC; --Lock Detect from the CPLL of the GT
664  TXRESETDONE : in STD_LOGIC;
665  MMCM_LOCK : in STD_LOGIC;
666  GTTXRESET : out STD_LOGIC:='0';
667  MMCM_RESET : out STD_LOGIC:='0';
668  QPLL_RESET : out STD_LOGIC:='0'; --Reset QPLL
669  CPLL_RESET : out STD_LOGIC:='0'; --Reset CPLL
670  TX_FSM_RESET_DONE : out STD_LOGIC:='0'; --Reset-sequence has sucessfully been finished.
671  TXUSERRDY : out STD_LOGIC:='0';
672  RUN_PHALIGNMENT : out STD_LOGIC:='0';
673  RESET_PHALIGNMENT : out STD_LOGIC:='0';
674  PHALIGNMENT_DONE : in STD_LOGIC;
675 
676  RETRY_COUNTER : out STD_LOGIC_VECTOR (RETRY_COUNTER_BITWIDTH-1 downto 0):=(others=>'0')-- Number of
677  -- Retries it took to get the transceiver up and running
678  );
679 end component;
680 
681 component SFP3_v2_7_RX_STARTUP_FSM
682  Generic(
683  EXAMPLE_SIMULATION : integer := 0;
684  EQ_MODE : string := "DFE";
685  GT_TYPE : string := "GTX";
686  STABLE_CLOCK_PERIOD : integer range 4 to 250 := 8; --Period of the stable clock driving this state-machine, unit is [ns]
687  RETRY_COUNTER_BITWIDTH : integer range 2 to 8 := 8;
688  TX_QPLL_USED : boolean := False; -- the TX and RX Reset FSMs must
689  RX_QPLL_USED : boolean := False; -- share these two generic values
690  PHASE_ALIGNMENT_MANUAL : boolean := True -- Decision if a manual phase-alignment is necessary or the automatic
691  -- is enough. For single-lane applications the automatic alignment is
692  -- sufficient
693  );
694  Port ( STABLE_CLOCK : in STD_LOGIC; --Stable Clock, either a stable clock from the PCB
695  --or reference-clock present at startup.
696  RXUSERCLK : in STD_LOGIC; --RXUSERCLK as used in the design
697  SOFT_RESET : in STD_LOGIC; --User Reset, can be pulled any time
698  QPLLREFCLKLOST : in STD_LOGIC; --QPLL Reference-clock for the GT is lost
699  CPLLREFCLKLOST : in STD_LOGIC; --CPLL Reference-clock for the GT is lost
700  QPLLLOCK : in STD_LOGIC; --Lock Detect from the QPLL of the GT
701  CPLLLOCK : in STD_LOGIC; --Lock Detect from the CPLL of the GT
702  RXRESETDONE : in STD_LOGIC;
703  MMCM_LOCK : in STD_LOGIC;
704  RECCLK_STABLE : in STD_LOGIC;
705  RECCLK_MONITOR_RESTART : in STD_LOGIC;
706  DATA_VALID : in STD_LOGIC;
707  TXUSERRDY : in STD_LOGIC; --TXUSERRDY from GT
708  DONT_RESET_ON_DATA_ERROR : in STD_LOGIC;
709  GTRXRESET : out STD_LOGIC:='0';
710  MMCM_RESET : out STD_LOGIC:='0';
711  QPLL_RESET : out STD_LOGIC:='0'; --Reset QPLL (only if RX uses QPLL)
712  CPLL_RESET : out STD_LOGIC:='0'; --Reset CPLL (only if RX uses CPLL)
713  RX_FSM_RESET_DONE : out STD_LOGIC:='0'; --Reset-sequence has sucessfully been finished.
714  RXUSERRDY : out STD_LOGIC:='0';
715  RUN_PHALIGNMENT : out STD_LOGIC;
716  PHALIGNMENT_DONE : in STD_LOGIC;
717  RESET_PHALIGNMENT : out STD_LOGIC:='0';
718  RXDFEAGCHOLD : out STD_LOGIC;
719  RXDFELFHOLD : out STD_LOGIC;
720  RXLPMLFHOLD : out STD_LOGIC;
721  RXLPMHFHOLD : out STD_LOGIC;
722  RETRY_COUNTER : out STD_LOGIC_VECTOR (RETRY_COUNTER_BITWIDTH-1 downto 0):=(others=>'0')-- Number of
723  -- Retries it took to get the transceiver up and running
724  );
725 end component;
726 
727 
728 
729 
730 
731 
732  function get_cdrlock_time(is_sim : in integer) return integer is
733  variable lock_time: integer;
734  begin
735  if (is_sim = 1) then
736  lock_time := 1000;
737  else
738  lock_time := 50000 / integer(10.3125); --Typical CDR lock time is 50,000UI as per DS183
739  end if;
740  return lock_time;
741  end function;
742 
743 
744 --***********************************Parameter Declarations********************
745 
746  constant DLY : time := 1 ns;
747  constant RX_CDRLOCK_TIME : integer := get_cdrlock_time(EXAMPLE_SIMULATION); -- 200us
748  constant WAIT_TIME_CDRLOCK : integer := RX_CDRLOCK_TIME / STABLE_CLOCK_PERIOD; -- 200 us time-out
749 
750  -------------------------- GT Wrapper Wires ------------------------------
751  signal gt0_txresetdone_i : std_logic;
752  signal gt0_rxresetdone_i : std_logic;
753  signal gt0_gttxreset_i : std_logic;
754  signal gt0_gttxreset_t : std_logic;
755  signal gt0_gtrxreset_i : std_logic;
756  signal gt0_gtrxreset_t : std_logic;
757  signal gt0_txpcsreset_i : std_logic;
758  signal gt0_rxpcsreset_i : std_logic;
759  signal gt0_rxdfelpmreset_i : std_logic;
760  signal gt0_txuserrdy_i : std_logic;
761  signal gt0_txuserrdy_t : std_logic;
762  signal gt0_rxuserrdy_i : std_logic;
763  signal gt0_rxuserrdy_t : std_logic;
764 
765  signal gt0_rxdfeagchold_i : std_logic;
766  signal gt0_rxdfelfhold_i : std_logic;
767  signal gt0_rxlpmlfhold_i : std_logic;
768  signal gt0_rxlpmhfhold_i : std_logic;
769 
770 
771  signal gt1_txresetdone_i : std_logic;
772  signal gt1_rxresetdone_i : std_logic;
773  signal gt1_gttxreset_i : std_logic;
774  signal gt1_gttxreset_t : std_logic;
775  signal gt1_gtrxreset_i : std_logic;
776  signal gt1_gtrxreset_t : std_logic;
777  signal gt1_txpcsreset_i : std_logic;
778  signal gt1_rxpcsreset_i : std_logic;
779  signal gt1_rxdfelpmreset_i : std_logic;
780  signal gt1_txuserrdy_i : std_logic;
781  signal gt1_txuserrdy_t : std_logic;
782  signal gt1_rxuserrdy_i : std_logic;
783  signal gt1_rxuserrdy_t : std_logic;
784 
785  signal gt1_rxdfeagchold_i : std_logic;
786  signal gt1_rxdfelfhold_i : std_logic;
787  signal gt1_rxlpmlfhold_i : std_logic;
788  signal gt1_rxlpmhfhold_i : std_logic;
789 
790 
791  signal gt2_txresetdone_i : std_logic;
792  signal gt2_rxresetdone_i : std_logic;
793  signal gt2_gttxreset_i : std_logic;
794  signal gt2_gttxreset_t : std_logic;
795  signal gt2_gtrxreset_i : std_logic;
796  signal gt2_gtrxreset_t : std_logic;
797  signal gt2_txpcsreset_i : std_logic;
798  signal gt2_rxpcsreset_i : std_logic;
799  signal gt2_rxdfelpmreset_i : std_logic;
800  signal gt2_txuserrdy_i : std_logic;
801  signal gt2_txuserrdy_t : std_logic;
802  signal gt2_rxuserrdy_i : std_logic;
803  signal gt2_rxuserrdy_t : std_logic;
804 
805  signal gt2_rxdfeagchold_i : std_logic;
806  signal gt2_rxdfelfhold_i : std_logic;
807  signal gt2_rxlpmlfhold_i : std_logic;
808  signal gt2_rxlpmhfhold_i : std_logic;
809 
810 
811 
812  signal gt0_qpllreset_i : std_logic;
813  signal gt0_qpllreset_t : std_logic;
814  signal gt0_qpllrefclklost_i : std_logic;
815  signal gt0_qplllock_i : std_logic;
816 
817 
818  ------------------------------- Global Signals -----------------------------
819  signal tied_to_ground_i : std_logic;
820  signal tied_to_vcc_i : std_logic;
821 
822  signal gt0_rxoutclk_i : std_logic;
823  signal gt0_recclk_stable_i : std_logic;
824 
825  signal gt1_rxoutclk_i : std_logic;
826  signal gt1_recclk_stable_i : std_logic;
827 
828  signal gt2_rxoutclk_i : std_logic;
829  signal gt2_recclk_stable_i : std_logic;
830 
831 
832 
833 
834 
835 
836  signal rx_cdrlock_counter : integer range 0 to WAIT_TIME_CDRLOCK:= 0 ;
837  signal rx_cdrlocked : std_logic;
838 
839 
840 
841 
842 
843 --**************************** Main Body of Code *******************************
844 begin
845  -- Static signal Assigments
846  tied_to_ground_i <= '0';
847  tied_to_vcc_i <= '1';
848 
849  ----------------------------- The GT Wrapper -----------------------------
850 
851  -- Use the instantiation template in the example directory to add the GT wrapper to your design.
852  -- In this example, the wrapper is wired up for basic operation with a frame generator and frame
853  -- checker. The GTs will reset, then attempt to align and transmit data. If channel bonding is
854  -- enabled, bonding should occur after alignment.
855 
856 
857  SFP3_v2_7_i : SFP3_v2_7
858  generic map
859  (
860  WRAPPER_SIM_GTRESET_SPEEDUP => EXAMPLE_SIM_GTRESET_SPEEDUP
861  )
862  port map
863  (
864 
865  --_____________________________________________________________________
866  --_____________________________________________________________________
867  --GT0 (X1Y12)
868 
869  ---------------------------- Channel - DRP Ports --------------------------
870  GT0_DRPADDR_IN => GT0_DRPADDR_IN,
871  GT0_DRPCLK_IN => GT0_DRPCLK_IN,
872  GT0_DRPDI_IN => GT0_DRPDI_IN,
873  GT0_DRPDO_OUT => GT0_DRPDO_OUT,
874  GT0_DRPEN_IN => GT0_DRPEN_IN,
875  GT0_DRPRDY_OUT => GT0_DRPRDY_OUT,
876  GT0_DRPWE_IN => GT0_DRPWE_IN,
877  ------------------------------- Loopback Ports -----------------------------
878  GT0_LOOPBACK_IN => GT0_LOOPBACK_IN,
879  ------------------------------ Power-Down Ports ----------------------------
880  GT0_RXPD_IN => GT0_RXPD_IN,
881  GT0_TXPD_IN => GT0_TXPD_IN,
882  --------------------- RX Initialization and Reset Ports --------------------
883  GT0_RXUSERRDY_IN => gt0_rxuserrdy_i,
884  -------------------------- RX Margin Analysis Ports ------------------------
885  GT0_EYESCANDATAERROR_OUT => GT0_EYESCANDATAERROR_OUT,
886  ------------------------- Receive Ports - CDR Ports ------------------------
887  GT0_RXCDRLOCK_OUT => GT0_RXCDRLOCK_OUT,
888  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
889  GT0_RXUSRCLK_IN => GT0_RXUSRCLK_IN,
890  GT0_RXUSRCLK2_IN => GT0_RXUSRCLK2_IN,
891  ------------------ Receive Ports - FPGA RX interface Ports -----------------
892  GT0_RXDATA_OUT => GT0_RXDATA_OUT,
893  ------------------- Receive Ports - Pattern Checker Ports ------------------
894  GT0_RXPRBSERR_OUT => GT0_RXPRBSERR_OUT,
895  GT0_RXPRBSSEL_IN => GT0_RXPRBSSEL_IN,
896  ------------------- Receive Ports - Pattern Checker ports ------------------
897  GT0_RXPRBSCNTRESET_IN => GT0_RXPRBSCNTRESET_IN ,
898  --------------------------- Receive Ports - RX AFE -------------------------
899  GT0_GTXRXP_IN => GT0_GTXRXP_IN,
900  ------------------------ Receive Ports - RX AFE Ports ----------------------
901  GT0_GTXRXN_IN => GT0_GTXRXN_IN,
902  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
903  GT0_RXBUFRESET_IN => GT0_RXBUFRESET_IN,
904  GT0_RXBUFSTATUS_OUT => GT0_RXBUFSTATUS_OUT ,
905  --------------------- Receive Ports - RX Equalizer Ports -------------------
906  GT0_RXDFEAGCHOLD_IN => gt0_rxdfeagchold_i,
907  GT0_RXDFELFHOLD_IN => gt0_rxdfelfhold_i,
908  --------------- Receive Ports - RX Fabric Output Control Ports -------------
909  GT0_RXOUTCLK_OUT => gt0_rxoutclk_i,
910  ---------------------- Receive Ports - RX Gearbox Ports --------------------
911  GT0_RXDATAVALID_OUT => GT0_RXDATAVALID_OUT ,
912  GT0_RXHEADER_OUT => GT0_RXHEADER_OUT,
913  GT0_RXHEADERVALID_OUT => GT0_RXHEADERVALID_OUT ,
914  --------------------- Receive Ports - RX Gearbox Ports --------------------
915  GT0_RXGEARBOXSLIP_IN => GT0_RXGEARBOXSLIP_IN ,
916  ------------- Receive Ports - RX Initialization and Reset Ports ------------
917  GT0_GTRXRESET_IN => gt0_gtrxreset_i,
918  GT0_RXPCSRESET_IN => gt0_rxpcsreset_i,
919  GT0_RXPMARESET_IN => GT0_RXPMARESET_IN,
920  ------------------ Receive Ports - RX Margin Analysis ports ----------------
921  GT0_RXLPMEN_IN => GT0_RXLPMEN_IN,
922  -------------- Receive Ports -RX Initialization and Reset Ports ------------
923  GT0_RXRESETDONE_OUT => gt0_rxresetdone_i,
924  --------------------- TX Initialization and Reset Ports --------------------
925  GT0_GTTXRESET_IN => gt0_gttxreset_i,
926  GT0_TXUSERRDY_IN => gt0_txuserrdy_i,
927  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
928  GT0_TXUSRCLK_IN => GT0_TXUSRCLK_IN,
929  GT0_TXUSRCLK2_IN => GT0_TXUSRCLK2_IN,
930  --------------- Transmit Ports - TX Configurable Driver Ports --------------
931  GT0_TXDIFFCTRL_IN => GT0_TXDIFFCTRL_IN,
932  GT0_TXINHIBIT_IN => GT0_TXINHIBIT_IN,
933  GT0_TXMAINCURSOR_IN => GT0_TXMAINCURSOR_IN ,
934  ------------------ Transmit Ports - TX Data Path interface -----------------
935  GT0_TXDATA_IN => GT0_TXDATA_IN,
936  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
937  GT0_GTXTXN_OUT => GT0_GTXTXN_OUT,
938  GT0_GTXTXP_OUT => GT0_GTXTXP_OUT,
939  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
940  GT0_TXOUTCLK_OUT => GT0_TXOUTCLK_OUT,
941  GT0_TXOUTCLKFABRIC_OUT => GT0_TXOUTCLKFABRIC_OUT ,
942  GT0_TXOUTCLKPCS_OUT => GT0_TXOUTCLKPCS_OUT ,
943  --------------------- Transmit Ports - TX Gearbox Ports --------------------
944  GT0_TXHEADER_IN => GT0_TXHEADER_IN,
945  GT0_TXSEQUENCE_IN => GT0_TXSEQUENCE_IN,
946  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
947  GT0_TXPCSRESET_IN => gt0_txpcsreset_i,
948  GT0_TXRESETDONE_OUT => gt0_txresetdone_i,
949  ------------------ Transmit Ports - pattern Generator Ports ----------------
950  GT0_TXPRBSSEL_IN => GT0_TXPRBSSEL_IN,
951 
952 
953 
954  --_____________________________________________________________________
955  --_____________________________________________________________________
956  --GT1 (X1Y13)
957 
958  ---------------------------- Channel - DRP Ports --------------------------
959  GT1_DRPADDR_IN => GT1_DRPADDR_IN,
960  GT1_DRPCLK_IN => GT1_DRPCLK_IN,
961  GT1_DRPDI_IN => GT1_DRPDI_IN,
962  GT1_DRPDO_OUT => GT1_DRPDO_OUT,
963  GT1_DRPEN_IN => GT1_DRPEN_IN,
964  GT1_DRPRDY_OUT => GT1_DRPRDY_OUT,
965  GT1_DRPWE_IN => GT1_DRPWE_IN,
966  ------------------------------- Loopback Ports -----------------------------
967  GT1_LOOPBACK_IN => GT1_LOOPBACK_IN,
968  ------------------------------ Power-Down Ports ----------------------------
969  GT1_RXPD_IN => GT1_RXPD_IN,
970  GT1_TXPD_IN => GT1_TXPD_IN,
971  --------------------- RX Initialization and Reset Ports --------------------
972  GT1_RXUSERRDY_IN => gt1_rxuserrdy_i,
973  -------------------------- RX Margin Analysis Ports ------------------------
974  GT1_EYESCANDATAERROR_OUT => GT1_EYESCANDATAERROR_OUT,
975  ------------------------- Receive Ports - CDR Ports ------------------------
976  GT1_RXCDRLOCK_OUT => GT1_RXCDRLOCK_OUT,
977  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
978  GT1_RXUSRCLK_IN => GT1_RXUSRCLK_IN,
979  GT1_RXUSRCLK2_IN => GT1_RXUSRCLK2_IN,
980  ------------------ Receive Ports - FPGA RX interface Ports -----------------
981  GT1_RXDATA_OUT => GT1_RXDATA_OUT,
982  ------------------- Receive Ports - Pattern Checker Ports ------------------
983  GT1_RXPRBSERR_OUT => GT1_RXPRBSERR_OUT,
984  GT1_RXPRBSSEL_IN => GT1_RXPRBSSEL_IN,
985  ------------------- Receive Ports - Pattern Checker ports ------------------
986  GT1_RXPRBSCNTRESET_IN => GT1_RXPRBSCNTRESET_IN ,
987  --------------------------- Receive Ports - RX AFE -------------------------
988  GT1_GTXRXP_IN => GT1_GTXRXP_IN,
989  ------------------------ Receive Ports - RX AFE Ports ----------------------
990  GT1_GTXRXN_IN => GT1_GTXRXN_IN,
991  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
992  GT1_RXBUFRESET_IN => GT1_RXBUFRESET_IN,
993  GT1_RXBUFSTATUS_OUT => GT1_RXBUFSTATUS_OUT ,
994  --------------------- Receive Ports - RX Equalizer Ports -------------------
995  GT1_RXDFEAGCHOLD_IN => gt1_rxdfeagchold_i,
996  GT1_RXDFELFHOLD_IN => gt1_rxdfelfhold_i,
997  --------------- Receive Ports - RX Fabric Output Control Ports -------------
998  GT1_RXOUTCLK_OUT => gt1_rxoutclk_i,
999  ---------------------- Receive Ports - RX Gearbox Ports --------------------
1000  GT1_RXDATAVALID_OUT => GT1_RXDATAVALID_OUT ,
1001  GT1_RXHEADER_OUT => GT1_RXHEADER_OUT,
1002  GT1_RXHEADERVALID_OUT => GT1_RXHEADERVALID_OUT ,
1003  --------------------- Receive Ports - RX Gearbox Ports --------------------
1004  GT1_RXGEARBOXSLIP_IN => GT1_RXGEARBOXSLIP_IN ,
1005  ------------- Receive Ports - RX Initialization and Reset Ports ------------
1006  GT1_GTRXRESET_IN => gt1_gtrxreset_i,
1007  GT1_RXPCSRESET_IN => gt1_rxpcsreset_i,
1008  GT1_RXPMARESET_IN => GT1_RXPMARESET_IN,
1009  ------------------ Receive Ports - RX Margin Analysis ports ----------------
1010  GT1_RXLPMEN_IN => GT1_RXLPMEN_IN,
1011  -------------- Receive Ports -RX Initialization and Reset Ports ------------
1012  GT1_RXRESETDONE_OUT => gt1_rxresetdone_i,
1013  --------------------- TX Initialization and Reset Ports --------------------
1014  GT1_GTTXRESET_IN => gt1_gttxreset_i,
1015  GT1_TXUSERRDY_IN => gt1_txuserrdy_i,
1016  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
1017  GT1_TXUSRCLK_IN => GT1_TXUSRCLK_IN,
1018  GT1_TXUSRCLK2_IN => GT1_TXUSRCLK2_IN,
1019  --------------- Transmit Ports - TX Configurable Driver Ports --------------
1020  GT1_TXDIFFCTRL_IN => GT1_TXDIFFCTRL_IN,
1021  GT1_TXINHIBIT_IN => GT1_TXINHIBIT_IN,
1022  GT1_TXMAINCURSOR_IN => GT1_TXMAINCURSOR_IN ,
1023  ------------------ Transmit Ports - TX Data Path interface -----------------
1024  GT1_TXDATA_IN => GT1_TXDATA_IN,
1025  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
1026  GT1_GTXTXN_OUT => GT1_GTXTXN_OUT,
1027  GT1_GTXTXP_OUT => GT1_GTXTXP_OUT,
1028  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
1029  GT1_TXOUTCLK_OUT => GT1_TXOUTCLK_OUT,
1030  GT1_TXOUTCLKFABRIC_OUT => GT1_TXOUTCLKFABRIC_OUT ,
1031  GT1_TXOUTCLKPCS_OUT => GT1_TXOUTCLKPCS_OUT ,
1032  --------------------- Transmit Ports - TX Gearbox Ports --------------------
1033  GT1_TXHEADER_IN => GT1_TXHEADER_IN,
1034  GT1_TXSEQUENCE_IN => GT1_TXSEQUENCE_IN,
1035  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
1036  GT1_TXPCSRESET_IN => gt1_txpcsreset_i,
1037  GT1_TXRESETDONE_OUT => gt1_txresetdone_i,
1038  ------------------ Transmit Ports - pattern Generator Ports ----------------
1039  GT1_TXPRBSSEL_IN => GT1_TXPRBSSEL_IN,
1040 
1041 
1042 
1043  --_____________________________________________________________________
1044  --_____________________________________________________________________
1045  --GT2 (X1Y14)
1046 
1047  ---------------------------- Channel - DRP Ports --------------------------
1048  GT2_DRPADDR_IN => GT2_DRPADDR_IN,
1049  GT2_DRPCLK_IN => GT2_DRPCLK_IN,
1050  GT2_DRPDI_IN => GT2_DRPDI_IN,
1051  GT2_DRPDO_OUT => GT2_DRPDO_OUT,
1052  GT2_DRPEN_IN => GT2_DRPEN_IN,
1053  GT2_DRPRDY_OUT => GT2_DRPRDY_OUT,
1054  GT2_DRPWE_IN => GT2_DRPWE_IN,
1055  ------------------------------- Loopback Ports -----------------------------
1056  GT2_LOOPBACK_IN => GT2_LOOPBACK_IN,
1057  ------------------------------ Power-Down Ports ----------------------------
1058  GT2_RXPD_IN => GT2_RXPD_IN,
1059  GT2_TXPD_IN => GT2_TXPD_IN,
1060  --------------------- RX Initialization and Reset Ports --------------------
1061  GT2_RXUSERRDY_IN => gt2_rxuserrdy_i,
1062  -------------------------- RX Margin Analysis Ports ------------------------
1063  GT2_EYESCANDATAERROR_OUT => GT2_EYESCANDATAERROR_OUT,
1064  ------------------------- Receive Ports - CDR Ports ------------------------
1065  GT2_RXCDRLOCK_OUT => GT2_RXCDRLOCK_OUT,
1066  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
1067  GT2_RXUSRCLK_IN => GT2_RXUSRCLK_IN,
1068  GT2_RXUSRCLK2_IN => GT2_RXUSRCLK2_IN,
1069  ------------------ Receive Ports - FPGA RX interface Ports -----------------
1070  GT2_RXDATA_OUT => GT2_RXDATA_OUT,
1071  ------------------- Receive Ports - Pattern Checker Ports ------------------
1072  GT2_RXPRBSERR_OUT => GT2_RXPRBSERR_OUT,
1073  GT2_RXPRBSSEL_IN => GT2_RXPRBSSEL_IN,
1074  ------------------- Receive Ports - Pattern Checker ports ------------------
1075  GT2_RXPRBSCNTRESET_IN => GT2_RXPRBSCNTRESET_IN ,
1076  --------------------------- Receive Ports - RX AFE -------------------------
1077  GT2_GTXRXP_IN => GT2_GTXRXP_IN,
1078  ------------------------ Receive Ports - RX AFE Ports ----------------------
1079  GT2_GTXRXN_IN => GT2_GTXRXN_IN,
1080  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
1081  GT2_RXBUFRESET_IN => GT2_RXBUFRESET_IN,
1082  GT2_RXBUFSTATUS_OUT => GT2_RXBUFSTATUS_OUT ,
1083  --------------------- Receive Ports - RX Equalizer Ports -------------------
1084  GT2_RXDFEAGCHOLD_IN => gt2_rxdfeagchold_i,
1085  GT2_RXDFELFHOLD_IN => gt2_rxdfelfhold_i,
1086  --------------- Receive Ports - RX Fabric Output Control Ports -------------
1087  GT2_RXOUTCLK_OUT => gt2_rxoutclk_i,
1088  ---------------------- Receive Ports - RX Gearbox Ports --------------------
1089  GT2_RXDATAVALID_OUT => GT2_RXDATAVALID_OUT ,
1090  GT2_RXHEADER_OUT => GT2_RXHEADER_OUT,
1091  GT2_RXHEADERVALID_OUT => GT2_RXHEADERVALID_OUT ,
1092  --------------------- Receive Ports - RX Gearbox Ports --------------------
1093  GT2_RXGEARBOXSLIP_IN => GT2_RXGEARBOXSLIP_IN ,
1094  ------------- Receive Ports - RX Initialization and Reset Ports ------------
1095  GT2_GTRXRESET_IN => gt2_gtrxreset_i,
1096  GT2_RXPCSRESET_IN => gt2_rxpcsreset_i,
1097  GT2_RXPMARESET_IN => GT2_RXPMARESET_IN,
1098  ------------------ Receive Ports - RX Margin Analysis ports ----------------
1099  GT2_RXLPMEN_IN => GT2_RXLPMEN_IN,
1100  -------------- Receive Ports -RX Initialization and Reset Ports ------------
1101  GT2_RXRESETDONE_OUT => gt2_rxresetdone_i,
1102  --------------------- TX Initialization and Reset Ports --------------------
1103  GT2_GTTXRESET_IN => gt2_gttxreset_i,
1104  GT2_TXUSERRDY_IN => gt2_txuserrdy_i,
1105  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
1106  GT2_TXUSRCLK_IN => GT2_TXUSRCLK_IN,
1107  GT2_TXUSRCLK2_IN => GT2_TXUSRCLK2_IN,
1108  --------------- Transmit Ports - TX Configurable Driver Ports --------------
1109  GT2_TXDIFFCTRL_IN => GT2_TXDIFFCTRL_IN,
1110  GT2_TXINHIBIT_IN => GT2_TXINHIBIT_IN,
1111  GT2_TXMAINCURSOR_IN => GT2_TXMAINCURSOR_IN ,
1112  ------------------ Transmit Ports - TX Data Path interface -----------------
1113  GT2_TXDATA_IN => GT2_TXDATA_IN,
1114  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
1115  GT2_GTXTXN_OUT => GT2_GTXTXN_OUT,
1116  GT2_GTXTXP_OUT => GT2_GTXTXP_OUT,
1117  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
1118  GT2_TXOUTCLK_OUT => GT2_TXOUTCLK_OUT,
1119  GT2_TXOUTCLKFABRIC_OUT => GT2_TXOUTCLKFABRIC_OUT ,
1120  GT2_TXOUTCLKPCS_OUT => GT2_TXOUTCLKPCS_OUT ,
1121  --------------------- Transmit Ports - TX Gearbox Ports --------------------
1122  GT2_TXHEADER_IN => GT2_TXHEADER_IN,
1123  GT2_TXSEQUENCE_IN => GT2_TXSEQUENCE_IN,
1124  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
1125  GT2_TXPCSRESET_IN => gt2_txpcsreset_i,
1126  GT2_TXRESETDONE_OUT => gt2_txresetdone_i,
1127  ------------------ Transmit Ports - pattern Generator Ports ----------------
1128  GT2_TXPRBSSEL_IN => GT2_TXPRBSSEL_IN,
1129 
1130 
1131 
1132 
1133  --____________________________COMMON PORTS________________________________
1134  ---------------------- Common Block - Ref Clock Ports ---------------------
1135  GT0_GTREFCLK0_COMMON_IN => GT0_GTREFCLK0_COMMON_IN ,
1136  ------------------------- Common Block - QPLL Ports ------------------------
1137  GT0_QPLLLOCK_OUT => gt0_qplllock_i,
1138  GT0_QPLLLOCKDETCLK_IN => GT0_QPLLLOCKDETCLK_IN ,
1139  GT0_QPLLREFCLKLOST_OUT => gt0_qpllrefclklost_i ,
1140  GT0_QPLLRESET_IN => gt0_qpllreset_i
1141 
1142  );
1143 
1144  gt0_rxpcsreset_i <= tied_to_ground_i;
1145  gt0_txpcsreset_i <= tied_to_ground_i;
1146  gt1_rxpcsreset_i <= tied_to_ground_i;
1147  gt1_txpcsreset_i <= tied_to_ground_i;
1148  gt2_rxpcsreset_i <= tied_to_ground_i;
1149  gt2_txpcsreset_i <= tied_to_ground_i;
1150 
1151  gt0_rxdfelpmreset_i <= tied_to_ground_i;
1152  gt1_rxdfelpmreset_i <= tied_to_ground_i;
1153  gt2_rxdfelpmreset_i <= tied_to_ground_i;
1154 
1155 
1156 
1157 
1158  GT0_TXRESETDONE_OUT <= gt0_txresetdone_i;
1159  GT0_RXRESETDONE_OUT <= gt0_rxresetdone_i;
1160  GT0_RXOUTCLK_OUT <= gt0_rxoutclk_i;
1161  GT1_TXRESETDONE_OUT <= gt1_txresetdone_i;
1162  GT1_RXRESETDONE_OUT <= gt1_rxresetdone_i;
1163  GT1_RXOUTCLK_OUT <= gt1_rxoutclk_i;
1164  GT2_TXRESETDONE_OUT <= gt2_txresetdone_i;
1165  GT2_RXRESETDONE_OUT <= gt2_rxresetdone_i;
1166  GT2_RXOUTCLK_OUT <= gt2_rxoutclk_i;
1167  GT0_QPLLLOCK_OUT <= gt0_qplllock_i;
1168 
1169 chipscope : if EXAMPLE_USE_CHIPSCOPE = 1 generate
1170  gt0_gttxreset_i <= GT0_GTTXRESET_IN or gt0_gttxreset_t;
1171  gt0_gtrxreset_i <= GT0_GTRXRESET_IN or gt0_gtrxreset_t;
1172  gt0_txuserrdy_i <= GT0_TXUSERRDY_IN or gt0_txuserrdy_t;
1173  gt0_rxuserrdy_i <= GT0_RXUSERRDY_IN or gt0_rxuserrdy_t;
1174  gt1_gttxreset_i <= GT1_GTTXRESET_IN or gt1_gttxreset_t;
1175  gt1_gtrxreset_i <= GT1_GTRXRESET_IN or gt1_gtrxreset_t;
1176  gt1_txuserrdy_i <= GT1_TXUSERRDY_IN or gt1_txuserrdy_t;
1177  gt1_rxuserrdy_i <= GT1_RXUSERRDY_IN or gt1_rxuserrdy_t;
1178  gt2_gttxreset_i <= GT2_GTTXRESET_IN or gt2_gttxreset_t;
1179  gt2_gtrxreset_i <= GT2_GTRXRESET_IN or gt2_gtrxreset_t;
1180  gt2_txuserrdy_i <= GT2_TXUSERRDY_IN or gt2_txuserrdy_t;
1181  gt2_rxuserrdy_i <= GT2_RXUSERRDY_IN or gt2_rxuserrdy_t;
1182  gt0_qpllreset_i <= GT0_QPLLRESET_IN or gt0_qpllreset_t;
1183 end generate chipscope;
1184 
1185 no_chipscope : if EXAMPLE_USE_CHIPSCOPE = 0 generate
1186  gt0_gttxreset_i <= gt0_gttxreset_t;
1187  gt0_gtrxreset_i <= gt0_gtrxreset_t;
1188  gt0_txuserrdy_i <= gt0_txuserrdy_t;
1189  gt0_rxuserrdy_i <= gt0_rxuserrdy_t;
1190  gt1_gttxreset_i <= gt1_gttxreset_t;
1191  gt1_gtrxreset_i <= gt1_gtrxreset_t;
1192  gt1_txuserrdy_i <= gt1_txuserrdy_t;
1193  gt1_rxuserrdy_i <= gt1_rxuserrdy_t;
1194  gt2_gttxreset_i <= gt2_gttxreset_t;
1195  gt2_gtrxreset_i <= gt2_gtrxreset_t;
1196  gt2_txuserrdy_i <= gt2_txuserrdy_t;
1197  gt2_rxuserrdy_i <= gt2_rxuserrdy_t;
1198  gt0_qpllreset_i <= gt0_qpllreset_t;
1199 end generate no_chipscope;
1200 
1201 
1202 gt0_txresetfsm_i: SFP3_v2_7_TX_STARTUP_FSM
1203 
1204  generic map(
1205  GT_TYPE => "GTX", --GTX or GTH or GTP
1206  STABLE_CLOCK_PERIOD => STABLE_CLOCK_PERIOD, -- Period of the stable clock driving this state-machine, unit is [ns]
1207  RETRY_COUNTER_BITWIDTH => 8,
1208  TX_QPLL_USED => TRUE , -- the TX and RX Reset FSMs must
1209  RX_QPLL_USED => TRUE, -- share these two generic values
1210  PHASE_ALIGNMENT_MANUAL => FALSE -- Decision if a manual phase-alignment is necessary or the automatic
1211  -- is enough. For single-lane applications the automatic alignment is
1212  -- sufficient
1213  )
1214  port map (
1215  STABLE_CLOCK => SYSCLK_IN,
1216  TXUSERCLK => GT0_TXUSRCLK_IN,
1217  SOFT_RESET => SOFT_RESET_IN,
1218  QPLLREFCLKLOST => gt0_qpllrefclklost_i ,
1219  CPLLREFCLKLOST => tied_to_ground_i,
1220  QPLLLOCK => gt0_qplllock_i,
1221  CPLLLOCK => tied_to_vcc_i,
1222  TXRESETDONE => gt0_txresetdone_i,
1223  MMCM_LOCK => tied_to_vcc_i,
1224  GTTXRESET => gt0_gttxreset_t,
1225  MMCM_RESET => open,
1226  QPLL_RESET => gt0_qpllreset_t,
1227  CPLL_RESET => open,
1228  TX_FSM_RESET_DONE => GT0_TX_FSM_RESET_DONE_OUT,
1229  TXUSERRDY => gt0_txuserrdy_t,
1230  RUN_PHALIGNMENT => open,
1231  RESET_PHALIGNMENT => open,
1232  PHALIGNMENT_DONE => tied_to_vcc_i,
1233  RETRY_COUNTER => open
1234  );
1235 
1236 
1237 gt1_txresetfsm_i: SFP3_v2_7_TX_STARTUP_FSM
1238 
1239  generic map(
1240  GT_TYPE => "GTX", --GTX or GTH or GTP
1241  STABLE_CLOCK_PERIOD => STABLE_CLOCK_PERIOD, -- Period of the stable clock driving this state-machine, unit is [ns]
1242  RETRY_COUNTER_BITWIDTH => 8,
1243  TX_QPLL_USED => TRUE , -- the TX and RX Reset FSMs must
1244  RX_QPLL_USED => TRUE, -- share these two generic values
1245  PHASE_ALIGNMENT_MANUAL => FALSE -- Decision if a manual phase-alignment is necessary or the automatic
1246  -- is enough. For single-lane applications the automatic alignment is
1247  -- sufficient
1248  )
1249  port map (
1250  STABLE_CLOCK => SYSCLK_IN,
1251  TXUSERCLK => GT1_TXUSRCLK_IN,
1252  SOFT_RESET => SOFT_RESET_IN,
1253  QPLLREFCLKLOST => gt0_qpllrefclklost_i ,
1254  CPLLREFCLKLOST => tied_to_ground_i,
1255  QPLLLOCK => gt0_qplllock_i,
1256  CPLLLOCK => tied_to_vcc_i,
1257  TXRESETDONE => gt1_txresetdone_i,
1258  MMCM_LOCK => tied_to_vcc_i,
1259  GTTXRESET => gt1_gttxreset_t,
1260  MMCM_RESET => open,
1261  QPLL_RESET => open,
1262  CPLL_RESET => open,
1263  TX_FSM_RESET_DONE => GT1_TX_FSM_RESET_DONE_OUT,
1264  TXUSERRDY => gt1_txuserrdy_t,
1265  RUN_PHALIGNMENT => open,
1266  RESET_PHALIGNMENT => open,
1267  PHALIGNMENT_DONE => tied_to_vcc_i,
1268  RETRY_COUNTER => open
1269  );
1270 
1271 
1272 
1273 
1274 
1275 
1276 gt0_rxresetfsm_i: SFP3_v2_7_RX_STARTUP_FSM
1277 
1278  generic map(
1279  EXAMPLE_SIMULATION => EXAMPLE_SIMULATION,
1280  GT_TYPE => "GTX", --GTX or GTH or GTP
1281  EQ_MODE => "DFE", --Rx Equalization Mode - Set to DFE or LPM
1282  STABLE_CLOCK_PERIOD => STABLE_CLOCK_PERIOD, --Period of the stable clock driving this state-machine, unit is [ns]
1283  RETRY_COUNTER_BITWIDTH => 8,
1284  TX_QPLL_USED => TRUE , -- the TX and RX Reset FSMs must
1285  RX_QPLL_USED => TRUE, -- share these two generic values
1286  PHASE_ALIGNMENT_MANUAL => FALSE -- Decision if a manual phase-alignment is necessary or the automatic
1287  -- is enough. For single-lane applications the automatic alignment is
1288  -- sufficient
1289  )
1290  port map (
1291  STABLE_CLOCK => SYSCLK_IN,
1292  RXUSERCLK => GT0_RXUSRCLK_IN,
1293  SOFT_RESET => SOFT_RESET_IN,
1294  DONT_RESET_ON_DATA_ERROR => DONT_RESET_ON_DATA_ERROR_IN,
1295  QPLLREFCLKLOST => gt0_qpllrefclklost_i ,
1296  CPLLREFCLKLOST => tied_to_ground_i,
1297  QPLLLOCK => gt0_qplllock_i,
1298  CPLLLOCK => tied_to_vcc_i,
1299  RXRESETDONE => gt0_rxresetdone_i,
1300  MMCM_LOCK => tied_to_vcc_i,
1301  RECCLK_STABLE => gt0_recclk_stable_i ,
1302  RECCLK_MONITOR_RESTART => tied_to_ground_i,
1303  DATA_VALID => GT0_DATA_VALID_IN,
1304  TXUSERRDY => tied_to_vcc_i,
1305  GTRXRESET => gt0_gtrxreset_t,
1306  MMCM_RESET => open,
1307  QPLL_RESET => open,
1308  CPLL_RESET => open,
1309  RX_FSM_RESET_DONE => GT0_RX_FSM_RESET_DONE_OUT,
1310  RXUSERRDY => gt0_rxuserrdy_t,
1311  RUN_PHALIGNMENT => open,
1312  RESET_PHALIGNMENT => open,
1313  PHALIGNMENT_DONE => tied_to_vcc_i,
1314  RXDFEAGCHOLD => gt0_rxdfeagchold_i ,
1315  RXDFELFHOLD => gt0_rxdfelfhold_i,
1316  RXLPMLFHOLD => gt0_rxlpmlfhold_i,
1317  RXLPMHFHOLD => gt0_rxlpmhfhold_i,
1318  RETRY_COUNTER => open
1319  );
1320 
1321 gt1_rxresetfsm_i: SFP3_v2_7_RX_STARTUP_FSM
1322 
1323  generic map(
1324  EXAMPLE_SIMULATION => EXAMPLE_SIMULATION,
1325  GT_TYPE => "GTX", --GTX or GTH or GTP
1326  EQ_MODE => "DFE", --Rx Equalization Mode - Set to DFE or LPM
1327  STABLE_CLOCK_PERIOD => STABLE_CLOCK_PERIOD, --Period of the stable clock driving this state-machine, unit is [ns]
1328  RETRY_COUNTER_BITWIDTH => 8,
1329  TX_QPLL_USED => TRUE , -- the TX and RX Reset FSMs must
1330  RX_QPLL_USED => TRUE, -- share these two generic values
1331  PHASE_ALIGNMENT_MANUAL => FALSE -- Decision if a manual phase-alignment is necessary or the automatic
1332  -- is enough. For single-lane applications the automatic alignment is
1333  -- sufficient
1334  )
1335  port map (
1336  STABLE_CLOCK => SYSCLK_IN,
1337  RXUSERCLK => GT1_RXUSRCLK_IN,
1338  SOFT_RESET => SOFT_RESET_IN,
1339  DONT_RESET_ON_DATA_ERROR => DONT_RESET_ON_DATA_ERROR_IN,
1340  QPLLREFCLKLOST => gt0_qpllrefclklost_i ,
1341  CPLLREFCLKLOST => tied_to_ground_i,
1342  QPLLLOCK => gt0_qplllock_i,
1343  CPLLLOCK => tied_to_vcc_i,
1344  RXRESETDONE => gt1_rxresetdone_i,
1345  MMCM_LOCK => tied_to_vcc_i,
1346  RECCLK_STABLE => gt1_recclk_stable_i ,
1347  RECCLK_MONITOR_RESTART => tied_to_ground_i,
1348  DATA_VALID => GT1_DATA_VALID_IN,
1349  TXUSERRDY => tied_to_vcc_i,
1350  GTRXRESET => gt1_gtrxreset_t,
1351  MMCM_RESET => open,
1352  QPLL_RESET => open,
1353  CPLL_RESET => open,
1354  RX_FSM_RESET_DONE => GT1_RX_FSM_RESET_DONE_OUT,
1355  RXUSERRDY => gt1_rxuserrdy_t,
1356  RUN_PHALIGNMENT => open,
1357  RESET_PHALIGNMENT => open,
1358  PHALIGNMENT_DONE => tied_to_vcc_i,
1359  RXDFEAGCHOLD => gt1_rxdfeagchold_i,
1360  RXDFELFHOLD => gt1_rxdfelfhold_i,
1361  RXLPMLFHOLD => gt1_rxlpmlfhold_i,
1362  RXLPMHFHOLD => gt1_rxlpmhfhold_i,
1363  RETRY_COUNTER => open
1364  );
1365 g_gt2_resetfsm : if(flavor /= "HCAL") generate
1366 
1367  gt2_txresetfsm_i: SFP3_v2_7_TX_STARTUP_FSM
1368 
1369  generic map(
1370  GT_TYPE => "GTX", --GTX or GTH or GTP
1371  STABLE_CLOCK_PERIOD => STABLE_CLOCK_PERIOD, -- Period of the stable clock driving this state-machine, unit is [ns]
1372  RETRY_COUNTER_BITWIDTH => 8,
1373  TX_QPLL_USED => TRUE , -- the TX and RX Reset FSMs must
1374  RX_QPLL_USED => TRUE, -- share these two generic values
1375  PHASE_ALIGNMENT_MANUAL => FALSE -- Decision if a manual phase-alignment is necessary or the automatic
1376  -- is enough. For single-lane applications the automatic alignment is
1377  -- sufficient
1378  )
1379  port map (
1380  STABLE_CLOCK => SYSCLK_IN,
1381  TXUSERCLK => GT2_TXUSRCLK_IN,
1382  SOFT_RESET => SOFT_RESET_IN,
1383  QPLLREFCLKLOST => gt0_qpllrefclklost_i ,
1384  CPLLREFCLKLOST => tied_to_ground_i,
1385  QPLLLOCK => gt0_qplllock_i,
1386  CPLLLOCK => tied_to_vcc_i,
1387  TXRESETDONE => gt2_txresetdone_i,
1388  MMCM_LOCK => tied_to_vcc_i,
1389  GTTXRESET => gt2_gttxreset_t,
1390  MMCM_RESET => open,
1391  QPLL_RESET => open,
1392  CPLL_RESET => open,
1393  TX_FSM_RESET_DONE => GT2_TX_FSM_RESET_DONE_OUT,
1394  TXUSERRDY => gt2_txuserrdy_t,
1395  RUN_PHALIGNMENT => open,
1396  RESET_PHALIGNMENT => open,
1397  PHALIGNMENT_DONE => tied_to_vcc_i,
1398  RETRY_COUNTER => open
1399  );
1400 
1401  gt2_rxresetfsm_i: SFP3_v2_7_RX_STARTUP_FSM
1402 
1403  generic map(
1404  EXAMPLE_SIMULATION => EXAMPLE_SIMULATION,
1405  GT_TYPE => "GTX", --GTX or GTH or GTP
1406  EQ_MODE => "DFE", --Rx Equalization Mode - Set to DFE or LPM
1407  STABLE_CLOCK_PERIOD => STABLE_CLOCK_PERIOD, --Period of the stable clock driving this state-machine, unit is [ns]
1408  RETRY_COUNTER_BITWIDTH => 8,
1409  TX_QPLL_USED => TRUE , -- the TX and RX Reset FSMs must
1410  RX_QPLL_USED => TRUE, -- share these two generic values
1411  PHASE_ALIGNMENT_MANUAL => FALSE -- Decision if a manual phase-alignment is necessary or the automatic
1412  -- is enough. For single-lane applications the automatic alignment is
1413  -- sufficient
1414  )
1415  port map (
1416  STABLE_CLOCK => SYSCLK_IN,
1417  RXUSERCLK => GT2_RXUSRCLK_IN,
1418  SOFT_RESET => SOFT_RESET_IN,
1419  DONT_RESET_ON_DATA_ERROR => DONT_RESET_ON_DATA_ERROR_IN,
1420  QPLLREFCLKLOST => gt0_qpllrefclklost_i ,
1421  CPLLREFCLKLOST => tied_to_ground_i,
1422  QPLLLOCK => gt0_qplllock_i,
1423  CPLLLOCK => tied_to_vcc_i,
1424  RXRESETDONE => gt2_rxresetdone_i,
1425  MMCM_LOCK => tied_to_vcc_i,
1426  RECCLK_STABLE => gt2_recclk_stable_i ,
1427  RECCLK_MONITOR_RESTART => tied_to_ground_i,
1428  DATA_VALID => GT2_DATA_VALID_IN,
1429  TXUSERRDY => tied_to_vcc_i,
1430  GTRXRESET => gt2_gtrxreset_t,
1431  MMCM_RESET => open,
1432  QPLL_RESET => open,
1433  CPLL_RESET => open,
1434  RX_FSM_RESET_DONE => GT2_RX_FSM_RESET_DONE_OUT,
1435  RXUSERRDY => gt2_rxuserrdy_t,
1436  RUN_PHALIGNMENT => open,
1437  RESET_PHALIGNMENT => open,
1438  PHALIGNMENT_DONE => tied_to_vcc_i,
1439  RXDFEAGCHOLD => gt2_rxdfeagchold_i,
1440  RXDFELFHOLD => gt2_rxdfelfhold_i,
1441  RXLPMLFHOLD => gt2_rxlpmlfhold_i,
1442  RXLPMHFHOLD => gt2_rxlpmhfhold_i,
1443  RETRY_COUNTER => open
1444  );
1445 end generate;
1446 
1447 
1448  cdrlock_timeout:process(SYSCLK_IN)
1449  begin
1450  if rising_edge(SYSCLK_IN) then
1451  if(gt0_gtrxreset_i = '1') then
1452  rx_cdrlocked <= '0';
1453  rx_cdrlock_counter <= 0 after DLY;
1454  elsif (rx_cdrlock_counter = WAIT_TIME_CDRLOCK) then
1455  rx_cdrlocked <= '1';
1456  rx_cdrlock_counter <= rx_cdrlock_counter after DLY;
1457  else
1458  rx_cdrlock_counter <= rx_cdrlock_counter + 1 after DLY;
1459  end if;
1460  end if;
1461  end process;
1462 
1463 gt0_recclk_stable_i <= rx_cdrlocked;
1464 gt1_recclk_stable_i <= rx_cdrlocked;
1465 gt2_recclk_stable_i <= rx_cdrlocked;
1466 
1467 
1468 
1469 
1470 
1471 
1472 
1473 end RTL;
1474 
1475 
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