RTL Architecture Reference

List of all members.

Functions
integer	get_cdrlock_time ( is_sim: in in integer )

Processes
cdrlock_timeout	( SYSCLK_IN )

Components
SFP3_v2_7	<Entity SFP3_v2_7>
SFP3_v2_7_TX_STARTUP_FSM	<Entity SFP3_v2_7_TX_STARTUP_FSM>
SFP3_v2_7_RX_STARTUP_FSM	<Entity SFP3_v2_7_RX_STARTUP_FSM>

Constants
DLY	time := 1 ns
RX_CDRLOCK_TIME	integer := get_cdrlock_time ( EXAMPLE_SIMULATION )
WAIT_TIME_CDRLOCK	integer := RX_CDRLOCK_TIME /STABLE_CLOCK_PERIOD

Signals
gt0_txresetdone_i	std_logic
gt0_rxresetdone_i	std_logic
gt0_gttxreset_i	std_logic
gt0_gttxreset_t	std_logic
gt0_gtrxreset_i	std_logic
gt0_gtrxreset_t	std_logic
gt0_txpcsreset_i	std_logic
gt0_rxpcsreset_i	std_logic
gt0_rxdfelpmreset_i	std_logic
gt0_txuserrdy_i	std_logic
gt0_txuserrdy_t	std_logic
gt0_rxuserrdy_i	std_logic
gt0_rxuserrdy_t	std_logic
gt0_rxdfeagchold_i	std_logic
gt0_rxdfelfhold_i	std_logic
gt0_rxlpmlfhold_i	std_logic
gt0_rxlpmhfhold_i	std_logic
gt1_txresetdone_i	std_logic
gt1_rxresetdone_i	std_logic
gt1_gttxreset_i	std_logic
gt1_gttxreset_t	std_logic
gt1_gtrxreset_i	std_logic
gt1_gtrxreset_t	std_logic
gt1_txpcsreset_i	std_logic
gt1_rxpcsreset_i	std_logic
gt1_rxdfelpmreset_i	std_logic
gt1_txuserrdy_i	std_logic
gt1_txuserrdy_t	std_logic
gt1_rxuserrdy_i	std_logic
gt1_rxuserrdy_t	std_logic
gt1_rxdfeagchold_i	std_logic
gt1_rxdfelfhold_i	std_logic
gt1_rxlpmlfhold_i	std_logic
gt1_rxlpmhfhold_i	std_logic
gt2_txresetdone_i	std_logic
gt2_rxresetdone_i	std_logic
gt2_gttxreset_i	std_logic
gt2_gttxreset_t	std_logic
gt2_gtrxreset_i	std_logic
gt2_gtrxreset_t	std_logic
gt2_txpcsreset_i	std_logic
gt2_rxpcsreset_i	std_logic
gt2_rxdfelpmreset_i	std_logic
gt2_txuserrdy_i	std_logic
gt2_txuserrdy_t	std_logic
gt2_rxuserrdy_i	std_logic
gt2_rxuserrdy_t	std_logic
gt2_rxdfeagchold_i	std_logic
gt2_rxdfelfhold_i	std_logic
gt2_rxlpmlfhold_i	std_logic
gt2_rxlpmhfhold_i	std_logic
gt0_qpllreset_i	std_logic
gt0_qpllreset_t	std_logic
gt0_qpllrefclklost_i	std_logic
gt0_qplllock_i	std_logic
tied_to_ground_i	std_logic
tied_to_vcc_i	std_logic
gt0_rxoutclk_i	std_logic
gt0_recclk_stable_i	std_logic
gt1_rxoutclk_i	std_logic
gt1_recclk_stable_i	std_logic
gt2_rxoutclk_i	std_logic
gt2_recclk_stable_i	std_logic
rx_cdrlock_counter	integer range 0 to WAIT_TIME_CDRLOCK := 0
rx_cdrlocked	std_logic

Instantiations
SFP3_v2_7_i	SFP3_v2_7 <Entity SFP3_v2_7>
gt0_txresetfsm_i	SFP3_v2_7_TX_STARTUP_FSM <Entity SFP3_v2_7_TX_STARTUP_FSM>
gt1_txresetfsm_i	SFP3_v2_7_TX_STARTUP_FSM <Entity SFP3_v2_7_TX_STARTUP_FSM>
gt0_rxresetfsm_i	SFP3_v2_7_RX_STARTUP_FSM <Entity SFP3_v2_7_RX_STARTUP_FSM>
gt1_rxresetfsm_i	SFP3_v2_7_RX_STARTUP_FSM <Entity SFP3_v2_7_RX_STARTUP_FSM>
gt2_txresetfsm_i	SFP3_v2_7_TX_STARTUP_FSM <Entity SFP3_v2_7_TX_STARTUP_FSM>
gt2_rxresetfsm_i	SFP3_v2_7_RX_STARTUP_FSM <Entity SFP3_v2_7_RX_STARTUP_FSM>

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Detailed Description

Definition at line 355 of file sfp3_v2_7_init.vhd.

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The documentation for this class was generated from the following files:

• src/common_10G/SFP3/SFP3_v2_7/example_design/sfp3_v2_7_init.vhd