AMC13
Firmwares for the different applications of the AMC13 uTCA board made at Boston University
 All Classes Variables
serdes5gpdprod.vhd
1 -------------------------------------------------------------------------------
2 -- ____ ____
3 -- / /\/ /
4 -- /___/ \ / Vendor: Xilinx
5 -- \ \ \/ Version : 2.7
6 -- \ \ Application : 7 Series FPGAs Transceivers Wizard
7 -- / / Filename : serdes5gpdprod.vhd
8 -- /___/ /\
9 -- \ \ / \
10 -- \___\/\___\
11 --
12 --
13 -- Module serdes5GpdProd (a GT Wrapper)
14 -- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
15 --
16 --
17 -- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
18 --
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62 
63 
64 library ieee;
65 use ieee.std_logic_1164.all;
66 use ieee.numeric_std.all;
67 use work.amc13_pack.all;
68 library UNISIM;
69 use UNISIM.VCOMPONENTS.ALL;
70 
71 
72 --***************************** Entity Declaration ****************************
73 
74 entity serdes5GpdProd is
75 generic
76 (
77  QPLL_FBDIV_TOP : integer := 80;
78 
79  -- Simulation attributes
80  WRAPPER_SIM_GTRESET_SPEEDUP : string := "FALSE"; -- Set to "true" to speed up sim reset
81  RX_DFE_KL_CFG2_IN : bit_vector := X"301148AC";
82  PMA_RSV_IN : bit_vector := x"001E7080"
83 
84 );
85 port
86 (
87  --_________________________________________________________________________
88  --_________________________________________________________________________
89  --GT0 (X0Y12)
90  --____________________________CHANNEL PORTS________________________________
91  ---------------------------- Channel - DRP Ports --------------------------
92  GT0_DRPADDR_IN : in std_logic_vector(8 downto 0);
93  GT0_DRPCLK_IN : in std_logic;
94  GT0_DRPDI_IN : in std_logic_vector(15 downto 0);
95  GT0_DRPDO_OUT : out std_logic_vector(15 downto 0);
96  GT0_DRPEN_IN : in std_logic;
97  GT0_DRPRDY_OUT : out std_logic;
98  GT0_DRPWE_IN : in std_logic;
99  ------------------------------ Power-Down Ports ----------------------------
100  GT0_RXPD_IN : in std_logic_vector(1 downto 0);
101  GT0_TXPD_IN : in std_logic_vector(1 downto 0);
102  --------------------- RX Initialization and Reset Ports --------------------
103  GT0_RXUSERRDY_IN : in std_logic;
104  -------------------------- RX Margin Analysis Ports ------------------------
105  GT0_EYESCANDATAERROR_OUT : out std_logic;
106  ------------------------- Receive Ports - CDR Ports ------------------------
107  GT0_RXCDRLOCK_OUT : out std_logic;
108  ------------------- Receive Ports - Clock Correction Ports -----------------
109  GT0_RXCLKCORCNT_OUT : out std_logic_vector(1 downto 0);
110  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
111  GT0_RXUSRCLK_IN : in std_logic;
112  GT0_RXUSRCLK2_IN : in std_logic;
113  ------------------ Receive Ports - FPGA RX interface Ports -----------------
114  GT0_RXDATA_OUT : out std_logic_vector(31 downto 0);
115  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
116  GT0_RXDISPERR_OUT : out std_logic_vector(3 downto 0);
117  GT0_RXNOTINTABLE_OUT : out std_logic_vector(3 downto 0);
118  --------------------------- Receive Ports - RX AFE -------------------------
119  GT0_GTXRXP_IN : in std_logic;
120  ------------------------ Receive Ports - RX AFE Ports ----------------------
121  GT0_GTXRXN_IN : in std_logic;
122  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
123  GT0_RXBUFSTATUS_OUT : out std_logic_vector(2 downto 0);
124  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
125  GT0_RXBYTEISALIGNED_OUT : out std_logic;
126  GT0_RXBYTEREALIGN_OUT : out std_logic;
127  GT0_RXCOMMADET_OUT : out std_logic;
128  GT0_RXMCOMMAALIGNEN_IN : in std_logic;
129  GT0_RXPCOMMAALIGNEN_IN : in std_logic;
130  --------------------- Receive Ports - RX Equalizer Ports -------------------
131  GT0_RXDFEAGCHOLD_IN : in std_logic;
132  GT0_RXDFELFHOLD_IN : in std_logic;
133  --------------- Receive Ports - RX Fabric Output Control Ports -------------
134  GT0_RXOUTCLK_OUT : out std_logic;
135  ------------- Receive Ports - RX Initialization and Reset Ports ------------
136  GT0_GTRXRESET_IN : in std_logic;
137  GT0_RXPMARESET_IN : in std_logic;
138  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
139  GT0_RXCHARISCOMMA_OUT : out std_logic_vector(3 downto 0);
140  GT0_RXCHARISK_OUT : out std_logic_vector(3 downto 0);
141  -------------- Receive Ports -RX Initialization and Reset Ports ------------
142  GT0_RXRESETDONE_OUT : out std_logic;
143  --------------------- TX Initialization and Reset Ports --------------------
144  GT0_GTTXRESET_IN : in std_logic;
145  GT0_TXUSERRDY_IN : in std_logic;
146  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
147  GT0_TXUSRCLK_IN : in std_logic;
148  GT0_TXUSRCLK2_IN : in std_logic;
149  ------------------ Transmit Ports - TX Data Path interface -----------------
150  GT0_TXDATA_IN : in std_logic_vector(31 downto 0);
151  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
152  GT0_GTXTXN_OUT : out std_logic;
153  GT0_GTXTXP_OUT : out std_logic;
154  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
155  GT0_TXOUTCLK_OUT : out std_logic;
156  GT0_TXOUTCLKFABRIC_OUT : out std_logic;
157  GT0_TXOUTCLKPCS_OUT : out std_logic;
158  --------------------- Transmit Ports - TX Gearbox Ports --------------------
159  GT0_TXCHARISK_IN : in std_logic_vector(3 downto 0);
160  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
161  GT0_TXRESETDONE_OUT : out std_logic;
162 
163  --GT1 (X0Y13)
164  --____________________________CHANNEL PORTS________________________________
165  ---------------------------- Channel - DRP Ports --------------------------
166  GT1_DRPADDR_IN : in std_logic_vector(8 downto 0);
167  GT1_DRPCLK_IN : in std_logic;
168  GT1_DRPDI_IN : in std_logic_vector(15 downto 0);
169  GT1_DRPDO_OUT : out std_logic_vector(15 downto 0);
170  GT1_DRPEN_IN : in std_logic;
171  GT1_DRPRDY_OUT : out std_logic;
172  GT1_DRPWE_IN : in std_logic;
173  ------------------------------ Power-Down Ports ----------------------------
174  GT1_RXPD_IN : in std_logic_vector(1 downto 0);
175  GT1_TXPD_IN : in std_logic_vector(1 downto 0);
176  --------------------- RX Initialization and Reset Ports --------------------
177  GT1_RXUSERRDY_IN : in std_logic;
178  -------------------------- RX Margin Analysis Ports ------------------------
179  GT1_EYESCANDATAERROR_OUT : out std_logic;
180  ------------------------- Receive Ports - CDR Ports ------------------------
181  GT1_RXCDRLOCK_OUT : out std_logic;
182  ------------------- Receive Ports - Clock Correction Ports -----------------
183  GT1_RXCLKCORCNT_OUT : out std_logic_vector(1 downto 0);
184  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
185  GT1_RXUSRCLK_IN : in std_logic;
186  GT1_RXUSRCLK2_IN : in std_logic;
187  ------------------ Receive Ports - FPGA RX interface Ports -----------------
188  GT1_RXDATA_OUT : out std_logic_vector(31 downto 0);
189  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
190  GT1_RXDISPERR_OUT : out std_logic_vector(3 downto 0);
191  GT1_RXNOTINTABLE_OUT : out std_logic_vector(3 downto 0);
192  --------------------------- Receive Ports - RX AFE -------------------------
193  GT1_GTXRXP_IN : in std_logic;
194  ------------------------ Receive Ports - RX AFE Ports ----------------------
195  GT1_GTXRXN_IN : in std_logic;
196  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
197  GT1_RXBUFSTATUS_OUT : out std_logic_vector(2 downto 0);
198  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
199  GT1_RXBYTEISALIGNED_OUT : out std_logic;
200  GT1_RXBYTEREALIGN_OUT : out std_logic;
201  GT1_RXCOMMADET_OUT : out std_logic;
202  GT1_RXMCOMMAALIGNEN_IN : in std_logic;
203  GT1_RXPCOMMAALIGNEN_IN : in std_logic;
204  --------------------- Receive Ports - RX Equalizer Ports -------------------
205  GT1_RXDFEAGCHOLD_IN : in std_logic;
206  GT1_RXDFELFHOLD_IN : in std_logic;
207  --------------- Receive Ports - RX Fabric Output Control Ports -------------
208  GT1_RXOUTCLK_OUT : out std_logic;
209  ------------- Receive Ports - RX Initialization and Reset Ports ------------
210  GT1_GTRXRESET_IN : in std_logic;
211  GT1_RXPMARESET_IN : in std_logic;
212  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
213  GT1_RXCHARISCOMMA_OUT : out std_logic_vector(3 downto 0);
214  GT1_RXCHARISK_OUT : out std_logic_vector(3 downto 0);
215  -------------- Receive Ports -RX Initialization and Reset Ports ------------
216  GT1_RXRESETDONE_OUT : out std_logic;
217  --------------------- TX Initialization and Reset Ports --------------------
218  GT1_GTTXRESET_IN : in std_logic;
219  GT1_TXUSERRDY_IN : in std_logic;
220  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
221  GT1_TXUSRCLK_IN : in std_logic;
222  GT1_TXUSRCLK2_IN : in std_logic;
223  ------------------ Transmit Ports - TX Data Path interface -----------------
224  GT1_TXDATA_IN : in std_logic_vector(31 downto 0);
225  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
226  GT1_GTXTXN_OUT : out std_logic;
227  GT1_GTXTXP_OUT : out std_logic;
228  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
229  GT1_TXOUTCLK_OUT : out std_logic;
230  GT1_TXOUTCLKFABRIC_OUT : out std_logic;
231  GT1_TXOUTCLKPCS_OUT : out std_logic;
232  --------------------- Transmit Ports - TX Gearbox Ports --------------------
233  GT1_TXCHARISK_IN : in std_logic_vector(3 downto 0);
234  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
235  GT1_TXRESETDONE_OUT : out std_logic;
236 
237  --GT2 (X0Y14)
238  --____________________________CHANNEL PORTS________________________________
239  ---------------------------- Channel - DRP Ports --------------------------
240  GT2_DRPADDR_IN : in std_logic_vector(8 downto 0);
241  GT2_DRPCLK_IN : in std_logic;
242  GT2_DRPDI_IN : in std_logic_vector(15 downto 0);
243  GT2_DRPDO_OUT : out std_logic_vector(15 downto 0);
244  GT2_DRPEN_IN : in std_logic;
245  GT2_DRPRDY_OUT : out std_logic;
246  GT2_DRPWE_IN : in std_logic;
247  ------------------------------ Power-Down Ports ----------------------------
248  GT2_RXPD_IN : in std_logic_vector(1 downto 0);
249  GT2_TXPD_IN : in std_logic_vector(1 downto 0);
250  --------------------- RX Initialization and Reset Ports --------------------
251  GT2_RXUSERRDY_IN : in std_logic;
252  -------------------------- RX Margin Analysis Ports ------------------------
253  GT2_EYESCANDATAERROR_OUT : out std_logic;
254  ------------------------- Receive Ports - CDR Ports ------------------------
255  GT2_RXCDRLOCK_OUT : out std_logic;
256  ------------------- Receive Ports - Clock Correction Ports -----------------
257  GT2_RXCLKCORCNT_OUT : out std_logic_vector(1 downto 0);
258  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
259  GT2_RXUSRCLK_IN : in std_logic;
260  GT2_RXUSRCLK2_IN : in std_logic;
261  ------------------ Receive Ports - FPGA RX interface Ports -----------------
262  GT2_RXDATA_OUT : out std_logic_vector(31 downto 0);
263  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
264  GT2_RXDISPERR_OUT : out std_logic_vector(3 downto 0);
265  GT2_RXNOTINTABLE_OUT : out std_logic_vector(3 downto 0);
266  --------------------------- Receive Ports - RX AFE -------------------------
267  GT2_GTXRXP_IN : in std_logic;
268  ------------------------ Receive Ports - RX AFE Ports ----------------------
269  GT2_GTXRXN_IN : in std_logic;
270  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
271  GT2_RXBUFSTATUS_OUT : out std_logic_vector(2 downto 0);
272  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
273  GT2_RXBYTEISALIGNED_OUT : out std_logic;
274  GT2_RXBYTEREALIGN_OUT : out std_logic;
275  GT2_RXCOMMADET_OUT : out std_logic;
276  GT2_RXMCOMMAALIGNEN_IN : in std_logic;
277  GT2_RXPCOMMAALIGNEN_IN : in std_logic;
278  --------------------- Receive Ports - RX Equalizer Ports -------------------
279  GT2_RXDFEAGCHOLD_IN : in std_logic;
280  GT2_RXDFELFHOLD_IN : in std_logic;
281  --------------- Receive Ports - RX Fabric Output Control Ports -------------
282  GT2_RXOUTCLK_OUT : out std_logic;
283  ------------- Receive Ports - RX Initialization and Reset Ports ------------
284  GT2_GTRXRESET_IN : in std_logic;
285  GT2_RXPMARESET_IN : in std_logic;
286  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
287  GT2_RXCHARISCOMMA_OUT : out std_logic_vector(3 downto 0);
288  GT2_RXCHARISK_OUT : out std_logic_vector(3 downto 0);
289  -------------- Receive Ports -RX Initialization and Reset Ports ------------
290  GT2_RXRESETDONE_OUT : out std_logic;
291  --------------------- TX Initialization and Reset Ports --------------------
292  GT2_GTTXRESET_IN : in std_logic;
293  GT2_TXUSERRDY_IN : in std_logic;
294  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
295  GT2_TXUSRCLK_IN : in std_logic;
296  GT2_TXUSRCLK2_IN : in std_logic;
297  ------------------ Transmit Ports - TX Data Path interface -----------------
298  GT2_TXDATA_IN : in std_logic_vector(31 downto 0);
299  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
300  GT2_GTXTXN_OUT : out std_logic;
301  GT2_GTXTXP_OUT : out std_logic;
302  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
303  GT2_TXOUTCLK_OUT : out std_logic;
304  GT2_TXOUTCLKFABRIC_OUT : out std_logic;
305  GT2_TXOUTCLKPCS_OUT : out std_logic;
306  --------------------- Transmit Ports - TX Gearbox Ports --------------------
307  GT2_TXCHARISK_IN : in std_logic_vector(3 downto 0);
308  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
309  GT2_TXRESETDONE_OUT : out std_logic;
310 
311 
312  --____________________________COMMON PORTS________________________________
313  ---------------------- Common Block - Ref Clock Ports ---------------------
314  GT0_GTREFCLK0_COMMON_IN : in std_logic;
315  ------------------------- Common Block - QPLL Ports ------------------------
316  GT0_QPLLLOCK_OUT : out std_logic;
317  GT0_QPLLLOCKDETCLK_IN : in std_logic;
318  GT0_QPLLREFCLKLOST_OUT : out std_logic;
319  GT0_QPLLRESET_IN : in std_logic
320 
321 
322 );
323 
324 
325 end serdes5GpdProd;
326 
327 architecture RTL of serdes5GpdProd is
328 
329  attribute CORE_GENERATION_INFO : string;
330  attribute CORE_GENERATION_INFO of RTL : architecture is "serdes5GpdProd,gtwizard_v2_7,{protocol_file=Start_from_scratch}";
331 
332 
333 --***********************************Parameter Declarations********************
334 
335  constant DLY : time := 1 ns;
336 
337 --***************************** Signal Declarations *****************************
338 
339  -- ground and tied_to_vcc_i signals
340  signal tied_to_ground_i : std_logic;
341  signal tied_to_ground_vec_i : std_logic_vector(63 downto 0);
342  signal tied_to_vcc_i : std_logic;
343  signal gt0_qplloutclk_i : std_logic;
344  signal gt0_qplloutrefclk_i : std_logic;
345 
346 
347  signal gt0_mgtrefclktx_i : std_logic_vector(1 downto 0);
348  signal gt0_mgtrefclkrx_i : std_logic_vector(1 downto 0);
349 
350  signal gt1_mgtrefclktx_i : std_logic_vector(1 downto 0);
351  signal gt1_mgtrefclkrx_i : std_logic_vector(1 downto 0);
352 
353  signal gt2_mgtrefclktx_i : std_logic_vector(1 downto 0);
354  signal gt2_mgtrefclkrx_i : std_logic_vector(1 downto 0);
355 
356 
357  signal gt0_qpllclk_i : std_logic;
358  signal gt0_qpllrefclk_i : std_logic;
359  signal gt1_qpllclk_i : std_logic;
360  signal gt1_qpllrefclk_i : std_logic;
361  signal gt2_qpllclk_i : std_logic;
362  signal gt2_qpllrefclk_i : std_logic;
363 
364 
365 --*************************** Component Declarations **************************
366 component serdes5GpdProd_GT
367 generic
368 (
369  -- Simulation attributes
370  GT_SIM_GTRESET_SPEEDUP : string := "FALSE";
371  RX_DFE_KL_CFG2_IN : bit_vector := X"3010D90C";
372  PMA_RSV_IN : bit_vector := X"00000000";
373  PCS_RSVD_ATTR_IN : bit_vector := X"000000000000"
374 );
375 port
376 (
377  ---------------------------- Channel - DRP Ports --------------------------
378  DRPADDR_IN : in std_logic_vector(8 downto 0);
379  DRPCLK_IN : in std_logic;
380  DRPDI_IN : in std_logic_vector(15 downto 0);
381  DRPDO_OUT : out std_logic_vector(15 downto 0);
382  DRPEN_IN : in std_logic;
383  DRPRDY_OUT : out std_logic;
384  DRPWE_IN : in std_logic;
385  ------------------------------- Clocking Ports -----------------------------
386  QPLLCLK_IN : in std_logic;
387  QPLLREFCLK_IN : in std_logic;
388  ------------------------------ Power-Down Ports ----------------------------
389  RXPD_IN : in std_logic_vector(1 downto 0);
390  TXPD_IN : in std_logic_vector(1 downto 0);
391  --------------------- RX Initialization and Reset Ports --------------------
392  RXUSERRDY_IN : in std_logic;
393  -------------------------- RX Margin Analysis Ports ------------------------
394  EYESCANDATAERROR_OUT : out std_logic;
395  ------------------------- Receive Ports - CDR Ports ------------------------
396  RXCDRLOCK_OUT : out std_logic;
397  ------------------- Receive Ports - Clock Correction Ports -----------------
398  RXCLKCORCNT_OUT : out std_logic_vector(1 downto 0);
399  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
400  RXUSRCLK_IN : in std_logic;
401  RXUSRCLK2_IN : in std_logic;
402  ------------------ Receive Ports - FPGA RX interface Ports -----------------
403  RXDATA_OUT : out std_logic_vector(31 downto 0);
404  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
405  RXDISPERR_OUT : out std_logic_vector(3 downto 0);
406  RXNOTINTABLE_OUT : out std_logic_vector(3 downto 0);
407  --------------------------- Receive Ports - RX AFE -------------------------
408  GTXRXP_IN : in std_logic;
409  ------------------------ Receive Ports - RX AFE Ports ----------------------
410  GTXRXN_IN : in std_logic;
411  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
412  RXBUFSTATUS_OUT : out std_logic_vector(2 downto 0);
413  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
414  RXBYTEISALIGNED_OUT : out std_logic;
415  RXBYTEREALIGN_OUT : out std_logic;
416  RXCOMMADET_OUT : out std_logic;
417  RXMCOMMAALIGNEN_IN : in std_logic;
418  RXPCOMMAALIGNEN_IN : in std_logic;
419  --------------------- Receive Ports - RX Equalizer Ports -------------------
420  RXDFEAGCHOLD_IN : in std_logic;
421  RXDFELFHOLD_IN : in std_logic;
422  --------------- Receive Ports - RX Fabric Output Control Ports -------------
423  RXOUTCLK_OUT : out std_logic;
424  ------------- Receive Ports - RX Initialization and Reset Ports ------------
425  GTRXRESET_IN : in std_logic;
426  RXPMARESET_IN : in std_logic;
427  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
428  RXCHARISCOMMA_OUT : out std_logic_vector(3 downto 0);
429  RXCHARISK_OUT : out std_logic_vector(3 downto 0);
430  -------------- Receive Ports -RX Initialization and Reset Ports ------------
431  RXRESETDONE_OUT : out std_logic;
432  --------------------- TX Initialization and Reset Ports --------------------
433  GTTXRESET_IN : in std_logic;
434  TXUSERRDY_IN : in std_logic;
435  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
436  TXUSRCLK_IN : in std_logic;
437  TXUSRCLK2_IN : in std_logic;
438  ------------------ Transmit Ports - TX Data Path interface -----------------
439  TXDATA_IN : in std_logic_vector(31 downto 0);
440  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
441  GTXTXN_OUT : out std_logic;
442  GTXTXP_OUT : out std_logic;
443  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
444  TXOUTCLK_OUT : out std_logic;
445  TXOUTCLKFABRIC_OUT : out std_logic;
446  TXOUTCLKPCS_OUT : out std_logic;
447  --------------------- Transmit Ports - TX Gearbox Ports --------------------
448  TXCHARISK_IN : in std_logic_vector(3 downto 0);
449  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
450  TXRESETDONE_OUT : out std_logic
451 
452 
453 );
454 end component;
455 
456 
457 
458 --*************************Logic to set Attribute QPLL_FB_DIV*****************************
459  impure function conv_qpll_fbdiv_top (qpllfbdiv_top : in integer) return bit_vector is
460  begin
461  if (qpllfbdiv_top = 16) then
462  return "0000100000";
463  elsif (qpllfbdiv_top = 20) then
464  return "0000110000" ;
465  elsif (qpllfbdiv_top = 32) then
466  return "0001100000" ;
467  elsif (qpllfbdiv_top = 40) then
468  return "0010000000" ;
469  elsif (qpllfbdiv_top = 64) then
470  return "0011100000" ;
471  elsif (qpllfbdiv_top = 66) then
472  return "0101000000" ;
473  elsif (qpllfbdiv_top = 80) then
474  return "0100100000" ;
475  elsif (qpllfbdiv_top = 100) then
476  return "0101110000" ;
477  else
478  return "0000000000" ;
479  end if;
480  end function;
481 
482  impure function conv_qpll_fbdiv_ratio (qpllfbdiv_top : in integer) return bit is
483  begin
484  if (qpllfbdiv_top = 16) then
485  return '1';
486  elsif (qpllfbdiv_top = 20) then
487  return '1' ;
488  elsif (qpllfbdiv_top = 32) then
489  return '1' ;
490  elsif (qpllfbdiv_top = 40) then
491  return '1' ;
492  elsif (qpllfbdiv_top = 64) then
493  return '1' ;
494  elsif (qpllfbdiv_top = 66) then
495  return '0' ;
496  elsif (qpllfbdiv_top = 80) then
497  return '1' ;
498  elsif (qpllfbdiv_top = 100) then
499  return '1' ;
500  else
501  return '1' ;
502  end if;
503  end function;
504 
505  constant QPLL_FBDIV_IN : bit_vector(9 downto 0) := conv_qpll_fbdiv_top(QPLL_FBDIV_TOP);
506  constant QPLL_FBDIV_RATIO : bit := conv_qpll_fbdiv_ratio(QPLL_FBDIV_TOP);
507 
508 --********************************* Main Body of Code**************************
509 
510 begin
511 
512  tied_to_ground_i <= '0';
513  tied_to_ground_vec_i(63 downto 0) <= (others => '0');
514  tied_to_vcc_i <= '1';
515  gt0_qpllclk_i <= gt0_qplloutclk_i;
516  gt0_qpllrefclk_i <= gt0_qplloutrefclk_i;
517 
518  gt1_qpllclk_i <= gt0_qplloutclk_i;
519  gt1_qpllrefclk_i <= gt0_qplloutrefclk_i;
520 
521  gt2_qpllclk_i <= gt0_qplloutclk_i;
522  gt2_qpllrefclk_i <= gt0_qplloutrefclk_i;
523 
524 
525 
526  --------------------------- GT Instances -------------------------------
527 
528  --_________________________________________________________________________
529  --_________________________________________________________________________
530  --GT0 (X0Y12)
531 
532  gt0_serdes5GpdProd_i : serdes5GpdProd_GT
533  generic map
534  (
535  -- Simulation attributes
536  GT_SIM_GTRESET_SPEEDUP => WRAPPER_SIM_GTRESET_SPEEDUP ,
537  RX_DFE_KL_CFG2_IN => RX_DFE_KL_CFG2_IN,
538  PMA_RSV_IN => PMA_RSV_IN,
539  PCS_RSVD_ATTR_IN => X"000000000000"
540  )
541  port map
542  (
543  ---------------------------- Channel - DRP Ports --------------------------
544  DRPADDR_IN => GT0_DRPADDR_IN,
545  DRPCLK_IN => GT0_DRPCLK_IN,
546  DRPDI_IN => GT0_DRPDI_IN,
547  DRPDO_OUT => GT0_DRPDO_OUT,
548  DRPEN_IN => GT0_DRPEN_IN,
549  DRPRDY_OUT => GT0_DRPRDY_OUT,
550  DRPWE_IN => GT0_DRPWE_IN,
551  ------------------------------- Clocking Ports -----------------------------
552  QPLLCLK_IN => gt0_qpllclk_i,
553  QPLLREFCLK_IN => gt0_qpllrefclk_i,
554  ------------------------------ Power-Down Ports ----------------------------
555  RXPD_IN => GT0_RXPD_IN,
556  TXPD_IN => GT0_TXPD_IN,
557  --------------------- RX Initialization and Reset Ports --------------------
558  RXUSERRDY_IN => GT0_RXUSERRDY_IN,
559  -------------------------- RX Margin Analysis Ports ------------------------
560  EYESCANDATAERROR_OUT => GT0_EYESCANDATAERROR_OUT,
561  ------------------------- Receive Ports - CDR Ports ------------------------
562  RXCDRLOCK_OUT => GT0_RXCDRLOCK_OUT,
563  ------------------- Receive Ports - Clock Correction Ports -----------------
564  RXCLKCORCNT_OUT => GT0_RXCLKCORCNT_OUT ,
565  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
566  RXUSRCLK_IN => GT0_RXUSRCLK_IN,
567  RXUSRCLK2_IN => GT0_RXUSRCLK2_IN,
568  ------------------ Receive Ports - FPGA RX interface Ports -----------------
569  RXDATA_OUT => GT0_RXDATA_OUT,
570  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
571  RXDISPERR_OUT => GT0_RXDISPERR_OUT,
572  RXNOTINTABLE_OUT => GT0_RXNOTINTABLE_OUT ,
573  --------------------------- Receive Ports - RX AFE -------------------------
574  GTXRXP_IN => GT0_GTXRXP_IN,
575  ------------------------ Receive Ports - RX AFE Ports ----------------------
576  GTXRXN_IN => GT0_GTXRXN_IN,
577  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
578  RXBUFSTATUS_OUT => GT0_RXBUFSTATUS_OUT ,
579  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
580  RXBYTEISALIGNED_OUT => GT0_RXBYTEISALIGNED_OUT ,
581  RXBYTEREALIGN_OUT => GT0_RXBYTEREALIGN_OUT ,
582  RXCOMMADET_OUT => GT0_RXCOMMADET_OUT,
583  RXMCOMMAALIGNEN_IN => GT0_RXMCOMMAALIGNEN_IN ,
584  RXPCOMMAALIGNEN_IN => GT0_RXPCOMMAALIGNEN_IN ,
585  --------------------- Receive Ports - RX Equalizer Ports -------------------
586  RXDFEAGCHOLD_IN => GT0_RXDFEAGCHOLD_IN ,
587  RXDFELFHOLD_IN => GT0_RXDFELFHOLD_IN,
588  --------------- Receive Ports - RX Fabric Output Control Ports -------------
589  RXOUTCLK_OUT => GT0_RXOUTCLK_OUT,
590  ------------- Receive Ports - RX Initialization and Reset Ports ------------
591  GTRXRESET_IN => GT0_GTRXRESET_IN,
592  RXPMARESET_IN => GT0_RXPMARESET_IN,
593  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
594  RXCHARISCOMMA_OUT => GT0_RXCHARISCOMMA_OUT ,
595  RXCHARISK_OUT => GT0_RXCHARISK_OUT,
596  -------------- Receive Ports -RX Initialization and Reset Ports ------------
597  RXRESETDONE_OUT => GT0_RXRESETDONE_OUT ,
598  --------------------- TX Initialization and Reset Ports --------------------
599  GTTXRESET_IN => GT0_GTTXRESET_IN,
600  TXUSERRDY_IN => GT0_TXUSERRDY_IN,
601  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
602  TXUSRCLK_IN => GT0_TXUSRCLK_IN,
603  TXUSRCLK2_IN => GT0_TXUSRCLK2_IN,
604  ------------------ Transmit Ports - TX Data Path interface -----------------
605  TXDATA_IN => GT0_TXDATA_IN,
606  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
607  GTXTXN_OUT => GT0_GTXTXN_OUT,
608  GTXTXP_OUT => GT0_GTXTXP_OUT,
609  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
610  TXOUTCLK_OUT => GT0_TXOUTCLK_OUT,
611  TXOUTCLKFABRIC_OUT => GT0_TXOUTCLKFABRIC_OUT ,
612  TXOUTCLKPCS_OUT => GT0_TXOUTCLKPCS_OUT ,
613  --------------------- Transmit Ports - TX Gearbox Ports --------------------
614  TXCHARISK_IN => GT0_TXCHARISK_IN,
615  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
616  TXRESETDONE_OUT => GT0_TXRESETDONE_OUT
617 
618  );
619 
620  --_________________________________________________________________________
621  --_________________________________________________________________________
622  --GT1 (X0Y13)
623 
624  gt1_serdes5GpdProd_i : serdes5GpdProd_GT
625  generic map
626  (
627  -- Simulation attributes
628  GT_SIM_GTRESET_SPEEDUP => WRAPPER_SIM_GTRESET_SPEEDUP ,
629  RX_DFE_KL_CFG2_IN => RX_DFE_KL_CFG2_IN,
630  PMA_RSV_IN => PMA_RSV_IN,
631  PCS_RSVD_ATTR_IN => X"000000000000"
632  )
633  port map
634  (
635  ---------------------------- Channel - DRP Ports --------------------------
636  DRPADDR_IN => GT1_DRPADDR_IN,
637  DRPCLK_IN => GT1_DRPCLK_IN,
638  DRPDI_IN => GT1_DRPDI_IN,
639  DRPDO_OUT => GT1_DRPDO_OUT,
640  DRPEN_IN => GT1_DRPEN_IN,
641  DRPRDY_OUT => GT1_DRPRDY_OUT,
642  DRPWE_IN => GT1_DRPWE_IN,
643  ------------------------------- Clocking Ports -----------------------------
644  QPLLCLK_IN => gt1_qpllclk_i,
645  QPLLREFCLK_IN => gt1_qpllrefclk_i,
646  ------------------------------ Power-Down Ports ----------------------------
647  RXPD_IN => GT1_RXPD_IN,
648  TXPD_IN => GT1_TXPD_IN,
649  --------------------- RX Initialization and Reset Ports --------------------
650  RXUSERRDY_IN => GT1_RXUSERRDY_IN,
651  -------------------------- RX Margin Analysis Ports ------------------------
652  EYESCANDATAERROR_OUT => GT1_EYESCANDATAERROR_OUT,
653  ------------------------- Receive Ports - CDR Ports ------------------------
654  RXCDRLOCK_OUT => GT1_RXCDRLOCK_OUT,
655  ------------------- Receive Ports - Clock Correction Ports -----------------
656  RXCLKCORCNT_OUT => GT1_RXCLKCORCNT_OUT ,
657  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
658  RXUSRCLK_IN => GT1_RXUSRCLK_IN,
659  RXUSRCLK2_IN => GT1_RXUSRCLK2_IN,
660  ------------------ Receive Ports - FPGA RX interface Ports -----------------
661  RXDATA_OUT => GT1_RXDATA_OUT,
662  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
663  RXDISPERR_OUT => GT1_RXDISPERR_OUT,
664  RXNOTINTABLE_OUT => GT1_RXNOTINTABLE_OUT ,
665  --------------------------- Receive Ports - RX AFE -------------------------
666  GTXRXP_IN => GT1_GTXRXP_IN,
667  ------------------------ Receive Ports - RX AFE Ports ----------------------
668  GTXRXN_IN => GT1_GTXRXN_IN,
669  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
670  RXBUFSTATUS_OUT => GT1_RXBUFSTATUS_OUT ,
671  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
672  RXBYTEISALIGNED_OUT => GT1_RXBYTEISALIGNED_OUT ,
673  RXBYTEREALIGN_OUT => GT1_RXBYTEREALIGN_OUT ,
674  RXCOMMADET_OUT => GT1_RXCOMMADET_OUT,
675  RXMCOMMAALIGNEN_IN => GT1_RXMCOMMAALIGNEN_IN ,
676  RXPCOMMAALIGNEN_IN => GT1_RXPCOMMAALIGNEN_IN ,
677  --------------------- Receive Ports - RX Equalizer Ports -------------------
678  RXDFEAGCHOLD_IN => GT1_RXDFEAGCHOLD_IN ,
679  RXDFELFHOLD_IN => GT1_RXDFELFHOLD_IN,
680  --------------- Receive Ports - RX Fabric Output Control Ports -------------
681  RXOUTCLK_OUT => GT1_RXOUTCLK_OUT,
682  ------------- Receive Ports - RX Initialization and Reset Ports ------------
683  GTRXRESET_IN => GT1_GTRXRESET_IN,
684  RXPMARESET_IN => GT1_RXPMARESET_IN,
685  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
686  RXCHARISCOMMA_OUT => GT1_RXCHARISCOMMA_OUT ,
687  RXCHARISK_OUT => GT1_RXCHARISK_OUT,
688  -------------- Receive Ports -RX Initialization and Reset Ports ------------
689  RXRESETDONE_OUT => GT1_RXRESETDONE_OUT ,
690  --------------------- TX Initialization and Reset Ports --------------------
691  GTTXRESET_IN => GT1_GTTXRESET_IN,
692  TXUSERRDY_IN => GT1_TXUSERRDY_IN,
693  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
694  TXUSRCLK_IN => GT1_TXUSRCLK_IN,
695  TXUSRCLK2_IN => GT1_TXUSRCLK2_IN,
696  ------------------ Transmit Ports - TX Data Path interface -----------------
697  TXDATA_IN => GT1_TXDATA_IN,
698  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
699  GTXTXN_OUT => GT1_GTXTXN_OUT,
700  GTXTXP_OUT => GT1_GTXTXP_OUT,
701  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
702  TXOUTCLK_OUT => GT1_TXOUTCLK_OUT,
703  TXOUTCLKFABRIC_OUT => GT1_TXOUTCLKFABRIC_OUT ,
704  TXOUTCLKPCS_OUT => GT1_TXOUTCLKPCS_OUT ,
705  --------------------- Transmit Ports - TX Gearbox Ports --------------------
706  TXCHARISK_IN => GT1_TXCHARISK_IN,
707  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
708  TXRESETDONE_OUT => GT1_TXRESETDONE_OUT
709 
710  );
711 
712  --_________________________________________________________________________
713  --_________________________________________________________________________
714  --GT2 (X0Y14)
715 g_gt2 : if (flavor /= "HCAL") generate
716  gt2_serdes5GpdProd_i : serdes5GpdProd_GT
717  generic map
718  (
719  -- Simulation attributes
720  GT_SIM_GTRESET_SPEEDUP => WRAPPER_SIM_GTRESET_SPEEDUP ,
721  RX_DFE_KL_CFG2_IN => RX_DFE_KL_CFG2_IN,
722  PMA_RSV_IN => PMA_RSV_IN,
723  PCS_RSVD_ATTR_IN => X"000000000000"
724  )
725  port map
726  (
727  ---------------------------- Channel - DRP Ports --------------------------
728  DRPADDR_IN => GT2_DRPADDR_IN,
729  DRPCLK_IN => GT2_DRPCLK_IN,
730  DRPDI_IN => GT2_DRPDI_IN,
731  DRPDO_OUT => GT2_DRPDO_OUT,
732  DRPEN_IN => GT2_DRPEN_IN,
733  DRPRDY_OUT => GT2_DRPRDY_OUT,
734  DRPWE_IN => GT2_DRPWE_IN,
735  ------------------------------- Clocking Ports -----------------------------
736  QPLLCLK_IN => gt2_qpllclk_i,
737  QPLLREFCLK_IN => gt2_qpllrefclk_i,
738  ------------------------------ Power-Down Ports ----------------------------
739  RXPD_IN => GT2_RXPD_IN,
740  TXPD_IN => GT2_TXPD_IN,
741  --------------------- RX Initialization and Reset Ports --------------------
742  RXUSERRDY_IN => GT2_RXUSERRDY_IN,
743  -------------------------- RX Margin Analysis Ports ------------------------
744  EYESCANDATAERROR_OUT => GT2_EYESCANDATAERROR_OUT,
745  ------------------------- Receive Ports - CDR Ports ------------------------
746  RXCDRLOCK_OUT => GT2_RXCDRLOCK_OUT,
747  ------------------- Receive Ports - Clock Correction Ports -----------------
748  RXCLKCORCNT_OUT => GT2_RXCLKCORCNT_OUT ,
749  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
750  RXUSRCLK_IN => GT2_RXUSRCLK_IN,
751  RXUSRCLK2_IN => GT2_RXUSRCLK2_IN,
752  ------------------ Receive Ports - FPGA RX interface Ports -----------------
753  RXDATA_OUT => GT2_RXDATA_OUT,
754  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
755  RXDISPERR_OUT => GT2_RXDISPERR_OUT,
756  RXNOTINTABLE_OUT => GT2_RXNOTINTABLE_OUT ,
757  --------------------------- Receive Ports - RX AFE -------------------------
758  GTXRXP_IN => GT2_GTXRXP_IN,
759  ------------------------ Receive Ports - RX AFE Ports ----------------------
760  GTXRXN_IN => GT2_GTXRXN_IN,
761  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
762  RXBUFSTATUS_OUT => GT2_RXBUFSTATUS_OUT ,
763  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
764  RXBYTEISALIGNED_OUT => GT2_RXBYTEISALIGNED_OUT ,
765  RXBYTEREALIGN_OUT => GT2_RXBYTEREALIGN_OUT ,
766  RXCOMMADET_OUT => GT2_RXCOMMADET_OUT,
767  RXMCOMMAALIGNEN_IN => GT2_RXMCOMMAALIGNEN_IN ,
768  RXPCOMMAALIGNEN_IN => GT2_RXPCOMMAALIGNEN_IN ,
769  --------------------- Receive Ports - RX Equalizer Ports -------------------
770  RXDFEAGCHOLD_IN => GT2_RXDFEAGCHOLD_IN ,
771  RXDFELFHOLD_IN => GT2_RXDFELFHOLD_IN,
772  --------------- Receive Ports - RX Fabric Output Control Ports -------------
773  RXOUTCLK_OUT => GT2_RXOUTCLK_OUT,
774  ------------- Receive Ports - RX Initialization and Reset Ports ------------
775  GTRXRESET_IN => GT2_GTRXRESET_IN,
776  RXPMARESET_IN => GT2_RXPMARESET_IN,
777  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
778  RXCHARISCOMMA_OUT => GT2_RXCHARISCOMMA_OUT ,
779  RXCHARISK_OUT => GT2_RXCHARISK_OUT,
780  -------------- Receive Ports -RX Initialization and Reset Ports ------------
781  RXRESETDONE_OUT => GT2_RXRESETDONE_OUT ,
782  --------------------- TX Initialization and Reset Ports --------------------
783  GTTXRESET_IN => GT2_GTTXRESET_IN,
784  TXUSERRDY_IN => GT2_TXUSERRDY_IN,
785  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
786  TXUSRCLK_IN => GT2_TXUSRCLK_IN,
787  TXUSRCLK2_IN => GT2_TXUSRCLK2_IN,
788  ------------------ Transmit Ports - TX Data Path interface -----------------
789  TXDATA_IN => GT2_TXDATA_IN,
790  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
791  GTXTXN_OUT => GT2_GTXTXN_OUT,
792  GTXTXP_OUT => GT2_GTXTXP_OUT,
793  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
794  TXOUTCLK_OUT => GT2_TXOUTCLK_OUT,
795  TXOUTCLKFABRIC_OUT => GT2_TXOUTCLKFABRIC_OUT ,
796  TXOUTCLKPCS_OUT => GT2_TXOUTCLKPCS_OUT ,
797  --------------------- Transmit Ports - TX Gearbox Ports --------------------
798  TXCHARISK_IN => GT2_TXCHARISK_IN,
799  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
800  TXRESETDONE_OUT => GT2_TXRESETDONE_OUT
801 
802  );
803 end generate g_gt2;
804  --_________________________________________________________________________
805  --_________________________________________________________________________
806  --_________________________GTXE2_COMMON____________________________________
807 
808  gtxe2_common_0_i : GTXE2_COMMON
809  generic map
810  (
811  -- Simulation attributes
812  SIM_RESET_SPEEDUP => WRAPPER_SIM_GTRESET_SPEEDUP ,
813  SIM_QPLLREFCLK_SEL => ("001"),
814  SIM_VERSION => "4.0",
815 
816 
817  ------------------COMMON BLOCK Attributes---------------
818  BIAS_CFG => (x"0000040000001000"),
819  COMMON_CFG => (x"00000000"),
820  QPLL_CFG => (x"0680181"),
821  QPLL_CLKOUT_CFG => ("0000"),
822  QPLL_COARSE_FREQ_OVRD => ("010000"),
823  QPLL_COARSE_FREQ_OVRD_EN => ('0'),
824  QPLL_CP => ("0000011111"),
825  QPLL_CP_MONITOR_EN => ('0'),
826  QPLL_DMONITOR_SEL => ('0'),
827  QPLL_FBDIV => (QPLL_FBDIV_IN),
828  QPLL_FBDIV_MONITOR_EN => ('0'),
829  QPLL_FBDIV_RATIO => (QPLL_FBDIV_RATIO),
830  QPLL_INIT_CFG => (x"000006"),
831  QPLL_LOCK_CFG => (x"21E8"),
832  QPLL_LPF => ("1111"),
833  QPLL_REFCLK_DIV => (1)
834 
835 
836  )
837  port map
838  (
839  ------------- Common Block - Dynamic Reconfiguration Port (DRP) -----------
840  DRPADDR => tied_to_ground_vec_i (7 downto 0),
841  DRPCLK => tied_to_ground_i,
842  DRPDI => tied_to_ground_vec_i (15 downto 0),
843  DRPDO => open,
844  DRPEN => tied_to_ground_i,
845  DRPRDY => open,
846  DRPWE => tied_to_ground_i,
847  ---------------------- Common Block - Ref Clock Ports ---------------------
848  GTGREFCLK => tied_to_ground_i,
849  GTNORTHREFCLK0 => tied_to_ground_i,
850  GTNORTHREFCLK1 => tied_to_ground_i,
851  GTREFCLK0 => GT0_GTREFCLK0_COMMON_IN ,
852  GTREFCLK1 => tied_to_ground_i,
853  GTSOUTHREFCLK0 => tied_to_ground_i,
854  GTSOUTHREFCLK1 => tied_to_ground_i,
855  ------------------------- Common Block - QPLL Ports -----------------------
856  QPLLDMONITOR => open,
857  ----------------------- Common Block - Clocking Ports ----------------------
858  QPLLOUTCLK => gt0_qplloutclk_i,
859  QPLLOUTREFCLK => gt0_qplloutrefclk_i ,
860  REFCLKOUTMONITOR => open,
861  ------------------------- Common Block - QPLL Ports ------------------------
862  QPLLFBCLKLOST => open,
863  QPLLLOCK => GT0_QPLLLOCK_OUT,
864  QPLLLOCKDETCLK => GT0_QPLLLOCKDETCLK_IN ,
865  QPLLLOCKEN => tied_to_vcc_i,
866  QPLLOUTRESET => tied_to_ground_i,
867  QPLLPD => tied_to_ground_i,
868  QPLLREFCLKLOST => GT0_QPLLREFCLKLOST_OUT ,
869  QPLLREFCLKSEL => "001",
870  QPLLRESET => GT0_QPLLRESET_IN,
871  QPLLRSVD1 => "0000000000000000",
872  QPLLRSVD2 => "11111",
873  --------------------------------- QPLL Ports -------------------------------
874  BGBYPASSB => tied_to_vcc_i,
875  BGMONITORENB => tied_to_vcc_i,
876  BGPDB => tied_to_vcc_i,
877  BGRCALOVRD => "00000",
878  PMARSVD => "00000000",
879  RCALENB => tied_to_vcc_i
880 
881  );
882 
883 
884 
885 end RTL;
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