RTL Architecture Reference

List of all members.

Functions
bit_vector	conv_qpll_fbdiv_top ( qpllfbdiv_top: in in integer )	[ impure ]
bit	conv_qpll_fbdiv_ratio ( qpllfbdiv_top: in in integer )	[ impure ]

Components
serdes5GpdProd_GT	<Entity serdes5GpdProd_GT>

Constants
DLY	time := 1 ns
QPLL_FBDIV_IN	bit_vector ( 9 downto 0 ) := conv_qpll_fbdiv_top ( QPLL_FBDIV_TOP )
QPLL_FBDIV_RATIO	bit := conv_qpll_fbdiv_ratio ( QPLL_FBDIV_TOP )

Signals
tied_to_ground_i	std_logic
tied_to_ground_vec_i	std_logic_vector ( 63 downto 0 )
tied_to_vcc_i	std_logic
gt0_qplloutclk_i	std_logic
gt0_qplloutrefclk_i	std_logic
gt0_mgtrefclktx_i	std_logic_vector ( 1 downto 0 )
gt0_mgtrefclkrx_i	std_logic_vector ( 1 downto 0 )
gt1_mgtrefclktx_i	std_logic_vector ( 1 downto 0 )
gt1_mgtrefclkrx_i	std_logic_vector ( 1 downto 0 )
gt2_mgtrefclktx_i	std_logic_vector ( 1 downto 0 )
gt2_mgtrefclkrx_i	std_logic_vector ( 1 downto 0 )
gt0_qpllclk_i	std_logic
gt0_qpllrefclk_i	std_logic
gt1_qpllclk_i	std_logic
gt1_qpllrefclk_i	std_logic
gt2_qpllclk_i	std_logic
gt2_qpllrefclk_i	std_logic

Attributes
CORE_GENERATION_INFO	string
CORE_GENERATION_INFO	RTL : architecture is " serdes5GpdProd , gtwizard_v2_7 , {protocol_file = Start_from_scratch} "

Instantiations
gt0_serdes5GpdProd_i	serdes5GpdProd_GT <Entity serdes5GpdProd_GT>
gt1_serdes5GpdProd_i	serdes5GpdProd_GT <Entity serdes5GpdProd_GT>
gt2_serdes5GpdProd_i	serdes5GpdProd_GT <Entity serdes5GpdProd_GT>

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Detailed Description

Definition at line 327 of file serdes5gpdprod.vhd.

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The documentation for this class was generated from the following file:

• src/CMS_DAQ_if/5Gb/serdes5gpdprod.vhd