behavioral Architecture Reference

List of all members.

Processes
PROCESS_151	( reset ,clock )

Signals
mem_r_d	std_logic_vector ( 63 downto 0 )
mem_r_c	std_logic_vector ( 7 downto 0 )
reg_d	std_logic_vector ( 63 downto 0 )
reg_c	std_logic_vector ( 7 downto 0 )
shift	std_logic

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Detailed Description

Definition at line 30 of file xaui_wd_align.vhd.

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The documentation for this class was generated from the following file:

• src/CMS_DAQ_if/10Gb/slink/xaui_wd_align.vhd