AMC13
Firmwares for the different applications of the AMC13 uTCA board made at Boston University
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xaui_wd_align.vhd
1 ------------------------------------------------------
2 -- XAUI 64-bit alignment or reorder
3 --
4 -- Ver 1.00
5 --
6 -- Dominique Gigi May 2015
7 ------------------------------------------------------
8 --
9 --
10 --
11 --
12 ------------------------------------------------------
13 LIBRARY ieee;
14 USE ieee.std_logic_1164.all;
15 use ieee.numeric_std.all;
16 use work.mydefs.all;
17 
18 entity xaui_wd_align is
19 
20 port (
21  reset : in std_logic;
22  clock : in std_logic;
23 
24  data_i : in std_logic_vector(63 downto 0);
25  ctrl_i : in std_logic_vector(7 downto 0);
26  data_o : out std_logic_vector(63 downto 0);
27  ctrl_o : out std_logic_vector(7 downto 0)
28  );
29 end xaui_wd_align;
30 architecture behavioral of xaui_wd_align is
31 
32 
33 signal mem_r_d : std_logic_vector(63 downto 0);
34 signal mem_r_c : std_logic_vector(7 downto 0);
35 signal reg_d : std_logic_vector(63 downto 0);
36 signal reg_c : std_logic_vector(7 downto 0);
37 signal shift : std_logic;
38 
39 --attribute mark_debug : string;
40 
41 --attribute mark_debug of shift : signal is "true";
42 --attribute mark_debug of reg_d, mem_r_d : signal is "true";
43 --attribute mark_debug of reg_c : signal is "true";
44 
45 begin
46 
47 process(reset,clock)
48 begin
49 if reset = '0' then
50  shift <= '0';
51 elsif rising_edge(clock) then
52 
53  if FPGA_Brand = "ALTERA" then
54  if shift = '1' then
55  reg_d(63 downto 56) <= data_i(55 downto 48);
56  reg_c(7) <= ctrl_i(6);
57  reg_d(55 downto 48) <= data_i(39 downto 32);
58  reg_c(6) <= ctrl_i(4);
59  reg_d(47 downto 40) <= data_i(23 downto 16);
60  reg_c(5) <= ctrl_i(2);
61  reg_d(39 downto 32) <= data_i(07 downto 00);
62  reg_c(4) <= ctrl_i(0);
63 
64  reg_d(31 downto 24) <= mem_r_d(63 downto 56);
65  reg_c(3) <= mem_r_c(7);
66  reg_d(23 downto 16) <= mem_r_d(47 downto 40);
67  reg_c(2) <= mem_r_c(5);
68  reg_d(15 downto 8) <= mem_r_d(31 downto 24);
69  reg_c(1) <= mem_r_c(3);
70  reg_d( 7 downto 0) <= mem_r_d(15 downto 08);
71  reg_c(0) <= mem_r_c(1);
72  else
73  reg_d(63 downto 56) <= data_i(63 downto 56);
74  reg_c(7) <= ctrl_i(7);
75  reg_d(55 downto 48) <= data_i(47 downto 40);
76  reg_c(6) <= ctrl_i(5);
77  reg_d(47 downto 40) <= data_i(31 downto 24);
78  reg_c(5) <= ctrl_i(3);
79  reg_d(39 downto 32) <= data_i(15 downto 08);
80  reg_c(4) <= ctrl_i(1);
81  reg_d(31 downto 24) <= data_i(55 downto 48);
82  reg_c(3) <= ctrl_i(6);
83  reg_d(23 downto 16) <= data_i(39 downto 32);
84  reg_c(2) <= ctrl_i(4);
85  reg_d(15 downto 8) <= data_i(23 downto 16);
86  reg_c(1) <= ctrl_i(2);
87  reg_d( 7 downto 0) <= data_i(07 downto 00);
88  reg_c(0) <= ctrl_i(0);
89  end if;
90 
91  if data_i( 7 downto 0) = x"FB" and ctrl_i(0) = '1' then
92  shift <= '0';
93  elsif data_i(15 downto 8) = x"FB" and ctrl_i(1) = '1' then
94  shift <= '1';
95  end if;
96 
97 
98  elsif FPGA_Brand = "XILINX" then
99  if shift = '1' then
100  reg_d(63 downto 32) <= data_i(31 downto 00);
101  reg_c(7 downto 4) <= ctrl_i(3 downto 0);
102 
103  reg_d(31 downto 0) <= mem_r_d(63 downto 32);
104  reg_c(3 downto 0) <= mem_r_c(7 downto 4);
105  else
106  reg_d <= mem_r_d;--data_i;
107  reg_c <= mem_r_c;--ctrl_i;
108  end if;
109 
110  if data_i( 7 downto 0) = x"FB" and ctrl_i(0) = '1' then
111  shift <= '0';
112  elsif data_i(39 downto 32) = x"FB" and ctrl_i(4) = '1' then
113  shift <= '1';
114  end if;
115 
116  end if;
117 
118 
119 
120  mem_r_d <= data_i;
121  mem_r_c <= ctrl_i;
122 
123 end if;
124 end process;
125 
126 data_o <= reg_d;
127 ctrl_o <= reg_c;
128 
129 end behavioral;
130 
131 
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