simple Architecture Reference

List of all members.

Processes
input_block	( mac_clk )
output_block	( mac_clk )
busy_block	( mac_clk )

Types
address_buf	array ( 2 ** BUFWIDTH - 1 downto 0 ) of std_logic_vector ( 12 downto 0

Signals
end_address_buf	address_buf
last_busy	std_logic

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Detailed Description

Definition at line 30 of file udp_rxram_shim.vhd.

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The documentation for this class was generated from the following file:

• src/common/IPBUS/ipbus_core/hdl/udp_rxram_shim.vhd