udp_rxram_shim Entity Reference

Inheritance diagram for udp_rxram_shim:

List of all members.

Entities
simple	architecture

Use Clauses
numeric_std

Generics
BUFWIDTH	natural := 0

Ports
mac_clk	in std_logic
rst_macclk	in std_logic
rxram_end_addr	in std_logic_vector ( 12 downto 0 )
rxram_send	in std_logic
rxram_write_buf	in std_logic_vector ( BUFWIDTH - 1 downto 0 )
rxram_req_send	in std_logic
rxram_send_buf	in std_logic_vector ( BUFWIDTH - 1 downto 0 )
rxram_busy	in std_logic
rxram_end_addr_x	out std_logic_vector ( 12 downto 0 )
rxram_send_x	out std_logic
rxram_sent	out std_logic

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Detailed Description

Definition at line 7 of file udp_rxram_shim.vhd.

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The documentation for this class was generated from the following file:

• src/common/IPBUS/ipbus_core/hdl/udp_rxram_shim.vhd