rtl Architecture Reference

List of all members.

Processes
pkt_done_ipb_clk	( ipb_clk )
pkt_done_mac_clk	( mac_clk )
req_send_mac_clk	( mac_clk )
req_send_buf_ipb_clk	( ipb_clk )
pkt_rdy_ipb_clk	( ipb_clk )
enable_mac_clk	( mac_clk )
rarp_mac_clk	( mac_clk )
we_mac_clk	( mac_clk )
rst_ipb_mac_clk	( mac_clk )
busy_mac_clk	( mac_clk )
busy_up_down_ipb_clk	( ipb_clk )
busy_ipb_clk	( ipb_clk )
rx_read_buffer_ipb_clk	( ipb_clk )
tx_write_buffer_ipb_clk	( ipb_clk )

Signals
req_send_tff	std_logic
busy_buf	std_logic
busy_up_tff	std_logic
busy_down_tff	std_logic
enable_buf	std_logic_vector ( 1 downto 0 )
rarp_buf	std_logic_vector ( 1 downto 0 )
we_buf	std_logic_vector ( 1 downto 0 )
rst_ipb_buf	std_logic_vector ( 1 downto 0 )
req_send_buf	std_logic_vector ( 2 downto 0 )
pkt_done_read_buf	std_logic_vector ( 2 downto 0 )
pkt_done_write_buf	std_logic_vector ( 2 downto 0 )
busy_up_buf	std_logic_vector ( 2 downto 0 )
busy_down_buf	std_logic_vector ( 2 downto 0 )
pkt_done_r_tff	std_logic_vector ( 2 downto 0 )
pkt_done_w_tff	std_logic_vector ( 2 downto 0 )
rx_read_buf_buf	std_logic_vector ( BUFWIDTH - 1 downto 0 )
tx_write_buf_buf	std_logic_vector ( BUFWIDTH - 1 downto 0 )

Attributes
KEEP	string
KEEP	busy_down_buf : signal is " TRUE "
KEEP	busy_up_buf : signal is " TRUE "
KEEP	enable_buf : signal is " TRUE "
KEEP	pkt_done_read_buf : signal is " TRUE "
KEEP	pkt_done_write_buf : signal is " TRUE "
KEEP	rarp_buf : signal is " TRUE "
KEEP	req_send_buf : signal is " TRUE "
KEEP	rst_ipb_buf : signal is " TRUE "
KEEP	rx_read_buf_buf : signal is " TRUE "
KEEP	tx_write_buf_buf : signal is " TRUE "
KEEP	we_buf : signal is " TRUE "

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Detailed Description

Definition at line 43 of file udp_clock_crossing_if.vhd.

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The documentation for this class was generated from the following file:

• src/common/IPBUS/ipbus_core/hdl/udp_clock_crossing_if.vhd