udp_clock_crossing_if Entity Reference

Inheritance diagram for udp_clock_crossing_if:

List of all members.

Entities
rtl	architecture

Use Clauses
numeric_std

Generics
BUFWIDTH	natural := 0

Ports
mac_clk	in std_logic
rst_macclk	in std_logic
busy_125	in std_logic
rx_read_buffer_125	in std_logic_vector ( BUFWIDTH - 1 downto 0 )
rx_req_send_125	in std_logic
tx_write_buffer_125	in std_logic_vector ( BUFWIDTH - 1 downto 0 )
enable_125	out std_logic
rarp_125	out std_logic
rst_ipb_125	out std_logic
rx_ram_sent	out std_logic
tx_ram_written	out std_logic
we_125	out std_logic
ipb_clk	in std_logic
rst_ipb	in std_logic
enable	in std_logic
pkt_done_read	in std_logic
pkt_done_write	in std_logic
RARP	in std_logic
we	in std_logic
busy	out std_logic
pkt_rdy	out std_logic
rx_read_buffer	out std_logic_vector ( BUFWIDTH - 1 downto 0 )
tx_write_buffer	out std_logic_vector ( BUFWIDTH - 1 downto 0 )

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Detailed Description

Definition at line 9 of file udp_clock_crossing_if.vhd.

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The documentation for this class was generated from the following file:

• src/common/IPBUS/ipbus_core/hdl/udp_clock_crossing_if.vhd