behavioral Architecture Reference

List of all members.

Processes
PROCESS_144	( Rst_Pciclk ,PCIe_clk )
PROCESS_145	( PCIe_clk )
PROCESS_146	( evt_clk )
PROCESS_147	( Rst_Evtclk ,Start_rsync ( 1 ) ,evt_clk )
PROCESS_148	( evt_clk )
PROCESS_149	( Rst_Evtclk ,evt_clk )
PROCESS_150	( Rst_Evtclk ,evt_clk )
PROCESS_264	( Rst_Pciclk ,PCIe_clk )
PROCESS_265	( PCIe_clk )
PROCESS_266	( evt_clk )
PROCESS_267	( Rst_Evtclk ,Start_rsync ( 1 ) ,evt_clk )
PROCESS_268	( evt_clk )
PROCESS_269	( Rst_Evtclk ,evt_clk )
PROCESS_270	( Rst_Evtclk ,evt_clk )

Components
resync	<Entity resync>

Signals
delay_end_evt	std_logic_vector ( 3 downto 0 )
pre_trig_loop	std_logic
pre_trig_TTC	std_logic
delay_pre_trg_TTC	std_logic
trigger_mux	std_logic
trig_sync	std_logic
trigger_cnt	std_logic_vector ( 8 downto 0 )
evt_cnt	std_logic_vector ( 63 downto 0 )
check_trig	std_logic
evt_working	std_logic
pulse_trigger	std_logic
mem_evt_num	std_logic_vector ( 23 downto 0 )
pcie_ld	std_logic
ld_evt_nm	std_logic
start	std_logic
ena_PCI_trigger	std_logic
go_round	std_logic
reset_func	std_logic
PCI_trig	std_logic
Start_rsync	std_logic_vector ( 1 downto 0 )
Loop_rsync	std_logic

Instantiations
trg_gen	resync <Entity resync>
pre_trig_loop_i1	resync <Entity resync>
ld_evt_sync	resync <Entity resync>
trg_gen	resync <Entity resync>
pre_trig_loop_i1	resync <Entity resync>
ld_evt_sync	resync <Entity resync>

---

Detailed Description

Definition at line 49 of file trigger_gen.vhd.

---

The documentation for this class was generated from the following files:

• src/CMS_DAQ_if/10Gb/slink/trigger_gen.vhd
• src/CMS_DAQ_if/5Gb/slink/trigger_gen.vhd