drp_wr_fsm_beh Architecture Reference

List of all members.

Processes
PROCESS_845	( clk )

Libraries
IEEE

Use Clauses
STD_LOGIC_1164
STD_LOGIC_UNSIGNED
STD_LOGIC_ARITH

Constants
load_addr_agc	std_logic_vector ( 3 downto 0 ) := " 0001 "
rd_drp_agc	std_logic_vector ( 3 downto 0 ) := " 0010 "
wait_drprdy_agc	std_logic_vector ( 3 downto 0 ) := " 0011 "
mod_drp_agc	std_logic_vector ( 3 downto 0 ) := " 0100 "
load_drp_agc	std_logic_vector ( 3 downto 0 ) := " 0101 "
pulse_wr_agc	std_logic_vector ( 3 downto 0 ) := " 0110 "
wait_drp_dy_agc	std_logic_vector ( 3 downto 0 ) := " 0111 "
lock_agc	std_logic_vector ( 3 downto 0 ) := " 1000 "
endstate	std_logic_vector ( 3 downto 0 ) := " 1001 "
resetstate	std_logic_vector ( 3 downto 0 ) := " 1010 "

Signals
store_di0	std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
holds_reg	std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
DI_reg	std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
Address_reg	std_logic_vector ( 8 downto 0 ) := ( others = > ' 0 ' )
state_reg	std_logic_vector ( 3 downto 0 )
done_reg	std_logic := ' 0 '
kill_reg	std_logic := ' 0 '
rd_drp_reg	std_logic := ' 0 '
wr_drp_reg	std_logic := ' 0 '
not_kill	std_logic := ' 1 '

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Detailed Description

Definition at line 89 of file s6link_agc_loop_fsm.vhd.

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The documentation for this class was generated from the following file:

• src/common/IPBUS/S6Link/s6link_agc_loop_fsm.vhd