drp_wr_fsm Entity Reference

Inheritance diagram for drp_wr_fsm:

List of all members.

Entities
drp_wr_fsm_beh	architecture

Ports
lock0	in std_logic
lock1	in std_logic
lock2	in std_logic
lock3	in std_logic
clk	in std_logic
reset	in std_logic
ready	in std_logic
di0	in STD_LOGIC_VECTOR ( 15 downto 0 )
holds	out STD_LOGIC_VECTOR ( 3 downto 0 )
DI	out STD_LOGIC_VECTOR ( 15 downto 0 )
Address	out STD_LOGIC_VECTOR ( 8 downto 0 )
state	out STD_LOGIC_VECTOR ( 3 downto 0 )
done	out std_logic
kill	out std_logic
rd_drp	out std_logic
wr_drp	out std_logic

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Detailed Description

Definition at line 74 of file s6link_agc_loop_fsm.vhd.

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The documentation for this class was generated from the following file:

• src/common/IPBUS/S6Link/s6link_agc_loop_fsm.vhd