Behavioral Architecture Reference

List of all members.

Processes
PROCESS_813	( memclk )
PROCESS_814	( memclk )
PROCESS_815	( sysclk ,AddrQueue_wa ,AddrQueue_rap )
PROCESS_816	( memclk )
PROCESS_817	( memclk )

Components
RAM32x6D	<Entity RAM32x6D>

Signals
AddrQueue_di	std_logic_vector ( 13 downto 0 ) := ( others = > ' 0 ' )
AddrQueue_do	std_logic_vector ( 13 downto 0 ) := ( others = > ' 0 ' )
AddrQueue_dop	std_logic_vector ( 13 downto 12 ) := ( others = > ' 0 ' )
AddrQueue_wa	std_logic_vector ( 4 downto 0 ) := ( others = > ' 0 ' )
AddrQueue_rap	std_logic_vector ( 1 downto 0 ) := ( others = > ' 0 ' )
AddrQueue_ra	std_logic_vector ( 4 downto 0 ) := ( others = > ' 0 ' )
AddrQueue_wa0SyncRegs	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
AddrQueue_wa1SyncRegs	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
EoE_toggleSyncRegs	std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
EoB_toggleSyncRegs	std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
en_din	std_logic := ' 0 '
rqst_i	std_logic := ' 0 '
KiloByte_toggle_i	std_logic := ' 0 '
EoB_toggle_i	std_logic := ' 0 '
EoE_toggle_i	std_logic := ' 0 '
last_word	std_logic := ' 0 '
EventDone	std_logic := ' 0 '
EventDone_dl	std_logic := ' 0 '
FIFO_empty	std_logic := ' 1 '
FIFO_AlmostEmpty	std_logic := ' 1 '
FIFO_sel	std_logic_vector ( 1 downto 0 ) := ( others = > ' 0 ' )
FIFO_we	std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
FIFO_DI	std_logic_vector ( 65 downto 0 ) := ( others = > ' 0 ' )
FIFO_DO	std_logic_vector ( 257 downto 0 ) := ( others = > ' 0 ' )
WRCOUNT	array4x9
RDCOUNT	array4x9
dout_wc	std_logic_vector ( 4 downto 0 ) := ( others = > ' 0 ' )
app_wren	std_logic := ' 0 '
app_addr_i	std_logic_vector ( 13 downto 0 ) := ( others = > ' 0 ' )

Instantiations
i_AddrQueue	RAM32x6D <Entity RAM32x6D>

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Detailed Description

Definition at line 69 of file ddr_wportA.vhd.

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The documentation for this class was generated from the following files:

• src/common/DDR/ddr_wportA.vhd