Behavioral Architecture Reference

List of all members.

Processes
PROCESS_934	( clk2x )
PROCESS_935	( clk )
PROCESS_936	( clk2x ,reset_TXSync )
PROCESS_937	( TXUSRCLK )
PROCESS_938	( RXUSRCLK ,RXRESETDONE )
PROCESS_939	( RXUSRCLK )
PROCESS_940	( RXUSRCLK ,reset )
PROCESS_941	( RXUSRCLK )
PROCESS_942	( RXUSRCLK ,reset )
PROCESS_943	( clk2x )

Components
BLOCK_SYNC_SM	<Entity BLOCK_SYNC_SM>
SCRAMBLER	<Entity SCRAMBLER>
DESCRAMBLER	<Entity DESCRAMBLER>

Constants
EBLOCK	std_logic_vector ( 63 downto 0 ) := x " 1e1e1e1e1e1e1e1e "
LBLOCK	std_logic_vector ( 63 downto 0 ) := x " 0100000001000055 "
R_FAULT	std_logic_vector ( 31 downto 0 ) := x " 0200009c "
LBLOCK_R	std_logic_vector ( 71 downto 0 ) := x " 0100009c10100009c1 "
EBLOCK_R	std_logic_vector ( 71 downto 0 ) := x " fefefefeffefefefef "
RxIdle	array37x32 := ( x " ffff0000 " , x " ffff0000 " , x " ffff0000 " , x " ffff0000 " , x " ffff0000 " , x " ffff0000 " , x " ffff0000 " , x " 00000000 " , x " 00000000 " , x " 00000000 " , x " 00000000 " , x " 00000000 " , x " ffff0000 " , x " ffff0000 " , x " ffff0000 " , x " 00000000 " , x " 00000000 " , x " 00000000 " , x " 00000000 " , x " 00000000 " , x " ffff0000 " , x " ffff0000 " , x " ffff0000 " , x " 00000000 " , x " 00000000 " , x " 00000000 " , x " 00000000 " , x " 00000000 " , x " ffff0000 " , x " ffff0000 " , x " ffff0000 " , x " 00000000 " , x " 00000000 " , x " 00000000 " , x " 00000000 " , x " 00000000 " , x " 00000000 " )

Types
array37x32	array ( 0 to 36 ) of bit_vector ( 31 downto 0 )
state	( TX_INIT , TX_C , TX_D , TX_T , TX_E )
Rstate	( RX_INIT , RX_C , RX_D , RX_T , RX_E )

Signals
T_state	state := TX_INIT
EmacPhyTxC_q	std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
EmacPhyTxD_q	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
TxC	std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
TxD	std_logic_vector ( 63 downto 0 ) := ( others = > ' 0 ' )
TxD_q	std_logic_vector ( 63 downto 0 ) := ( others = > ' 0 ' )
c_coded	std_logic_vector ( 55 downto 0 ) := ( others = > ' 0 ' )
tx_coded	std_logic_vector ( 65 downto 0 ) := ( others = > ' 0 ' )
T_TYPE_C	std_logic := ' 0 '
T_TYPE_D	std_logic := ' 0 '
T_TYPE_S	std_logic := ' 0 '
T_TYPE_T	std_logic := ' 0 '
T_IS_D	std_logic := ' 0 '
T_IS_O	std_logic_vector ( 1 downto 0 ) := ( others = > ' 0 ' )
T_IS_S	std_logic_vector ( 1 downto 0 ) := ( others = > ' 0 ' )
T_IS_C	std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
T_IS_E	std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
T_IS_T	std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
GTX_TX_PAUSE_q	std_logic := ' 0 '
TX_FIFO_DI	std_logic_vector ( 33 downto 0 ) := ( others = > ' 0 ' )
TX_FIFO_DO	std_logic_vector ( 33 downto 0 ) := ( others = > ' 0 ' )
TX_FIFO_wa	std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
TX_FIFO_ra	std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
GTX_RXHEADER_IN	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
BLOCK_LOCK	std_logic := ' 0 '
BLOCK_SYNC_SM_RESET	std_logic := ' 0 '
BLOCK_NOT_LOCK	std_logic := ' 0 '
GTX_RXHEADERVLD_dl	std_logic_vector ( 1 downto 0 ) := ( others = > ' 0 ' )
GTX_RXHEADER_dl0	std_logic_vector ( 1 downto 0 ) := ( others = > ' 0 ' )
TX_UNSCRAMBLED_DATA	std_logic_vector ( 65 downto 0 ) := ( others = > ' 0 ' )
TX_UNSCRAMBLED_DATA_MUX	std_logic_vector ( 33 downto 0 ) := ( others = > ' 0 ' )
RX_UNSCRAMBLED_DATA	std_logic_vector ( 63 downto 0 ) := ( others = > ' 0 ' )
RX_UNSCRAMBLED_DATA_OUT	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
RXHEADER	std_logic_vector ( 1 downto 0 ) := ( others = > ' 0 ' )
R_state	Rstate := RX_INIT
RxC	std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
RxD	std_logic_vector ( 63 downto 0 ) := ( others = > ' 0 ' )
c_raw	std_logic_vector ( 63 downto 0 ) := ( others = > ' 0 ' )
rx_raw	std_logic_vector ( 71 downto 0 ) := ( others = > ' 0 ' )
rx_raw_ps2	std_logic_vector ( 71 downto 0 ) := ( others = > ' 0 ' )
rx_raw_ps3	std_logic_vector ( 71 downto 0 ) := ( others = > ' 0 ' )
rx_raw_mux	std_logic_vector ( 35 downto 0 ) := ( others = > ' 0 ' )
R_TYPE_C	std_logic := ' 0 '
R_TYPE_D	std_logic := ' 0 '
R_TYPE_S	std_logic := ' 0 '
R_TYPE_T	std_logic := ' 0 '
NEXT_TYPE_C	std_logic := ' 0 '
NEXT_TYPE_D	std_logic := ' 0 '
NEXT_TYPE_S	std_logic := ' 0 '
NEXT_TYPE_T	std_logic := ' 0 '
R_IS_D	std_logic := ' 0 '
R_IS_T	std_logic := ' 0 '
Legal_O	std_logic_vector ( 1 downto 0 ) := ( others = > ' 0 ' )
R_IS_O	std_logic_vector ( 1 downto 0 ) := ( others = > ' 0 ' )
R_IS_S	std_logic_vector ( 1 downto 0 ) := ( others = > ' 0 ' )
R_IS_C	std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
R_IS_E	std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
RX_FIFO_DI	std_logic_vector ( 36 downto 0 ) := ( others = > ' 0 ' )
RX_FIFO_DO	std_logic_vector ( 36 downto 0 ) := ( others = > ' 0 ' )
RX_FIFO_WA	std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
RX_FIFO_RA	std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
RX_FIFO_RA_G	std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
RX_FIFO_RA_P	std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
RX_FIFO_WA_RA_D	std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
RX_FIFO_RA_G0SyncRegs	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
RX_FIFO_RA_G1SyncRegs	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
RX_FIFO_RA_G2SyncRegs	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
RX_FIFO_RA_G3SyncRegs	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
RX_FIFO_WE	std_logic := ' 0 '
GTX_RXDVLD_q	std_logic := ' 0 '
skip_RX_FIFO_WE	std_logic := ' 0 '
ec_RX_FIFO_RAn	std_logic := ' 0 '
insert_IDLE	std_logic := ' 0 '
delete_IDLE	std_logic := ' 0 '
insert_IDLE_l	std_logic := ' 0 '
delete_IDLE_l	std_logic := ' 0 '
R_IS_RF	std_logic_vector ( 6 downto 0 ) := ( others = > ' 0 ' )
R_IS_LF	std_logic_vector ( 6 downto 0 ) := ( others = > ' 0 ' )
R_IS_IDLE	std_logic_vector ( 5 downto 0 ) := ( others = > ' 0 ' )
en_DI	std_logic := ' 0 '
en_II	std_logic := ' 0 '
T4567	std_logic := ' 0 '
inh	std_logic := ' 0 '
inh_cntr	std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
reset_RXSyncRegs	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
RXRESETDONE_SyncRegs	std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
RXGOOD_cntr	std_logic_vector ( 4 downto 0 ) := ( others = > ' 0 ' )

Instantiations
i_BLOCK_SYNC_SM	BLOCK_SYNC_SM <Entity BLOCK_SYNC_SM>
i_SCRAMBLER	SCRAMBLER <Entity SCRAMBLER>
i_DESCRAMBLER	DESCRAMBLER <Entity DESCRAMBLER>

---

Detailed Description

Definition at line 63 of file XGbEPCS32.vhd.

---

The documentation for this class was generated from the following files:

• src/common_10G/XGbEPCS32.vhd