1 ----------------------------------------------------------------------------------
5 -- Create Date: 09:
16:
59 11/24/2012
7 -- Module Name: EMAC_GXPCS - Behavioral
16 -- Revision 0.
01 -
File Created
17 -- Additional Comments:
19 ----------------------------------------------------------------------------------
21 use IEEE.STD_LOGIC_1164.
ALL;
22 use IEEE.STD_LOGIC_ARITH.
ALL;
23 use IEEE.STD_LOGIC_UNSIGNED.
ALL;
24 use IEEE.std_logic_misc.
all;
26 -- Uncomment the following library declaration if using
27 -- arithmetic functions with or values
28 --use IEEE.NUMERIC_STD.ALL;
30 -- Uncomment the following library declaration if instantiating
31 -- any Xilinx primitives in this code.
33 use UNISIM.VComponents.
all;
38 clk2x : IN ;
-- 2xSFP_REFCLK 312.5MHz norminal
41 TX_high : IN ;
-- in clk2x domain, TX_high = clk
46 GTX_TXD : out (31 downto 0) := (others => '0');
47 GTX_TXHEADER : out (1 downto 0) := (others => '0');
48 GTX_TX_PAUSE : IN ;
-- sequence counter = "011111"
49 GTX_RXD : in (31 downto 0);
51 GTX_RXHEADER : in (1 downto 0);
52 GTX_RXHEADERVLD : in ;
54 GTX_RXGEARBOXSLIP_OUT : out := '0';
55 EmacPhyTxC : in (3 downto 0);
56 EmacPhyTxD : in (31 downto 0);
57 PhyEmacRxC : out (3 downto 0) := (others => '0');
58 PhyEmacRxD : out (31 downto 0) := (others => '0');
59 status : out (31 downto 0)
66 RXHEADER_IN :
IN (
2 downto 0);
67 RXHEADERVALID_IN :
IN ;
71 RXGEARBOXSLIP_OUT :
OUT
80 UNSCRAMBLED_DATA_IN :
IN ((TX_DATA_WIDTH
-1)
downto 0);
84 SCRAMBLED_DATA_OUT :
OUT ((TX_DATA_WIDTH
-1)
downto 0)
93 SCRAMBLED_DATA_IN :
IN ((RX_DATA_WIDTH
-1)
downto 0);
97 UNSCRAMBLED_DATA_OUT :
OUT ((RX_DATA_WIDTH
-1)
downto 0)
100 constant EBLOCK : (63 downto 0) := x"1e1e1e1e1e1e1e1e";
101 constant LBLOCK : (63 downto 0) := x"0100000001000055";
102 constant R_FAULT : (31 downto 0) := x"0200009c";
103 constant LBLOCK_R : (71 downto 0) := x"0100009c10100009c1";
104 constant EBLOCK_R : (71 downto 0) := x"fefefefeffefefefef";
105 type array37x32 is array(0 to 36) of (31 downto 0);
106 constant RxIdle : array37x32 := (x"ffff0000",x"ffff0000",x"ffff0000",x"ffff0000",
107 x"ffff0000",x"ffff0000",x"ffff0000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",
108 x"ffff0000",x"ffff0000",x"ffff0000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",
109 x"ffff0000",x"ffff0000",x"ffff0000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",
110 x"ffff0000",x"ffff0000",x"ffff0000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",
112 type state is (TX_INIT, TX_C, TX_D, TX_T, TX_E);
113 signal T_state : state := TX_INIT;
114 signal EmacPhyTxC_q : (3 downto 0) := (others => '0');
115 signal EmacPhyTxD_q : (31 downto 0) := (others => '0');
116 signal TxC : (7 downto 0) := (others => '0');
117 signal TxD : (63 downto 0) := (others => '0');
118 signal TxD_q : (63 downto 0) := (others => '0');
119 signal c_coded : (55 downto 0) := (others => '0');
120 signal tx_coded : (65 downto 0) := (others => '0');
121 signal T_TYPE_C : := '0';
122 signal T_TYPE_D : := '0';
123 signal T_TYPE_S : := '0';
124 signal T_TYPE_T : := '0';
125 signal T_IS_D : := '0';
126 signal T_IS_O : (1 downto 0) := (others => '0');
127 signal T_IS_S : (1 downto 0) := (others => '0');
128 signal T_IS_C : (7 downto 0) := (others => '0');
129 signal T_IS_E : (7 downto 0) := (others => '0');
130 signal T_IS_T : (7 downto 0) := (others => '0');
131 signal GTX_TX_PAUSE_q : := '0';
132 signal TX_FIFO_DI : (33 downto 0) := (others => '0');
133 signal TX_FIFO_DO : (33 downto 0) := (others => '0');
134 signal TX_FIFO_wa : (3 downto 0) := (others => '0');
135 signal TX_FIFO_ra : (3 downto 0) := (others => '0');
136 signal GTX_RXHEADER_IN : (2 downto 0) := (others => '0');
137 signal BLOCK_LOCK : := '0';
138 signal BLOCK_SYNC_SM_RESET : := '0';
139 signal BLOCK_NOT_LOCK : := '0';
140 signal GTX_RXHEADERVLD_dl : (1 downto 0) := (others => '0');
141 signal GTX_RXHEADER_dl0 : (1 downto 0) := (others => '0');
142 signal TX_UNSCRAMBLED_DATA : (65 downto 0) := (others => '0');
143 signal TX_UNSCRAMBLED_DATA_MUX : (33 downto 0) := (others => '0');
144 signal RX_UNSCRAMBLED_DATA : (63 downto 0) := (others => '0');
145 signal RX_UNSCRAMBLED_DATA_OUT : (31 downto 0) := (others => '0');
146 signal RXHEADER : (1 downto 0) := (others => '0');
147 type Rstate is (RX_INIT, RX_C, RX_D, RX_T, RX_E);
148 signal R_state : Rstate := RX_INIT;
149 signal RxC : (7 downto 0) := (others => '0');
150 signal RxD : (63 downto 0) := (others => '0');
151 signal c_raw : (63 downto 0) := (others => '0');
152 signal rx_raw : (71 downto 0) := (others => '0');
153 signal rx_raw_ps2 : (71 downto 0) := (others => '0');
154 signal rx_raw_ps3 : (71 downto 0) := (others => '0');
155 signal rx_raw_mux : (35 downto 0) := (others => '0');
156 signal R_TYPE_C : := '0';
157 signal R_TYPE_D : := '0';
158 signal R_TYPE_S : := '0';
159 signal R_TYPE_T : := '0';
160 signal NEXT_TYPE_C : := '0';
161 signal NEXT_TYPE_D : := '0';
162 signal NEXT_TYPE_S : := '0';
163 signal NEXT_TYPE_T : := '0';
164 signal R_IS_D : := '0';
165 signal R_IS_T : := '0';
166 signal Legal_O : (1 downto 0) := (others => '0');
167 signal R_IS_O : (1 downto 0) := (others => '0');
168 signal R_IS_S : (1 downto 0) := (others => '0');
169 signal R_IS_C : (7 downto 0) := (others => '0');
170 signal R_IS_E : (7 downto 0) := (others => '0');
171 signal RX_FIFO_DI : (36 downto 0) := (others => '0');
172 signal RX_FIFO_DO : (36 downto 0) := (others => '0');
173 signal RX_FIFO_WA : (3 downto 0) := (others => '0');
174 signal RX_FIFO_RA : (3 downto 0) := (others => '0');
175 signal RX_FIFO_RA_G : (3 downto 0) := (others => '0');
176 signal RX_FIFO_RA_P : (3 downto 0) := (others => '0');
177 signal RX_FIFO_WA_RA_D : (3 downto 0) := (others => '0');
178 signal RX_FIFO_RA_G0SyncRegs : (2 downto 0) := (others => '0');
179 signal RX_FIFO_RA_G1SyncRegs : (2 downto 0) := (others => '0');
180 signal RX_FIFO_RA_G2SyncRegs : (2 downto 0) := (others => '0');
181 signal RX_FIFO_RA_G3SyncRegs : (2 downto 0) := (others => '0');
182 signal RX_FIFO_WE : := '0';
183 signal GTX_RXDVLD_q : := '0';
184 signal skip_RX_FIFO_WE : := '0';
185 signal ec_RX_FIFO_RAn : := '0';
186 signal insert_IDLE : := '0';
187 signal delete_IDLE : := '0';
188 signal insert_IDLE_l : := '0';
189 signal delete_IDLE_l : := '0';
190 signal R_IS_RF : (6 downto 0) := (others => '0');
191 signal R_IS_LF : (6 downto 0) := (others => '0');
192 signal R_IS_IDLE : (5 downto 0) := (others => '0');
193 signal en_DI : := '0';
194 signal en_II : := '0';
195 signal T4567 : := '0';
197 signal inh_cntr : (3 downto 0) := (others => '0');
198 signal reset_RXSyncRegs : (2 downto 0) := (others => '0');
199 signal RXRESETDONE_SyncRegs : (3 downto 0) := (others => '0');
200 signal RXGOOD_cntr : (4 downto 0) := (others => '0');
204 if(clk2x'event and clk2x = '1')then
205 if(TX_high = '0')then
206 EmacPhyTxC_q <= EmacPhyTxC;
207 EmacPhyTxD_q <= EmacPhyTxD;
209 TxC <= EmacPhyTxC & EmacPhyTxC_q;
210 TxD <= EmacPhyTxD & EmacPhyTxD_q;
212 if(TX_high = '1')then
213 TX_UNSCRAMBLED_DATA_MUX <= '1' & TX_UNSCRAMBLED_DATA(64) & TX_UNSCRAMBLED_DATA(31 downto 0);
215 TX_UNSCRAMBLED_DATA_MUX <= '0' & TX_UNSCRAMBLED_DATA(64 downto 32);
217 TX_FIFO_DI(33 downto 32) <= TX_UNSCRAMBLED_DATA_MUX(33 downto 32);
222 if(clk'event and clk = '1')then
223 if(TxC(3 downto 0) = x"1" and TxD(31 downto 0) = R_FAULT)then
228 if(TxC(7 downto 4) = x"1" and TxD(63 downto 32) = R_FAULT)then
233 if(TxC = x"01" and TxD(7 downto 0) = x"fb")then
238 if(TxC(7 downto 4) = x"1" and TxD(39 downto 32) = x"fb")then
244 if(TxC(i) = '1' and TxD(i*8+7 downto i*8) = x"07")then
249 if(TxC(i) = '1' and TxD(i*8+7 downto i*8) = x"fe")then
251 c_coded(I*7+6 downto i*7) <= "0011110";
254 c_coded(I*7+6 downto i*7) <= "0000000";
257 if(TxC(0) = '1' and TxD(7 downto 0) = x"fd")then
262 if(TxC(1 downto 0) = "10" and TxD(15 downto 8) = x"fd")then
267 if(TxC(2 downto 0) = "100" and TxD(23 downto 16) = x"fd")then
272 if(TxC(3 downto 0) = "1000" and TxD(31 downto 24) = x"fd")then
277 if(TxC(4 downto 0) = "10000" and TxD(39 downto 32) = x"fd")then
282 if(TxC(5 downto 0) = "100000" and TxD(47 downto 40) = x"fd")then
287 if(TxC(6 downto 0) = "1000000" and TxD(55 downto 48) = x"fd")then
292 if(TxC(7 downto 0) = "10000000" and TxD(63 downto 56) = x"fd")then
297 T_IS_D <= not or_reduce(TxC);
298 if(and_reduce(T_IS_C) = '1' or (T_IS_O(0) = '1' and T_IS_C(7 downto 4) = not T_IS_E(7 downto 4)) or (T_IS_O(1) = '1' and T_IS_C(3 downto 0) = not T_IS_E(3 downto 0)) or T_IS_O = "11")then
303 if(T_IS_S(0) = '1' or (T_IS_S(1) = '1' and (T_IS_C(3 downto 0) = not T_IS_E(3 downto 0) or T_IS_O(0) = '1')))then
310 if(T_IS_T(0) = '1' and T_IS_C(7 downto 1) = not T_IS_E(7 downto 1))then
313 if(T_IS_T(1) = '1' and T_IS_C(7 downto 2) = not T_IS_E(7 downto 2))then
316 if(T_IS_T(2) = '1' and T_IS_C(7 downto 3) = not T_IS_E(7 downto 3))then
319 if(T_IS_T(3) = '1' and T_IS_C(7 downto 4) = not T_IS_E(7 downto 4))then
322 if(T_IS_T(4) = '1' and T_IS_C(7 downto 5) = not T_IS_E(7 downto 5))then
325 if(T_IS_T(5) = '1' and T_IS_C(7 downto 6) = not T_IS_E(7 downto 6))then
328 if(T_IS_T(6) = '1' and T_IS_C(7) = not T_IS_E(7))then
331 if(T_IS_T(7) = '1')then
335 if(T_IS_C = x"ff")then
336 tx_coded(63 downto 0) <= x"000000000000001e";
338 if(T_IS_O(1) = '1' and T_IS_C(3 downto 0) = not T_IS_E(3 downto 0))then
339 tx_coded(63 downto 0) <= TxD_q(63 downto 40) & x"0" & c_coded(27 downto 0) & x"2d";
341 if(T_IS_S(1) = '1' and T_IS_C(3 downto 0) = not T_IS_E(3 downto 0))then
342 tx_coded(63 downto 0) <= TxD_q(63 downto 40) & x"0" & c_coded(27 downto 0) & x"33";
344 if(T_IS_O(0) = '1' and T_IS_C(7 downto 4) = not T_IS_E(7 downto 4))then
345 tx_coded(63 downto 0) <= c_coded(55 downto 28) & x"0" & TxD_q(31 downto 8) & x"4b";
347 if(T_IS_O = "11")then
348 tx_coded(63 downto 0) <= TxD_q(63 downto 40) & x"00" & TxD_q(31 downto 8) & x"55";
350 if(T_IS_S(1) = '1' and T_IS_O(0) = '1')then
351 tx_coded(63 downto 0) <= TxD_q(63 downto 40) & TxD_q(31 downto 0) & x"66";
353 if(T_IS_S(0) = '1')then
354 tx_coded(63 downto 0) <= TxD_q(63 downto 8) & x"78";
356 if(T_IS_T(0) = '1')then
357 tx_coded(63 downto 0) <= c_coded(55 downto 7) & "0000000" & x"87";
359 if(T_IS_T(1) = '1')then
360 tx_coded(63 downto 0) <= c_coded(55 downto 14) & "000000" & TxD_q(7 downto 0) & x"99";
362 if(T_IS_T(2) = '1')then
363 tx_coded(63 downto 0) <= c_coded(55 downto 21) & "00000" & TxD_q(15 downto 0) & x"aa";
365 if(T_IS_T(3) = '1')then
366 tx_coded(63 downto 0) <= c_coded(55 downto 28) & "0000" & TxD_q(23 downto 0) & x"b4";
368 if(T_IS_T(4) = '1')then
369 tx_coded(63 downto 0) <= c_coded(55 downto 35) & "000" & TxD_q(31 downto 0) & x"cc";
371 if(T_IS_T(5) = '1')then
372 tx_coded(63 downto 0) <= c_coded(55 downto 42) & "00" & TxD_q(39 downto 0) & x"d2";
374 if(T_IS_T(6) = '1')then
375 tx_coded(63 downto 0) <= c_coded(55 downto 49) & '0' & TxD_q(47 downto 0) & x"e1";
377 if(T_IS_T(7) = '1')then
378 tx_coded(63 downto 0) <= TxD_q(55 downto 0) & x"ff";
381 tx_coded(63 downto 0) <= TxD_q;
384 tx_coded(65 downto 64) <= "01";
386 tx_coded(65 downto 64) <= "10";
390 TX_UNSCRAMBLED_DATA <= "10" & LBLOCK;
394 TX_UNSCRAMBLED_DATA <= tx_coded;
395 if(T_TYPE_C = '1')then
397 elsif(T_TYPE_S = '1')then
401 TX_UNSCRAMBLED_DATA <= "10" & EBLOCK;
404 TX_UNSCRAMBLED_DATA <= tx_coded;
405 if(T_TYPE_S = '1')then
407 elsif(T_TYPE_C = '0')then
409 TX_UNSCRAMBLED_DATA <= "10" & EBLOCK;
412 TX_UNSCRAMBLED_DATA <= tx_coded;
413 if(T_TYPE_T = '1')then
415 elsif(T_TYPE_D = '0')then
417 TX_UNSCRAMBLED_DATA <= "10" & EBLOCK;
420 TX_UNSCRAMBLED_DATA <= tx_coded;
421 if(T_TYPE_C = '1')then
423 elsif(T_TYPE_S = '1')then
427 TX_UNSCRAMBLED_DATA <= "10" & EBLOCK;
430 TX_UNSCRAMBLED_DATA <= tx_coded;
431 if(T_TYPE_C = '1')then
433 elsif(T_TYPE_D = '1')then
435 elsif(T_TYPE_T = '1')then
438 TX_UNSCRAMBLED_DATA <= "10" & EBLOCK;
444 process(clk2x,reset_TXSync)
446 if(reset_TXSync = '1')then
448 elsif(clk2x'event and clk2x = '1')then
449 TX_FIFO_WA <= TX_FIFO_WA + 1;
452 g_TX_FIFO: for i in 0 to 33 generate
455 DPO => TX_FIFO_DO
(i
),
-- Read-only 1-bit data output
456 SPO =>
open,
-- R/W 1-bit data output
457 A0 => TX_FIFO_WA
(0),
-- R/W address[0] input
458 A1 => TX_FIFO_WA
(1),
-- R/W address[1] input
459 A2 => TX_FIFO_WA
(2),
-- R/W address[2] input
460 A3 => TX_FIFO_WA
(3),
-- R/W address[3] input
461 A4 => '0',
-- R/W address[4] input
462 D => TX_FIFO_DI
(i
),
-- Write 1-bit data input
463 DPRA0 => TX_FIFO_RA
(0),
-- Read-only address[0] input
464 DPRA1 => TX_FIFO_RA
(1),
-- Read-only address[1] input
465 DPRA2 => TX_FIFO_RA
(2),
-- Read-only address[2] input
466 DPRA3 => TX_FIFO_RA
(3),
-- Read-only address[3] input
467 DPRA4 => '0',
-- Read-only address[4] input
468 WCLK => clk2x,
-- Write clock input
469 WE => '1'
-- Write enable input
474 if(TXUSRCLK'event and TXUSRCLK = '1')then
475 if(reset_TXSync = '1')then
476 TX_FIFO_RA <= (others => '0');
477 elsif(GTX_TX_PAUSE = '0' or (TX_FIFO_DO(33) = '1' and GTX_TX_PAUSE_q = '0'))then
478 TX_FIFO_RA <= TX_FIFO_RA + 1;
481 GTX_TXHEADER <= "00";
483 GTX_TXHEADER <= not TX_FIFO_DO(32) & TX_FIFO_DO(32);
485 GTX_TX_PAUSE_q <= GTX_TX_PAUSE;
487 GTX_TXD <= (others => '0');
489 GTX_TXD <= TX_FIFO_DO(31 downto 0);
493 process(RXUSRCLK,RXRESETDONE)
495 if(RXRESETDONE = '0')then
496 RXRESETDONE_SyncRegs <= (others => '0');
497 elsif(RXUSRCLK'event and RXUSRCLK = '1')then
498 RXRESETDONE_SyncRegs <= RXRESETDONE_SyncRegs(2 downto 0) & '1';
502 BLOCKSYNC_OUT => BLOCK_LOCK,
503 RXGEARBOXSLIP_OUT => GTX_RXGEARBOXSLIP_OUT,
504 RXHEADER_IN => GTX_RXHEADER_IN,
505 RXHEADERVALID_IN => GTX_RXHEADERVLD,
506 USER_CLK => RXUSRCLK,
507 SYSTEM_RESET => BLOCK_SYNC_SM_RESET
509 BLOCK_SYNC_SM_RESET <= not RXRESETDONE_SyncRegs(3);
510 GTX_RXHEADER_IN <= '0' & GTX_RXHEADER;
511 BLOCK_NOT_LOCK <= not BLOCK_LOCK;
513 UNSCRAMBLED_DATA_IN => TX_UNSCRAMBLED_DATA_MUX
(31 downto 0),
514 SCRAMBLED_DATA_OUT => TX_FIFO_DI
(31 downto 0),
515 DATA_VALID_IN => '1',
517 SYSTEM_RESET => RESET_TXSync
521 SCRAMBLED_DATA_IN => GTX_RXD,
522 UNSCRAMBLED_DATA_OUT => RX_UNSCRAMBLED_DATA_OUT ,
523 DATA_VALID_IN => GTX_RXDVLD,
524 USER_CLK => RXUSRCLK,
525 SYSTEM_RESET => BLOCK_NOT_LOCK
529 if(RXUSRCLK'event and RXUSRCLK = '1')then
530 GTX_RXHEADERVLD_dl <= GTX_RXHEADERVLD_dl(0) & GTX_RXHEADERVLD;
531 if(GTX_RXHEADERVLD = '1')then
532 GTX_RXHEADER_dl0 <= GTX_RXHEADER;
534 if(GTX_RXHEADERVLD_dl(0) = '1')then
535 RX_UNSCRAMBLED_DATA(31 downto 0) <= RX_UNSCRAMBLED_DATA_OUT;
537 if(GTX_RXHEADERVLD_dl(1) = '1')then
538 RX_UNSCRAMBLED_DATA(63 downto 32) <= RX_UNSCRAMBLED_DATA_OUT;
540 if(GTX_RXHEADERVLD_dl(0) = '1')then
541 if(reset_RXSyncRegs(2) = '1' or R_state = RX_E)then
543 elsif(RXGOOD_cntr(4) = '1')then
546 if(reset_RXSyncRegs(2) = '1' or R_state = RX_E)then
547 RXGOOD_cntr <= (others => '0');
548 elsif(RXGOOD_cntr(4) = '0')then
549 RXGOOD_cntr <= RXGOOD_cntr + 1;
552 RXHEADER <= GTX_RXHEADER_dl0;
553 case RX_UNSCRAMBLED_DATA(3 downto 0) is
554 when x"1" => RxC <= x"c0";
555 when x"2" => RxC <= x"e0";
556 when x"3" | x"d" => RxC <= x"1f";
557 when x"4" => RxC <= x"f8";
558 when x"5" | x"6" => RxC <= x"11";
559 when x"7" | x"e" => RxC <= x"ff";
560 when x"8" => RxC <= x"01";
561 when x"9" => RxC <= x"fe";
562 when x"a" => RxC <= x"fc";
563 when x"b" => RxC <= x"f1";
564 when x"c" => RxC <= x"f0";
565 when x"f" => RxC <= x"80";
566 when others => RxC <= x"00";
568 RxD <= RX_UNSCRAMBLED_DATA;
570 if(RX_UNSCRAMBLED_DATA(i*7+14 downto i*7+8) = "0000000")then
575 if(RX_UNSCRAMBLED_DATA(i*7+14 downto i*7+8) = "0011110")then
577 c_raw(I*8+7 downto i*8) <= x"fe";
580 c_raw(I*8+7 downto i*8) <= x"07";
583 if(RX_UNSCRAMBLED_DATA(35 downto 8) = x"0010000" or RX_UNSCRAMBLED_DATA(35 downto 8) = x"0020000")then
588 if(RX_UNSCRAMBLED_DATA(63 downto 36) = x"0100000" or RX_UNSCRAMBLED_DATA(63 downto 36) = x"0200000")then
593 if(RX_UNSCRAMBLED_DATA(7 downto 4) = x"4" or RX_UNSCRAMBLED_DATA(7 downto 4) = x"5" or RX_UNSCRAMBLED_DATA(7 downto 4) = x"6")then
598 if(RX_UNSCRAMBLED_DATA(7 downto 4) = x"2" or RX_UNSCRAMBLED_DATA(7 downto 4) = x"5")then
603 if(RX_UNSCRAMBLED_DATA(7 downto 4) = x"7")then
608 if(RX_UNSCRAMBLED_DATA(7 downto 4) = x"3" or RX_UNSCRAMBLED_DATA(7 downto 4) = x"6")then
613 if(RXHEADER = "01")then
618 if(RX_UNSCRAMBLED_DATA(7) = '1')then
619 case RX_UNSCRAMBLED_DATA(6 downto 4) is
620 when "000" => R_IS_T <= not or_reduce(RX_UNSCRAMBLED_DATA(14 downto 8));
621 when "001" => R_IS_T <= not or_reduce(RX_UNSCRAMBLED_DATA(21 downto 16));
622 when "010" => R_IS_T <= not or_reduce(RX_UNSCRAMBLED_DATA(28 downto 24));
623 when "011" => R_IS_T <= not or_reduce(RX_UNSCRAMBLED_DATA(35 downto 32));
624 when "100" => R_IS_T <= not or_reduce(RX_UNSCRAMBLED_DATA(42 downto 40));
625 when "101" => R_IS_T <= not or_reduce(RX_UNSCRAMBLED_DATA(49 downto 48));
626 when "110" => R_IS_T <= not RX_UNSCRAMBLED_DATA(56);
627 when others => R_IS_T <= '1';
638 rx_raw_ps2 <= x"00" & RxD;
639 R_IS_IDLE(1 downto 0) <= "00";
640 R_IS_RF(1 downto 0) <= "00";
641 R_IS_LF(1 downto 0) <= "00";
643 R_IS_IDLE(0) <= and_reduce(RxC(3 downto 0)) and and_reduce(R_IS_C(3 downto 0)) and (not NEXT_TYPE_T or not T4567) and not R_IS_T;
644 R_IS_IDLE(1) <= and_reduce(RxC(7 downto 4)) and and_reduce(R_IS_C(7 downto 4)) and not R_IS_T;
645 R_IS_RF(0) <= R_IS_O(0) and Legal_O(0) and not RxD(24);
646 R_IS_RF(1) <= R_IS_O(1) and Legal_O(1) and not RxD(56);
647 R_IS_LF(0) <= R_IS_O(0) and Legal_O(0) and RxD(24);
648 R_IS_LF(1) <= R_IS_O(1) and Legal_O(1) and RxD(56);
650 rx_raw_ps2(71 downto 64) <= RxC;
651 if(RxC = x"ff" and R_IS_C = x"ff" and R_IS_T = '0')then
653 rx_raw_ps2(63 downto 0) <= c_raw;
654 elsif(Legal_O(0) = '1' and R_IS_O(0) = '1' and R_IS_C(7 downto 4) = not R_IS_E(7 downto 4) and RxC(7 downto 4) = x"f")then
656 rx_raw_ps2(63 downto 0) <= c_raw(63 downto 32) & RxD(31 downto 8) & x"9c";
657 elsif(Legal_O(1) = '1' and R_IS_O(1) = '1' and R_IS_C(3 downto 0) = not R_IS_E(3 downto 0) and RxC(3 downto 0) = x"f")then
659 rx_raw_ps2(63 downto 0) <= RxD(63 downto 40) & x"9c" & c_raw(31 downto 0);
660 elsif(Legal_O = "11" and R_IS_O = "11")then
662 rx_raw_ps2(63 downto 0) <= RxD(63 downto 40) & x"9c" & RxD(31 downto 8) & x"9c";
666 if(R_IS_S(0) = '1')then
668 rx_raw_ps2(63 downto 0) <= RxD(63 downto 8) & x"fb";
669 elsif(R_IS_S(1) = '1' and R_IS_C(3 downto 0) = not R_IS_E(3 downto 0) and RxC(3 downto 0) = x"f")then
671 rx_raw_ps2(63 downto 0) <= RxD(63 downto 40) & x"fb" & c_raw(31 downto 0);
672 elsif(R_IS_S(1) = '1' and Legal_O(1) = '1' and R_IS_O(1) = '1')then
674 rx_raw_ps2(63 downto 0) <= RxD(63 downto 40) & x"fb" & RxD(31 downto 8) & x"9c";
679 case RxD(6 downto 4) is
681 if(R_IS_C(7 downto 1) = not R_IS_E(7 downto 1))then
686 rx_raw_ps2(63 downto 0) <= c_raw(63 downto 8) & x"fd";
688 if(R_IS_C(7 downto 2) = not R_IS_E(7 downto 2))then
693 rx_raw_ps2(63 downto 0) <= c_raw(63 downto 16) & x"fd" & RxD(15 downto 8);
695 if(R_IS_C(7 downto 3) = not R_IS_E(7 downto 3))then
700 rx_raw_ps2(63 downto 0) <= c_raw(63 downto 24) & x"fd" & RxD(23 downto 8);
702 if(R_IS_C(7 downto 4) = not R_IS_E(7 downto 4))then
707 rx_raw_ps2(63 downto 0) <= c_raw(63 downto 32) & x"fd" & RxD(31 downto 8);
709 if(R_IS_C(7 downto 5) = not R_IS_E(7 downto 5))then
714 rx_raw_ps2(63 downto 0) <= c_raw(63 downto 40) & x"fd" & RxD(39 downto 8);
716 if(R_IS_C(7 downto 6) = not R_IS_E(7 downto 6))then
721 rx_raw_ps2(63 downto 0) <= c_raw(63 downto 48) & x"fd" & RxD(47 downto 8);
723 if(R_IS_C(7) = not R_IS_E(7))then
728 rx_raw_ps2(63 downto 0) <= c_raw(63 downto 56) & x"fd" & RxD(55 downto 8);
731 rx_raw_ps2(63 downto 0) <= x"fd" & RxD(63 downto 8);
739 R_TYPE_C <= NEXT_TYPE_C;
740 R_TYPE_D <= NEXT_TYPE_D;
741 R_TYPE_S <= NEXT_TYPE_S;
742 R_TYPE_T <= NEXT_TYPE_T;
743 rx_raw_ps3 <= rx_raw_ps2(63 downto 32) & rx_raw_ps2(71 downto 68) & rx_raw_ps2(31 downto 0) & rx_raw_ps2(67 downto 64);
744 R_IS_IDLE(3 downto 2) <= R_IS_IDLE(1 downto 0);
745 R_IS_RF(3 downto 2) <= R_IS_RF(1 downto 0);
746 R_IS_LF(3 downto 2) <= R_IS_LF(1 downto 0);
749 if(reset = '1' or BLOCK_LOCK = '0')then
752 R_IS_LF(5 downto 4) <= "11";
753 R_IS_RF(5 downto 4) <= "00";
754 R_IS_IDLE(5 downto 4) <= "00";
755 elsif(GTX_RXHEADERVLD_dl(0) = '1')then
758 rx_raw <= rx_raw_ps3;
759 R_IS_LF(5 downto 4) <= "11";
760 R_IS_RF(5 downto 4) <= "00";
761 R_IS_IDLE(5 downto 4) <= "00";
762 if(R_TYPE_C = '1')then
764 elsif(R_TYPE_S = '1')then
771 R_IS_LF(5 downto 4) <= R_IS_LF(3 downto 2);
772 R_IS_RF(5 downto 4) <= R_IS_RF(3 downto 2);
773 R_IS_IDLE(5 downto 4) <= R_IS_IDLE(3 downto 2);
774 rx_raw <= rx_raw_ps3;
775 if(R_TYPE_S = '1')then
777 elsif(R_TYPE_C = '0')then
782 R_IS_LF(5 downto 4) <= R_IS_LF(3 downto 2);
783 R_IS_RF(5 downto 4) <= R_IS_RF(3 downto 2);
784 R_IS_IDLE(5 downto 4) <= R_IS_IDLE(3 downto 2);
785 rx_raw <= rx_raw_ps3;
786 if(R_TYPE_T = '1' and (NEXT_TYPE_C = '1' or NEXT_TYPE_S = '1'))then
788 elsif(R_TYPE_D = '0')then
793 R_IS_LF(5 downto 4) <= R_IS_LF(3 downto 2);
794 R_IS_RF(5 downto 4) <= R_IS_RF(3 downto 2);
795 R_IS_IDLE(5 downto 4) <= R_IS_IDLE(3 downto 2);
796 rx_raw <= rx_raw_ps3;
797 if(R_TYPE_S = '1')then
803 rx_raw <= rx_raw_ps3;
804 R_IS_LF(5 downto 4) <= "00";
805 R_IS_RF(5 downto 4) <= "00";
806 R_IS_IDLE(5 downto 4) <= "00";
807 if(R_TYPE_C = '1')then
809 elsif(R_TYPE_D = '1')then
811 elsif(R_TYPE_T = '1' and (NEXT_TYPE_C = '1' or NEXT_TYPE_S = '1'))then
820 process(RXUSRCLK,reset)
823 reset_RXSyncRegs <= (others => '1');
825 elsif(RXUSRCLK'event and RXUSRCLK = '1')then
826 reset_RXSyncRegs <= reset_RXSyncRegs(1 downto 0) & '0';
827 if(BLOCK_LOCK = '0')then
829 elsif((GTX_RXHEADERVLD_dl(0) = '0' and and_reduce(rx_raw(3 downto 0)) = '0') or (GTX_RXHEADERVLD_dl(0) = '1' and and_reduce(rx_raw(39 downto 36)) = '0'))then
831 elsif((GTX_RXHEADERVLD_dl(0) = '0' and or_reduce(rx_raw(3 downto 0)) = '1') or (GTX_RXHEADERVLD_dl(0) = '1' and or_reduce(rx_raw(39 downto 36)) = '1'))then
838 if(RXUSRCLK'event and RXUSRCLK = '1')then
839 GTX_RXDVLD_q <= GTX_RXDVLD;
840 RX_FIFO_WE <= GTX_RXHEADERVLD_dl(1) or GTX_RXHEADERVLD_dl(0);
841 if(GTX_RXHEADERVLD_dl(0) = '0')then
842 rx_raw_mux <= rx_raw(35 downto 0);
843 R_IS_LF(6) <= R_IS_LF(4);
844 R_IS_RF(6) <= R_IS_RF(4);
845 if(R_IS_IDLE(4) = '1' or (R_IS_RF(6) = '1' and R_IS_RF(4) = '1') or (R_IS_LF(6) = '1' and R_IS_LF(4) = '1'))then
851 rx_raw_mux <= rx_raw(71 downto 36);
852 R_IS_LF(6) <= R_IS_LF(5);
853 R_IS_RF(6) <= R_IS_RF(5);
854 if(R_IS_IDLE(5) = '1' or (R_IS_RF(6) = '1' and R_IS_RF(5) = '1') or (R_IS_LF(6) = '1' and R_IS_LF(5) = '1'))then
860 RX_FIFO_DI(36) <= en_II and insert_IDLE_l and not(RX_FIFO_DI(36) and RX_FIFO_WE);
861 RX_FIFO_DI(35 downto 0) <= rx_raw_mux;
862 skip_RX_FIFO_WE <= not (RX_FIFO_WE and skip_RX_FIFO_WE) and en_DI and delete_IDLE_l;
863 if(inh = '1' or (RX_FIFO_WE = '1' and skip_RX_FIFO_WE = '1'))then
864 delete_IDLE_l <= '0';
865 elsif(GTX_RXDVLD_q = '1' and GTX_RXDVLD = '0')then
866 delete_IDLE_l <= delete_IDLE;
868 if(inh = '1' or (RX_FIFO_WE = '1' and RX_FIFO_DI(36) = '1'))then
869 insert_IDLE_l <= '0';
870 elsif(GTX_RXDVLD_q = '1' and GTX_RXDVLD = '0')then
871 insert_IDLE_l <= insert_IDLE;
875 process(RXUSRCLK,reset)
879 RX_FIFO_RA_G0SyncRegs <= (others => '0');
880 RX_FIFO_RA_G1SyncRegs <= (others => '0');
881 RX_FIFO_RA_G2SyncRegs <= (others => '0');
882 RX_FIFO_RA_G3SyncRegs <= (others => '0');
883 RX_FIFO_RA_P <= (others => '0');
884 RX_FIFO_WA_RA_D <= (others => '0');
886 elsif(RXUSRCLK'event and RXUSRCLK = '1')then
887 if(RX_FIFO_WE = '1' and skip_RX_FIFO_WE = '0')then
888 RX_FIFO_WA <= RX_FIFO_WA + 1;
890 RX_FIFO_RA_G0SyncRegs <= RX_FIFO_RA_G0SyncRegs(1 downto 0) & RX_FIFO_RA_G(0);
891 RX_FIFO_RA_G1SyncRegs <= RX_FIFO_RA_G1SyncRegs(1 downto 0) & RX_FIFO_RA_G(1);
892 RX_FIFO_RA_G2SyncRegs <= RX_FIFO_RA_G2SyncRegs(1 downto 0) & RX_FIFO_RA_G(2);
893 RX_FIFO_RA_G3SyncRegs <= RX_FIFO_RA_G3SyncRegs(1 downto 0) & RX_FIFO_RA_G(3);
894 RX_FIFO_RA_P(3) <= RX_FIFO_RA_G3SyncRegs(2);
895 RX_FIFO_RA_P(2) <= RX_FIFO_RA_G3SyncRegs(2) xor RX_FIFO_RA_G2SyncRegs(2);
896 RX_FIFO_RA_P(1) <= RX_FIFO_RA_G3SyncRegs(2) xor RX_FIFO_RA_G2SyncRegs(2) xor RX_FIFO_RA_G1SyncRegs(2);
897 RX_FIFO_RA_P(0) <= RX_FIFO_RA_G3SyncRegs(2) xor RX_FIFO_RA_G2SyncRegs(2) xor RX_FIFO_RA_G1SyncRegs(2) xor RX_FIFO_RA_G0SyncRegs(2);
898 RX_FIFO_WA_RA_D <= RX_FIFO_WA - RX_FIFO_RA_P;
899 if(RX_FIFO_WE = '1' and (skip_RX_FIFO_WE = '1' or RX_FIFO_DI(36) = '1'))then
901 elsif(inh_cntr(3) = '1')then
905 inh_cntr <= (others => '0');
906 elsif(GTX_RXHEADERVLD_dl(0) = '1')then
907 inh_cntr <= inh_cntr + 1;
911 i_delete_IDLE : ROM32X1
915 O => delete_IDLE,
-- ROM output
916 A0 => RX_FIFO_WA_RA_D
(0),
-- ROM address[0]
917 A1 => RX_FIFO_WA_RA_D
(1),
-- ROM address[1]
918 A2 => RX_FIFO_WA_RA_D
(2),
-- ROM address[2]
919 A3 => RX_FIFO_WA_RA_D
(3),
-- ROM address[3]
920 A4 => '0'
-- ROM address[4]
922 i_insert_IDLE : ROM32X1
926 O => insert_IDLE,
-- ROM output
927 A0 => RX_FIFO_WA_RA_D
(0),
-- ROM address[0]
928 A1 => RX_FIFO_WA_RA_D
(1),
-- ROM address[1]
929 A2 => RX_FIFO_WA_RA_D
(2),
-- ROM address[2]
930 A3 => RX_FIFO_WA_RA_D
(3),
-- ROM address[3]
931 A4 => '0'
-- ROM address[4]
933 g_RX_FIFO: for i in 0 to 36 generate
936 INIT => RxIdle
(i
)) -- Initial contents of RAM
938 DPO => RX_FIFO_DO
(i
),
-- Read-only 1-bit data output
939 SPO =>
open,
-- R/W 1-bit data output
940 A0 => RX_FIFO_WA
(0),
-- R/W address[0] input
941 A1 => RX_FIFO_WA
(1),
-- R/W address[1] input
942 A2 => RX_FIFO_WA
(2),
-- R/W address[2] input
943 A3 => RX_FIFO_WA
(3),
-- R/W address[3] input
944 A4 => '0',
-- R/W address[4] input
945 D => RX_FIFO_DI
(i
),
-- Write 1-bit data input
946 DPRA0 => RX_FIFO_RA
(0),
-- Read-only address[0] input
947 DPRA1 => RX_FIFO_RA
(1),
-- Read-only address[1] input
948 DPRA2 => RX_FIFO_RA
(2),
-- Read-only address[2] input
949 DPRA3 => RX_FIFO_RA
(3),
-- Read-only address[3] input
950 DPRA4 => ec_RX_FIFO_RAn ,
-- Read-only address[4] input
951 WCLK => RXUSRCLK,
-- Write clock input
952 WE => RX_FIFO_WE
-- Write enable input
955 -- add or remove idle(Ordered set) will be decided at the RX_FIFO write side
958 if(clk2x'event and clk2x = '1')then
959 ec_RX_FIFO_RAn <= RX_FIFO_DO(36);
961 RX_FIFO_RA <= (others => '0');
962 RX_FIFO_RA_G <= (others => '0');
964 if(ec_RX_FIFO_RAn = '0')then
965 RX_FIFO_RA <= RX_FIFO_RA +1;
967 RX_FIFO_RA_G(3) <= RX_FIFO_RA(3);
968 RX_FIFO_RA_G(2) <= RX_FIFO_RA(3) xor RX_FIFO_RA(2);
969 RX_FIFO_RA_G(1) <= RX_FIFO_RA(2) xor RX_FIFO_RA(1);
970 RX_FIFO_RA_G(0) <= RX_FIFO_RA(1) xor RX_FIFO_RA(0);
972 PhyEmacRxC <= RX_FIFO_DO(3 downto 0);
973 PhyEmacRxD <= RX_FIFO_DO(35 downto 4);