AMC13
Firmwares for the different applications of the AMC13 uTCA board made at Boston University
 All Classes Variables
XGbEPCS32.vhd
1 ----------------------------------------------------------------------------------
2 -- Company:
3 -- Engineer:
4 --
5 -- Create Date: 09:16:59 11/24/2012
6 -- Design Name:
7 -- Module Name: EMAC_GXPCS - Behavioral
8 -- Project Name:
9 -- Target Devices:
10 -- Tool versions:
11 -- Description:
12 --
13 -- Dependencies:
14 --
15 -- Revision:
16 -- Revision 0.01 - File Created
17 -- Additional Comments:
18 --
19 ----------------------------------------------------------------------------------
20 library IEEE;
21 use IEEE.STD_LOGIC_1164.ALL;
22 use IEEE.STD_LOGIC_ARITH.ALL;
23 use IEEE.STD_LOGIC_UNSIGNED.ALL;
24 use IEEE.std_logic_misc.all;
25 
26 -- Uncomment the following library declaration if using
27 -- arithmetic functions with Signed or Unsigned values
28 --use IEEE.NUMERIC_STD.ALL;
29 
30 -- Uncomment the following library declaration if instantiating
31 -- any Xilinx primitives in this code.
32 library UNISIM;
33 use UNISIM.VComponents.all;
34 
35 entity XGbEPCS32 is
36  Port (
37  reset : IN std_logic;
38  clk2x : IN std_logic; -- 2xSFP_REFCLK 312.5MHz norminal
39  clk : IN std_logic;
40  TXUSRCLK : IN std_logic;
41  TX_high : IN std_logic; -- in clk2x domain, TX_high = clk
42  RXUSRCLK : IN std_logic;
43  RXRESETDONE : IN std_logic;
44  RESET_TXSync : IN std_logic;
45  inh_TX : IN std_logic;
46  GTX_TXD : out STD_LOGIC_VECTOR (31 downto 0) := (others => '0');
47  GTX_TXHEADER : out STD_LOGIC_VECTOR (1 downto 0) := (others => '0');
48  GTX_TX_PAUSE : IN std_logic; -- sequence counter = "011111"
49  GTX_RXD : in STD_LOGIC_VECTOR (31 downto 0);
50  GTX_RXDVLD : in STD_LOGIC;
51  GTX_RXHEADER : in STD_LOGIC_VECTOR (1 downto 0);
52  GTX_RXHEADERVLD : in STD_LOGIC;
53  GTX_RXGOOD : out STD_LOGIC;
54  GTX_RXGEARBOXSLIP_OUT : out STD_LOGIC := '0';
55  EmacPhyTxC : in STD_LOGIC_VECTOR (3 downto 0);
56  EmacPhyTxD : in STD_LOGIC_VECTOR (31 downto 0);
57  PhyEmacRxC : out STD_LOGIC_VECTOR (3 downto 0) := (others => '0');
58  PhyEmacRxD : out STD_LOGIC_VECTOR (31 downto 0) := (others => '0');
59  status : out STD_LOGIC_VECTOR (31 downto 0)
60  );
61 end XGbEPCS32;
62 
63 architecture Behavioral of XGbEPCS32 is
64 COMPONENT BLOCK_SYNC_SM
65  PORT(
66  RXHEADER_IN : IN std_logic_vector(2 downto 0);
67  RXHEADERVALID_IN : IN std_logic;
68  USER_CLK : IN std_logic;
69  SYSTEM_RESET : IN std_logic;
70  BLOCKSYNC_OUT : OUT std_logic;
71  RXGEARBOXSLIP_OUT : OUT std_logic
72  );
73 END COMPONENT;
74 COMPONENT SCRAMBLER
75 generic
76 (
77  TX_DATA_WIDTH : integer := 32
78 );
79  PORT(
80  UNSCRAMBLED_DATA_IN : IN std_logic_vector((TX_DATA_WIDTH-1) downto 0);
81  DATA_VALID_IN : IN std_logic;
82  USER_CLK : IN std_logic;
83  SYSTEM_RESET : IN std_logic;
84  SCRAMBLED_DATA_OUT : OUT std_logic_vector((TX_DATA_WIDTH-1) downto 0)
85  );
86 END COMPONENT;
87 COMPONENT DESCRAMBLER
88 generic
89 (
90  RX_DATA_WIDTH : integer := 32
91 );
92  PORT(
93  SCRAMBLED_DATA_IN : IN std_logic_vector((RX_DATA_WIDTH-1) downto 0);
94  DATA_VALID_IN : IN std_logic;
95  USER_CLK : IN std_logic;
96  SYSTEM_RESET : IN std_logic;
97  UNSCRAMBLED_DATA_OUT : OUT std_logic_vector((RX_DATA_WIDTH-1) downto 0)
98  );
99 END COMPONENT;
100 constant EBLOCK : std_logic_vector(63 downto 0) := x"1e1e1e1e1e1e1e1e";
101 constant LBLOCK : std_logic_vector(63 downto 0) := x"0100000001000055";
102 constant R_FAULT : std_logic_vector(31 downto 0) := x"0200009c";
103 constant LBLOCK_R : std_logic_vector(71 downto 0) := x"0100009c10100009c1";
104 constant EBLOCK_R : std_logic_vector(71 downto 0) := x"fefefefeffefefefef";
105 type array37x32 is array(0 to 36) of bit_vector(31 downto 0);
106 constant RxIdle : array37x32 := (x"ffff0000",x"ffff0000",x"ffff0000",x"ffff0000",
107  x"ffff0000",x"ffff0000",x"ffff0000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",
108  x"ffff0000",x"ffff0000",x"ffff0000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",
109  x"ffff0000",x"ffff0000",x"ffff0000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",
110  x"ffff0000",x"ffff0000",x"ffff0000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",
111  x"00000000");
112 type state is (TX_INIT, TX_C, TX_D, TX_T, TX_E);
113 signal T_state : state := TX_INIT;
114 signal EmacPhyTxC_q : std_logic_vector(3 downto 0) := (others => '0');
115 signal EmacPhyTxD_q : std_logic_vector(31 downto 0) := (others => '0');
116 signal TxC : std_logic_vector(7 downto 0) := (others => '0');
117 signal TxD : std_logic_vector(63 downto 0) := (others => '0');
118 signal TxD_q : std_logic_vector(63 downto 0) := (others => '0');
119 signal c_coded : std_logic_vector(55 downto 0) := (others => '0');
120 signal tx_coded : std_logic_vector(65 downto 0) := (others => '0');
121 signal T_TYPE_C : std_logic := '0';
122 signal T_TYPE_D : std_logic := '0';
123 signal T_TYPE_S : std_logic := '0';
124 signal T_TYPE_T : std_logic := '0';
125 signal T_IS_D : std_logic := '0';
126 signal T_IS_O : std_logic_vector(1 downto 0) := (others => '0');
127 signal T_IS_S : std_logic_vector(1 downto 0) := (others => '0');
128 signal T_IS_C : std_logic_vector(7 downto 0) := (others => '0');
129 signal T_IS_E : std_logic_vector(7 downto 0) := (others => '0');
130 signal T_IS_T : std_logic_vector(7 downto 0) := (others => '0');
131 signal GTX_TX_PAUSE_q : std_logic := '0';
132 signal TX_FIFO_DI : std_logic_vector(33 downto 0) := (others => '0');
133 signal TX_FIFO_DO : std_logic_vector(33 downto 0) := (others => '0');
134 signal TX_FIFO_wa : std_logic_vector(3 downto 0) := (others => '0');
135 signal TX_FIFO_ra : std_logic_vector(3 downto 0) := (others => '0');
136 signal GTX_RXHEADER_IN : std_logic_vector(2 downto 0) := (others => '0');
137 signal BLOCK_LOCK : std_logic := '0';
138 signal BLOCK_SYNC_SM_RESET : std_logic := '0';
139 signal BLOCK_NOT_LOCK : std_logic := '0';
140 signal GTX_RXHEADERVLD_dl : std_logic_vector(1 downto 0) := (others => '0');
141 signal GTX_RXHEADER_dl0 : std_logic_vector(1 downto 0) := (others => '0');
142 signal TX_UNSCRAMBLED_DATA : std_logic_vector(65 downto 0) := (others => '0');
143 signal TX_UNSCRAMBLED_DATA_MUX : std_logic_vector(33 downto 0) := (others => '0');
144 signal RX_UNSCRAMBLED_DATA : std_logic_vector(63 downto 0) := (others => '0');
145 signal RX_UNSCRAMBLED_DATA_OUT : std_logic_vector(31 downto 0) := (others => '0');
146 signal RXHEADER : std_logic_vector(1 downto 0) := (others => '0');
147 type Rstate is (RX_INIT, RX_C, RX_D, RX_T, RX_E);
148 signal R_state : Rstate := RX_INIT;
149 signal RxC : std_logic_vector(7 downto 0) := (others => '0');
150 signal RxD : std_logic_vector(63 downto 0) := (others => '0');
151 signal c_raw : std_logic_vector(63 downto 0) := (others => '0');
152 signal rx_raw : std_logic_vector(71 downto 0) := (others => '0');
153 signal rx_raw_ps2 : std_logic_vector(71 downto 0) := (others => '0');
154 signal rx_raw_ps3 : std_logic_vector(71 downto 0) := (others => '0');
155 signal rx_raw_mux : std_logic_vector(35 downto 0) := (others => '0');
156 signal R_TYPE_C : std_logic := '0';
157 signal R_TYPE_D : std_logic := '0';
158 signal R_TYPE_S : std_logic := '0';
159 signal R_TYPE_T : std_logic := '0';
160 signal NEXT_TYPE_C : std_logic := '0';
161 signal NEXT_TYPE_D : std_logic := '0';
162 signal NEXT_TYPE_S : std_logic := '0';
163 signal NEXT_TYPE_T : std_logic := '0';
164 signal R_IS_D : std_logic := '0';
165 signal R_IS_T : std_logic := '0';
166 signal Legal_O : std_logic_vector(1 downto 0) := (others => '0');
167 signal R_IS_O : std_logic_vector(1 downto 0) := (others => '0');
168 signal R_IS_S : std_logic_vector(1 downto 0) := (others => '0');
169 signal R_IS_C : std_logic_vector(7 downto 0) := (others => '0');
170 signal R_IS_E : std_logic_vector(7 downto 0) := (others => '0');
171 signal RX_FIFO_DI : std_logic_vector(36 downto 0) := (others => '0');
172 signal RX_FIFO_DO : std_logic_vector(36 downto 0) := (others => '0');
173 signal RX_FIFO_WA : std_logic_vector(3 downto 0) := (others => '0');
174 signal RX_FIFO_RA : std_logic_vector(3 downto 0) := (others => '0');
175 signal RX_FIFO_RA_G : std_logic_vector(3 downto 0) := (others => '0');
176 signal RX_FIFO_RA_P : std_logic_vector(3 downto 0) := (others => '0');
177 signal RX_FIFO_WA_RA_D : std_logic_vector(3 downto 0) := (others => '0');
178 signal RX_FIFO_RA_G0SyncRegs : std_logic_vector(2 downto 0) := (others => '0');
179 signal RX_FIFO_RA_G1SyncRegs : std_logic_vector(2 downto 0) := (others => '0');
180 signal RX_FIFO_RA_G2SyncRegs : std_logic_vector(2 downto 0) := (others => '0');
181 signal RX_FIFO_RA_G3SyncRegs : std_logic_vector(2 downto 0) := (others => '0');
182 signal RX_FIFO_WE : std_logic := '0';
183 signal GTX_RXDVLD_q : std_logic := '0';
184 signal skip_RX_FIFO_WE : std_logic := '0';
185 signal ec_RX_FIFO_RAn : std_logic := '0';
186 signal insert_IDLE : std_logic := '0';
187 signal delete_IDLE : std_logic := '0';
188 signal insert_IDLE_l : std_logic := '0';
189 signal delete_IDLE_l : std_logic := '0';
190 signal R_IS_RF : std_logic_vector(6 downto 0) := (others => '0');
191 signal R_IS_LF : std_logic_vector(6 downto 0) := (others => '0');
192 signal R_IS_IDLE : std_logic_vector(5 downto 0) := (others => '0');
193 signal en_DI : std_logic := '0';
194 signal en_II : std_logic := '0';
195 signal T4567 : std_logic := '0';
196 signal inh : std_logic := '0';
197 signal inh_cntr : std_logic_vector(3 downto 0) := (others => '0');
198 signal reset_RXSyncRegs : std_logic_vector(2 downto 0) := (others => '0');
199 signal RXRESETDONE_SyncRegs : std_logic_vector(3 downto 0) := (others => '0');
200 signal RXGOOD_cntr : std_logic_vector(4 downto 0) := (others => '0');
201 begin
202 process(clk2x)
203 begin
204  if(clk2x'event and clk2x = '1')then
205  if(TX_high = '0')then
206  EmacPhyTxC_q <= EmacPhyTxC;
207  EmacPhyTxD_q <= EmacPhyTxD;
208  else
209  TxC <= EmacPhyTxC & EmacPhyTxC_q;
210  TxD <= EmacPhyTxD & EmacPhyTxD_q;
211  end if;
212  if(TX_high = '1')then
213  TX_UNSCRAMBLED_DATA_MUX <= '1' & TX_UNSCRAMBLED_DATA(64) & TX_UNSCRAMBLED_DATA(31 downto 0);
214  else
215  TX_UNSCRAMBLED_DATA_MUX <= '0' & TX_UNSCRAMBLED_DATA(64 downto 32);
216  end if;
217  TX_FIFO_DI(33 downto 32) <= TX_UNSCRAMBLED_DATA_MUX(33 downto 32);
218  end if;
219 end process;
220 process(clk)
221 begin
222  if(clk'event and clk = '1')then
223  if(TxC(3 downto 0) = x"1" and TxD(31 downto 0) = R_FAULT)then
224  T_IS_O(0) <= '1';
225  else
226  T_IS_O(0) <= '0';
227  end if;
228  if(TxC(7 downto 4) = x"1" and TxD(63 downto 32) = R_FAULT)then
229  T_IS_O(1) <= '1';
230  else
231  T_IS_O(1) <= '0';
232  end if;
233  if(TxC = x"01" and TxD(7 downto 0) = x"fb")then
234  T_IS_S(0) <= '1';
235  else
236  T_IS_S(0) <= '0';
237  end if;
238  if(TxC(7 downto 4) = x"1" and TxD(39 downto 32) = x"fb")then
239  T_IS_S(1) <= '1';
240  else
241  T_IS_S(1) <= '0';
242  end if;
243  for i in 0 to 7 loop
244  if(TxC(i) = '1' and TxD(i*8+7 downto i*8) = x"07")then
245  T_IS_C(i) <= '1';
246  else
247  T_IS_C(i) <= '0';
248  end if;
249  if(TxC(i) = '1' and TxD(i*8+7 downto i*8) = x"fe")then
250  T_IS_E(i) <= '1';
251  c_coded(I*7+6 downto i*7) <= "0011110";
252  else
253  T_IS_E(i) <= '0';
254  c_coded(I*7+6 downto i*7) <= "0000000";
255  end if;
256  end loop;
257  if(TxC(0) = '1' and TxD(7 downto 0) = x"fd")then
258  T_IS_T(0) <= '1';
259  else
260  T_IS_T(0) <= '0';
261  end if;
262  if(TxC(1 downto 0) = "10" and TxD(15 downto 8) = x"fd")then
263  T_IS_T(1) <= '1';
264  else
265  T_IS_T(1) <= '0';
266  end if;
267  if(TxC(2 downto 0) = "100" and TxD(23 downto 16) = x"fd")then
268  T_IS_T(2) <= '1';
269  else
270  T_IS_T(2) <= '0';
271  end if;
272  if(TxC(3 downto 0) = "1000" and TxD(31 downto 24) = x"fd")then
273  T_IS_T(3) <= '1';
274  else
275  T_IS_T(3) <= '0';
276  end if;
277  if(TxC(4 downto 0) = "10000" and TxD(39 downto 32) = x"fd")then
278  T_IS_T(4) <= '1';
279  else
280  T_IS_T(4) <= '0';
281  end if;
282  if(TxC(5 downto 0) = "100000" and TxD(47 downto 40) = x"fd")then
283  T_IS_T(5) <= '1';
284  else
285  T_IS_T(5) <= '0';
286  end if;
287  if(TxC(6 downto 0) = "1000000" and TxD(55 downto 48) = x"fd")then
288  T_IS_T(6) <= '1';
289  else
290  T_IS_T(6) <= '0';
291  end if;
292  if(TxC(7 downto 0) = "10000000" and TxD(63 downto 56) = x"fd")then
293  T_IS_T(7) <= '1';
294  else
295  T_IS_T(7) <= '0';
296  end if;
297  T_IS_D <= not or_reduce(TxC);
298  if(and_reduce(T_IS_C) = '1' or (T_IS_O(0) = '1' and T_IS_C(7 downto 4) = not T_IS_E(7 downto 4)) or (T_IS_O(1) = '1' and T_IS_C(3 downto 0) = not T_IS_E(3 downto 0)) or T_IS_O = "11")then
299  T_TYPE_C <= '1';
300  else
301  T_TYPE_C <= '0';
302  end if;
303  if(T_IS_S(0) = '1' or (T_IS_S(1) = '1' and (T_IS_C(3 downto 0) = not T_IS_E(3 downto 0) or T_IS_O(0) = '1')))then
304  T_TYPE_S <= '1';
305  else
306  T_TYPE_S <= '0';
307  end if;
308  T_TYPE_D <= T_IS_D;
309  T_TYPE_T <= '0';
310  if(T_IS_T(0) = '1' and T_IS_C(7 downto 1) = not T_IS_E(7 downto 1))then
311  T_TYPE_T <= '1';
312  end if;
313  if(T_IS_T(1) = '1' and T_IS_C(7 downto 2) = not T_IS_E(7 downto 2))then
314  T_TYPE_T <= '1';
315  end if;
316  if(T_IS_T(2) = '1' and T_IS_C(7 downto 3) = not T_IS_E(7 downto 3))then
317  T_TYPE_T <= '1';
318  end if;
319  if(T_IS_T(3) = '1' and T_IS_C(7 downto 4) = not T_IS_E(7 downto 4))then
320  T_TYPE_T <= '1';
321  end if;
322  if(T_IS_T(4) = '1' and T_IS_C(7 downto 5) = not T_IS_E(7 downto 5))then
323  T_TYPE_T <= '1';
324  end if;
325  if(T_IS_T(5) = '1' and T_IS_C(7 downto 6) = not T_IS_E(7 downto 6))then
326  T_TYPE_T <= '1';
327  end if;
328  if(T_IS_T(6) = '1' and T_IS_C(7) = not T_IS_E(7))then
329  T_TYPE_T <= '1';
330  end if;
331  if(T_IS_T(7) = '1')then
332  T_TYPE_T <= '1';
333  end if;
334  TxD_q <= TxD;
335  if(T_IS_C = x"ff")then
336  tx_coded(63 downto 0) <= x"000000000000001e";
337  end if;
338  if(T_IS_O(1) = '1' and T_IS_C(3 downto 0) = not T_IS_E(3 downto 0))then
339  tx_coded(63 downto 0) <= TxD_q(63 downto 40) & x"0" & c_coded(27 downto 0) & x"2d";
340  end if;
341  if(T_IS_S(1) = '1' and T_IS_C(3 downto 0) = not T_IS_E(3 downto 0))then
342  tx_coded(63 downto 0) <= TxD_q(63 downto 40) & x"0" & c_coded(27 downto 0) & x"33";
343  end if;
344  if(T_IS_O(0) = '1' and T_IS_C(7 downto 4) = not T_IS_E(7 downto 4))then
345  tx_coded(63 downto 0) <= c_coded(55 downto 28) & x"0" & TxD_q(31 downto 8) & x"4b";
346  end if;
347  if(T_IS_O = "11")then
348  tx_coded(63 downto 0) <= TxD_q(63 downto 40) & x"00" & TxD_q(31 downto 8) & x"55";
349  end if;
350  if(T_IS_S(1) = '1' and T_IS_O(0) = '1')then
351  tx_coded(63 downto 0) <= TxD_q(63 downto 40) & TxD_q(31 downto 0) & x"66";
352  end if;
353  if(T_IS_S(0) = '1')then
354  tx_coded(63 downto 0) <= TxD_q(63 downto 8) & x"78";
355  end if;
356  if(T_IS_T(0) = '1')then
357  tx_coded(63 downto 0) <= c_coded(55 downto 7) & "0000000" & x"87";
358  end if;
359  if(T_IS_T(1) = '1')then
360  tx_coded(63 downto 0) <= c_coded(55 downto 14) & "000000" & TxD_q(7 downto 0) & x"99";
361  end if;
362  if(T_IS_T(2) = '1')then
363  tx_coded(63 downto 0) <= c_coded(55 downto 21) & "00000" & TxD_q(15 downto 0) & x"aa";
364  end if;
365  if(T_IS_T(3) = '1')then
366  tx_coded(63 downto 0) <= c_coded(55 downto 28) & "0000" & TxD_q(23 downto 0) & x"b4";
367  end if;
368  if(T_IS_T(4) = '1')then
369  tx_coded(63 downto 0) <= c_coded(55 downto 35) & "000" & TxD_q(31 downto 0) & x"cc";
370  end if;
371  if(T_IS_T(5) = '1')then
372  tx_coded(63 downto 0) <= c_coded(55 downto 42) & "00" & TxD_q(39 downto 0) & x"d2";
373  end if;
374  if(T_IS_T(6) = '1')then
375  tx_coded(63 downto 0) <= c_coded(55 downto 49) & '0' & TxD_q(47 downto 0) & x"e1";
376  end if;
377  if(T_IS_T(7) = '1')then
378  tx_coded(63 downto 0) <= TxD_q(55 downto 0) & x"ff";
379  end if;
380  if(T_IS_D = '1')then
381  tx_coded(63 downto 0) <= TxD_q;
382  end if;
383  if(T_IS_D = '1')then
384  tx_coded(65 downto 64) <= "01";
385  else
386  tx_coded(65 downto 64) <= "10";
387  end if;
388  if(reset = '1')then
389  T_state <= TX_INIT;
390  TX_UNSCRAMBLED_DATA <= "10" & LBLOCK;
391  else
392  case T_state is
393  when TX_INIT =>
394  TX_UNSCRAMBLED_DATA <= tx_coded;
395  if(T_TYPE_C = '1')then
396  T_state <= TX_C;
397  elsif(T_TYPE_S = '1')then
398  T_state <= TX_D;
399  else
400  T_state <= TX_E;
401  TX_UNSCRAMBLED_DATA <= "10" & EBLOCK;
402  end if;
403  when TX_C =>
404  TX_UNSCRAMBLED_DATA <= tx_coded;
405  if(T_TYPE_S = '1')then
406  T_state <= TX_D;
407  elsif(T_TYPE_C = '0')then
408  T_state <= TX_E;
409  TX_UNSCRAMBLED_DATA <= "10" & EBLOCK;
410  end if;
411  when TX_D =>
412  TX_UNSCRAMBLED_DATA <= tx_coded;
413  if(T_TYPE_T = '1')then
414  T_state <= TX_T;
415  elsif(T_TYPE_D = '0')then
416  T_state <= TX_E;
417  TX_UNSCRAMBLED_DATA <= "10" & EBLOCK;
418  end if;
419  when TX_T =>
420  TX_UNSCRAMBLED_DATA <= tx_coded;
421  if(T_TYPE_C = '1')then
422  T_state <= TX_C;
423  elsif(T_TYPE_S = '1')then
424  T_state <= TX_D;
425  else
426  T_state <= TX_E;
427  TX_UNSCRAMBLED_DATA <= "10" & EBLOCK;
428  end if;
429  when others =>
430  TX_UNSCRAMBLED_DATA <= tx_coded;
431  if(T_TYPE_C = '1')then
432  T_state <= TX_C;
433  elsif(T_TYPE_D = '1')then
434  T_state <= TX_D;
435  elsif(T_TYPE_T = '1')then
436  T_state <= TX_T;
437  else
438  TX_UNSCRAMBLED_DATA <= "10" & EBLOCK;
439  end if;
440  end case;
441  end if;
442  end if;
443 end process;
444 process(clk2x,reset_TXSync)
445 begin
446  if(reset_TXSync = '1')then
447  TX_FIFO_WA <= x"8";
448  elsif(clk2x'event and clk2x = '1')then
449  TX_FIFO_WA <= TX_FIFO_WA + 1;
450  end if;
451 end process;
452 g_TX_FIFO: for i in 0 to 33 generate
453  i_TX_FIFO : RAM32X1D
454  port map (
455  DPO => TX_FIFO_DO(i), -- Read-only 1-bit data output
456  SPO => open, -- R/W 1-bit data output
457  A0 => TX_FIFO_WA(0), -- R/W address[0] input bit
458  A1 => TX_FIFO_WA(1), -- R/W address[1] input bit
459  A2 => TX_FIFO_WA(2), -- R/W address[2] input bit
460  A3 => TX_FIFO_WA(3), -- R/W address[3] input bit
461  A4 => '0', -- R/W address[4] input bit
462  D => TX_FIFO_DI(i), -- Write 1-bit data input
463  DPRA0 => TX_FIFO_RA(0), -- Read-only address[0] input bit
464  DPRA1 => TX_FIFO_RA(1), -- Read-only address[1] input bit
465  DPRA2 => TX_FIFO_RA(2), -- Read-only address[2] input bit
466  DPRA3 => TX_FIFO_RA(3), -- Read-only address[3] input bit
467  DPRA4 => '0', -- Read-only address[4] input bit
468  WCLK => clk2x, -- Write clock input
469  WE => '1' -- Write enable input
470  );
471 end generate;
472 process(TXUSRCLK)
473 begin
474  if(TXUSRCLK'event and TXUSRCLK = '1')then
475  if(reset_TXSync = '1')then
476  TX_FIFO_RA <= (others => '0');
477  elsif(GTX_TX_PAUSE = '0' or (TX_FIFO_DO(33) = '1' and GTX_TX_PAUSE_q = '0'))then
478  TX_FIFO_RA <= TX_FIFO_RA + 1;
479  end if;
480  if(inh_TX = '1')then
481  GTX_TXHEADER <= "00";
482  else
483  GTX_TXHEADER <= not TX_FIFO_DO(32) & TX_FIFO_DO(32);
484  end if;
485  GTX_TX_PAUSE_q <= GTX_TX_PAUSE;
486  if(inh_TX = '1')then
487  GTX_TXD <= (others => '0');
488  else
489  GTX_TXD <= TX_FIFO_DO(31 downto 0);
490  end if;
491  end if;
492 end process;
493 process(RXUSRCLK,RXRESETDONE)
494 begin
495  if(RXRESETDONE = '0')then
496  RXRESETDONE_SyncRegs <= (others => '0');
497  elsif(RXUSRCLK'event and RXUSRCLK = '1')then
498  RXRESETDONE_SyncRegs <= RXRESETDONE_SyncRegs(2 downto 0) & '1';
499  end if;
500 end process;
501 i_BLOCK_SYNC_SM: BLOCK_SYNC_SM PORT MAP(
502  BLOCKSYNC_OUT => BLOCK_LOCK,
503  RXGEARBOXSLIP_OUT => GTX_RXGEARBOXSLIP_OUT,
504  RXHEADER_IN => GTX_RXHEADER_IN,
505  RXHEADERVALID_IN => GTX_RXHEADERVLD,
506  USER_CLK => RXUSRCLK,
507  SYSTEM_RESET => BLOCK_SYNC_SM_RESET
508  );
509 BLOCK_SYNC_SM_RESET <= not RXRESETDONE_SyncRegs(3);
510 GTX_RXHEADER_IN <= '0' & GTX_RXHEADER;
511 BLOCK_NOT_LOCK <= not BLOCK_LOCK;
512 i_SCRAMBLER: SCRAMBLER PORT MAP(
513  UNSCRAMBLED_DATA_IN => TX_UNSCRAMBLED_DATA_MUX (31 downto 0),
514  SCRAMBLED_DATA_OUT => TX_FIFO_DI(31 downto 0),
515  DATA_VALID_IN => '1',
516  USER_CLK => clk2x,
517  SYSTEM_RESET => RESET_TXSync
518  );
519 -- Rx code follows
520 i_DESCRAMBLER: DESCRAMBLER PORT MAP(
521  SCRAMBLED_DATA_IN => GTX_RXD,
522  UNSCRAMBLED_DATA_OUT => RX_UNSCRAMBLED_DATA_OUT ,
523  DATA_VALID_IN => GTX_RXDVLD,
524  USER_CLK => RXUSRCLK,
525  SYSTEM_RESET => BLOCK_NOT_LOCK
526  );
527 process(RXUSRCLK)
528 begin
529  if(RXUSRCLK'event and RXUSRCLK = '1')then
530  GTX_RXHEADERVLD_dl <= GTX_RXHEADERVLD_dl(0) & GTX_RXHEADERVLD;
531  if(GTX_RXHEADERVLD = '1')then
532  GTX_RXHEADER_dl0 <= GTX_RXHEADER;
533  end if;
534  if(GTX_RXHEADERVLD_dl(0) = '1')then
535  RX_UNSCRAMBLED_DATA(31 downto 0) <= RX_UNSCRAMBLED_DATA_OUT;
536  end if;
537  if(GTX_RXHEADERVLD_dl(1) = '1')then
538  RX_UNSCRAMBLED_DATA(63 downto 32) <= RX_UNSCRAMBLED_DATA_OUT;
539  end if;
540  if(GTX_RXHEADERVLD_dl(0) = '1')then
541  if(reset_RXSyncRegs(2) = '1' or R_state = RX_E)then
542  GTX_RXGOOD <= '0';
543  elsif(RXGOOD_cntr(4) = '1')then
544  GTX_RXGOOD <= '1';
545  end if;
546  if(reset_RXSyncRegs(2) = '1' or R_state = RX_E)then
547  RXGOOD_cntr <= (others => '0');
548  elsif(RXGOOD_cntr(4) = '0')then
549  RXGOOD_cntr <= RXGOOD_cntr + 1;
550  end if;
551 -- pipeline stage 1
552  RXHEADER <= GTX_RXHEADER_dl0;
553  case RX_UNSCRAMBLED_DATA(3 downto 0) is
554  when x"1" => RxC <= x"c0";
555  when x"2" => RxC <= x"e0";
556  when x"3" | x"d" => RxC <= x"1f";
557  when x"4" => RxC <= x"f8";
558  when x"5" | x"6" => RxC <= x"11";
559  when x"7" | x"e" => RxC <= x"ff";
560  when x"8" => RxC <= x"01";
561  when x"9" => RxC <= x"fe";
562  when x"a" => RxC <= x"fc";
563  when x"b" => RxC <= x"f1";
564  when x"c" => RxC <= x"f0";
565  when x"f" => RxC <= x"80";
566  when others => RxC <= x"00";
567  end case;
568  RxD <= RX_UNSCRAMBLED_DATA;
569  for i in 0 to 7 loop
570  if(RX_UNSCRAMBLED_DATA(i*7+14 downto i*7+8) = "0000000")then
571  R_IS_C(i) <= '1';
572  else
573  R_IS_C(i) <= '0';
574  end if;
575  if(RX_UNSCRAMBLED_DATA(i*7+14 downto i*7+8) = "0011110")then
576  R_IS_E(i) <= '1';
577  c_raw(I*8+7 downto i*8) <= x"fe";
578  else
579  R_IS_E(i) <= '0';
580  c_raw(I*8+7 downto i*8) <= x"07";
581  end if;
582  end loop;
583  if(RX_UNSCRAMBLED_DATA(35 downto 8) = x"0010000" or RX_UNSCRAMBLED_DATA(35 downto 8) = x"0020000")then
584  Legal_O(0) <= '1';
585  else
586  Legal_O(0) <= '0';
587  end if;
588  if(RX_UNSCRAMBLED_DATA(63 downto 36) = x"0100000" or RX_UNSCRAMBLED_DATA(63 downto 36) = x"0200000")then
589  Legal_O(1) <= '1';
590  else
591  Legal_O(1) <= '0';
592  end if;
593  if(RX_UNSCRAMBLED_DATA(7 downto 4) = x"4" or RX_UNSCRAMBLED_DATA(7 downto 4) = x"5" or RX_UNSCRAMBLED_DATA(7 downto 4) = x"6")then
594  R_IS_O(0) <= '1';
595  else
596  R_IS_O(0) <= '0';
597  end if;
598  if(RX_UNSCRAMBLED_DATA(7 downto 4) = x"2" or RX_UNSCRAMBLED_DATA(7 downto 4) = x"5")then
599  R_IS_O(1) <= '1';
600  else
601  R_IS_O(1) <= '0';
602  end if;
603  if(RX_UNSCRAMBLED_DATA(7 downto 4) = x"7")then
604  R_IS_S(0) <= '1';
605  else
606  R_IS_S(0) <= '0';
607  end if;
608  if(RX_UNSCRAMBLED_DATA(7 downto 4) = x"3" or RX_UNSCRAMBLED_DATA(7 downto 4) = x"6")then
609  R_IS_S(1) <= '1';
610  else
611  R_IS_S(1) <= '0';
612  end if;
613  if(RXHEADER = "01")then
614  R_IS_D <= '1';
615  else
616  R_IS_D <= '0';
617  end if;
618  if(RX_UNSCRAMBLED_DATA(7) = '1')then
619  case RX_UNSCRAMBLED_DATA(6 downto 4) is
620  when "000" => R_IS_T <= not or_reduce(RX_UNSCRAMBLED_DATA(14 downto 8));
621  when "001" => R_IS_T <= not or_reduce(RX_UNSCRAMBLED_DATA(21 downto 16));
622  when "010" => R_IS_T <= not or_reduce(RX_UNSCRAMBLED_DATA(28 downto 24));
623  when "011" => R_IS_T <= not or_reduce(RX_UNSCRAMBLED_DATA(35 downto 32));
624  when "100" => R_IS_T <= not or_reduce(RX_UNSCRAMBLED_DATA(42 downto 40));
625  when "101" => R_IS_T <= not or_reduce(RX_UNSCRAMBLED_DATA(49 downto 48));
626  when "110" => R_IS_T <= not RX_UNSCRAMBLED_DATA(56);
627  when others => R_IS_T <= '1';
628  end case;
629  else
630  R_IS_T <= '0';
631  end if;
632 -- pipeline stage 2
633  if(R_IS_D = '1')then
634  NEXT_TYPE_D <= '1';
635  NEXT_TYPE_C <= '0';
636  NEXT_TYPE_S <= '0';
637  NEXT_TYPE_T <= '0';
638  rx_raw_ps2 <= x"00" & RxD;
639  R_IS_IDLE(1 downto 0) <= "00";
640  R_IS_RF(1 downto 0) <= "00";
641  R_IS_LF(1 downto 0) <= "00";
642  else
643  R_IS_IDLE(0) <= and_reduce(RxC(3 downto 0)) and and_reduce(R_IS_C(3 downto 0)) and (not NEXT_TYPE_T or not T4567) and not R_IS_T;
644  R_IS_IDLE(1) <= and_reduce(RxC(7 downto 4)) and and_reduce(R_IS_C(7 downto 4)) and not R_IS_T;
645  R_IS_RF(0) <= R_IS_O(0) and Legal_O(0) and not RxD(24);
646  R_IS_RF(1) <= R_IS_O(1) and Legal_O(1) and not RxD(56);
647  R_IS_LF(0) <= R_IS_O(0) and Legal_O(0) and RxD(24);
648  R_IS_LF(1) <= R_IS_O(1) and Legal_O(1) and RxD(56);
649  NEXT_TYPE_D <= '0';
650  rx_raw_ps2(71 downto 64) <= RxC;
651  if(RxC = x"ff" and R_IS_C = x"ff" and R_IS_T = '0')then
652  NEXT_TYPE_C <= '1';
653  rx_raw_ps2(63 downto 0) <= c_raw;
654  elsif(Legal_O(0) = '1' and R_IS_O(0) = '1' and R_IS_C(7 downto 4) = not R_IS_E(7 downto 4) and RxC(7 downto 4) = x"f")then
655  NEXT_TYPE_C <= '1';
656  rx_raw_ps2(63 downto 0) <= c_raw(63 downto 32) & RxD(31 downto 8) & x"9c";
657  elsif(Legal_O(1) = '1' and R_IS_O(1) = '1' and R_IS_C(3 downto 0) = not R_IS_E(3 downto 0) and RxC(3 downto 0) = x"f")then
658  NEXT_TYPE_C <= '1';
659  rx_raw_ps2(63 downto 0) <= RxD(63 downto 40) & x"9c" & c_raw(31 downto 0);
660  elsif(Legal_O = "11" and R_IS_O = "11")then
661  NEXT_TYPE_C <= '1';
662  rx_raw_ps2(63 downto 0) <= RxD(63 downto 40) & x"9c" & RxD(31 downto 8) & x"9c";
663  else
664  NEXT_TYPE_C <= '0';
665  end if;
666  if(R_IS_S(0) = '1')then
667  NEXT_TYPE_S <= '1';
668  rx_raw_ps2(63 downto 0) <= RxD(63 downto 8) & x"fb";
669  elsif(R_IS_S(1) = '1' and R_IS_C(3 downto 0) = not R_IS_E(3 downto 0) and RxC(3 downto 0) = x"f")then
670  NEXT_TYPE_S <= '1';
671  rx_raw_ps2(63 downto 0) <= RxD(63 downto 40) & x"fb" & c_raw(31 downto 0);
672  elsif(R_IS_S(1) = '1' and Legal_O(1) = '1' and R_IS_O(1) = '1')then
673  NEXT_TYPE_S <= '1';
674  rx_raw_ps2(63 downto 0) <= RxD(63 downto 40) & x"fb" & RxD(31 downto 8) & x"9c";
675  else
676  NEXT_TYPE_S <= '0';
677  end if;
678  if(R_IS_T = '1')then
679  case RxD(6 downto 4) is
680  when "000" =>
681  if(R_IS_C(7 downto 1) = not R_IS_E(7 downto 1))then
682  NEXT_TYPE_T <= '1';
683  else
684  NEXT_TYPE_T <= '0';
685  end if;
686  rx_raw_ps2(63 downto 0) <= c_raw(63 downto 8) & x"fd";
687  when "001" =>
688  if(R_IS_C(7 downto 2) = not R_IS_E(7 downto 2))then
689  NEXT_TYPE_T <= '1';
690  else
691  NEXT_TYPE_T <= '0';
692  end if;
693  rx_raw_ps2(63 downto 0) <= c_raw(63 downto 16) & x"fd" & RxD(15 downto 8);
694  when "010" =>
695  if(R_IS_C(7 downto 3) = not R_IS_E(7 downto 3))then
696  NEXT_TYPE_T <= '1';
697  else
698  NEXT_TYPE_T <= '0';
699  end if;
700  rx_raw_ps2(63 downto 0) <= c_raw(63 downto 24) & x"fd" & RxD(23 downto 8);
701  when "011" =>
702  if(R_IS_C(7 downto 4) = not R_IS_E(7 downto 4))then
703  NEXT_TYPE_T <= '1';
704  else
705  NEXT_TYPE_T <= '0';
706  end if;
707  rx_raw_ps2(63 downto 0) <= c_raw(63 downto 32) & x"fd" & RxD(31 downto 8);
708  when "100" =>
709  if(R_IS_C(7 downto 5) = not R_IS_E(7 downto 5))then
710  NEXT_TYPE_T <= '1';
711  else
712  NEXT_TYPE_T <= '0';
713  end if;
714  rx_raw_ps2(63 downto 0) <= c_raw(63 downto 40) & x"fd" & RxD(39 downto 8);
715  when "101" =>
716  if(R_IS_C(7 downto 6) = not R_IS_E(7 downto 6))then
717  NEXT_TYPE_T <= '1';
718  else
719  NEXT_TYPE_T <= '0';
720  end if;
721  rx_raw_ps2(63 downto 0) <= c_raw(63 downto 48) & x"fd" & RxD(47 downto 8);
722  when "110" =>
723  if(R_IS_C(7) = not R_IS_E(7))then
724  NEXT_TYPE_T <= '1';
725  else
726  NEXT_TYPE_T <= '0';
727  end if;
728  rx_raw_ps2(63 downto 0) <= c_raw(63 downto 56) & x"fd" & RxD(55 downto 8);
729  when others =>
730  NEXT_TYPE_T <= '1';
731  rx_raw_ps2(63 downto 0) <= x"fd" & RxD(63 downto 8);
732  end case;
733  else
734  NEXT_TYPE_T <= '0';
735  end if;
736  end if;
737  T4567 <= RxD(6);
738 -- pipeline stage 3
739  R_TYPE_C <= NEXT_TYPE_C;
740  R_TYPE_D <= NEXT_TYPE_D;
741  R_TYPE_S <= NEXT_TYPE_S;
742  R_TYPE_T <= NEXT_TYPE_T;
743  rx_raw_ps3 <= rx_raw_ps2(63 downto 32) & rx_raw_ps2(71 downto 68) & rx_raw_ps2(31 downto 0) & rx_raw_ps2(67 downto 64);
744  R_IS_IDLE(3 downto 2) <= R_IS_IDLE(1 downto 0);
745  R_IS_RF(3 downto 2) <= R_IS_RF(1 downto 0);
746  R_IS_LF(3 downto 2) <= R_IS_LF(1 downto 0);
747  end if;
748 -- pipeline stage 4
749  if(reset = '1' or BLOCK_LOCK = '0')then
750  R_state <= RX_INIT;
751  rx_raw <= LBLOCK_R;
752  R_IS_LF(5 downto 4) <= "11";
753  R_IS_RF(5 downto 4) <= "00";
754  R_IS_IDLE(5 downto 4) <= "00";
755  elsif(GTX_RXHEADERVLD_dl(0) = '1')then
756  case R_state is
757  when RX_INIT =>
758  rx_raw <= rx_raw_ps3;
759  R_IS_LF(5 downto 4) <= "11";
760  R_IS_RF(5 downto 4) <= "00";
761  R_IS_IDLE(5 downto 4) <= "00";
762  if(R_TYPE_C = '1')then
763  R_state <= RX_C;
764  elsif(R_TYPE_S = '1')then
765  R_state <= RX_D;
766  else
767  R_state <= RX_E;
768  rx_raw <= EBLOCK_R;
769  end if;
770  when RX_C =>
771  R_IS_LF(5 downto 4) <= R_IS_LF(3 downto 2);
772  R_IS_RF(5 downto 4) <= R_IS_RF(3 downto 2);
773  R_IS_IDLE(5 downto 4) <= R_IS_IDLE(3 downto 2);
774  rx_raw <= rx_raw_ps3;
775  if(R_TYPE_S = '1')then
776  R_state <= RX_D;
777  elsif(R_TYPE_C = '0')then
778  R_state <= RX_E;
779  rx_raw <= EBLOCK_R;
780  end if;
781  when RX_D =>
782  R_IS_LF(5 downto 4) <= R_IS_LF(3 downto 2);
783  R_IS_RF(5 downto 4) <= R_IS_RF(3 downto 2);
784  R_IS_IDLE(5 downto 4) <= R_IS_IDLE(3 downto 2);
785  rx_raw <= rx_raw_ps3;
786  if(R_TYPE_T = '1' and (NEXT_TYPE_C = '1' or NEXT_TYPE_S = '1'))then
787  R_state <= RX_T;
788  elsif(R_TYPE_D = '0')then
789  R_state <= RX_E;
790  rx_raw <= EBLOCK_R;
791  end if;
792  when RX_T =>
793  R_IS_LF(5 downto 4) <= R_IS_LF(3 downto 2);
794  R_IS_RF(5 downto 4) <= R_IS_RF(3 downto 2);
795  R_IS_IDLE(5 downto 4) <= R_IS_IDLE(3 downto 2);
796  rx_raw <= rx_raw_ps3;
797  if(R_TYPE_S = '1')then
798  R_state <= RX_D;
799  else
800  R_state <= RX_C;
801  end if;
802  when others =>
803  rx_raw <= rx_raw_ps3;
804  R_IS_LF(5 downto 4) <= "00";
805  R_IS_RF(5 downto 4) <= "00";
806  R_IS_IDLE(5 downto 4) <= "00";
807  if(R_TYPE_C = '1')then
808  R_state <= RX_C;
809  elsif(R_TYPE_D = '1')then
810  R_state <= RX_D;
811  elsif(R_TYPE_T = '1' and (NEXT_TYPE_C = '1' or NEXT_TYPE_S = '1'))then
812  R_state <= RX_T;
813  else
814  rx_raw <= EBLOCK_R;
815  end if;
816  end case;
817  end if;
818  end if;
819 end process;
820 process(RXUSRCLK,reset)
821 begin
822  if(reset = '1')then
823  reset_RXSyncRegs <= (others => '1');
824  en_II <= '1';
825  elsif(RXUSRCLK'event and RXUSRCLK = '1')then
826  reset_RXSyncRegs <= reset_RXSyncRegs(1 downto 0) & '0';
827  if(BLOCK_LOCK = '0')then
828  en_II <= '1';
829  elsif((GTX_RXHEADERVLD_dl(0) = '0' and and_reduce(rx_raw(3 downto 0)) = '0') or (GTX_RXHEADERVLD_dl(0) = '1' and and_reduce(rx_raw(39 downto 36)) = '0'))then
830  en_II <= '0';
831  elsif((GTX_RXHEADERVLD_dl(0) = '0' and or_reduce(rx_raw(3 downto 0)) = '1') or (GTX_RXHEADERVLD_dl(0) = '1' and or_reduce(rx_raw(39 downto 36)) = '1'))then
832  en_II <= '1';
833  end if;
834  end if;
835 end process;
836 process(RXUSRCLK)
837 begin
838  if(RXUSRCLK'event and RXUSRCLK = '1')then
839  GTX_RXDVLD_q <= GTX_RXDVLD;
840  RX_FIFO_WE <= GTX_RXHEADERVLD_dl(1) or GTX_RXHEADERVLD_dl(0);
841  if(GTX_RXHEADERVLD_dl(0) = '0')then
842  rx_raw_mux <= rx_raw(35 downto 0);
843  R_IS_LF(6) <= R_IS_LF(4);
844  R_IS_RF(6) <= R_IS_RF(4);
845  if(R_IS_IDLE(4) = '1' or (R_IS_RF(6) = '1' and R_IS_RF(4) = '1') or (R_IS_LF(6) = '1' and R_IS_LF(4) = '1'))then
846  en_DI <= '1';
847  else
848  en_DI <= '0';
849  end if;
850  else
851  rx_raw_mux <= rx_raw(71 downto 36);
852  R_IS_LF(6) <= R_IS_LF(5);
853  R_IS_RF(6) <= R_IS_RF(5);
854  if(R_IS_IDLE(5) = '1' or (R_IS_RF(6) = '1' and R_IS_RF(5) = '1') or (R_IS_LF(6) = '1' and R_IS_LF(5) = '1'))then
855  en_DI <= '1';
856  else
857  en_DI <= '0';
858  end if;
859  end if;
860  RX_FIFO_DI(36) <= en_II and insert_IDLE_l and not(RX_FIFO_DI(36) and RX_FIFO_WE);
861  RX_FIFO_DI(35 downto 0) <= rx_raw_mux;
862  skip_RX_FIFO_WE <= not (RX_FIFO_WE and skip_RX_FIFO_WE) and en_DI and delete_IDLE_l;
863  if(inh = '1' or (RX_FIFO_WE = '1' and skip_RX_FIFO_WE = '1'))then
864  delete_IDLE_l <= '0';
865  elsif(GTX_RXDVLD_q = '1' and GTX_RXDVLD = '0')then
866  delete_IDLE_l <= delete_IDLE;
867  end if;
868  if(inh = '1' or (RX_FIFO_WE = '1' and RX_FIFO_DI(36) = '1'))then
869  insert_IDLE_l <= '0';
870  elsif(GTX_RXDVLD_q = '1' and GTX_RXDVLD = '0')then
871  insert_IDLE_l <= insert_IDLE;
872  end if;
873  end if;
874 end process;
875 process(RXUSRCLK,reset)
876 begin
877  if(reset = '1')then
878  RX_FIFO_WA <= x"8";
879  RX_FIFO_RA_G0SyncRegs <= (others => '0');
880  RX_FIFO_RA_G1SyncRegs <= (others => '0');
881  RX_FIFO_RA_G2SyncRegs <= (others => '0');
882  RX_FIFO_RA_G3SyncRegs <= (others => '0');
883  RX_FIFO_RA_P <= (others => '0');
884  RX_FIFO_WA_RA_D <= (others => '0');
885  inh <= '0';
886  elsif(RXUSRCLK'event and RXUSRCLK = '1')then
887  if(RX_FIFO_WE = '1' and skip_RX_FIFO_WE = '0')then
888  RX_FIFO_WA <= RX_FIFO_WA + 1;
889  end if;
890  RX_FIFO_RA_G0SyncRegs <= RX_FIFO_RA_G0SyncRegs(1 downto 0) & RX_FIFO_RA_G(0);
891  RX_FIFO_RA_G1SyncRegs <= RX_FIFO_RA_G1SyncRegs(1 downto 0) & RX_FIFO_RA_G(1);
892  RX_FIFO_RA_G2SyncRegs <= RX_FIFO_RA_G2SyncRegs(1 downto 0) & RX_FIFO_RA_G(2);
893  RX_FIFO_RA_G3SyncRegs <= RX_FIFO_RA_G3SyncRegs(1 downto 0) & RX_FIFO_RA_G(3);
894  RX_FIFO_RA_P(3) <= RX_FIFO_RA_G3SyncRegs(2);
895  RX_FIFO_RA_P(2) <= RX_FIFO_RA_G3SyncRegs(2) xor RX_FIFO_RA_G2SyncRegs(2);
896  RX_FIFO_RA_P(1) <= RX_FIFO_RA_G3SyncRegs(2) xor RX_FIFO_RA_G2SyncRegs(2) xor RX_FIFO_RA_G1SyncRegs(2);
897  RX_FIFO_RA_P(0) <= RX_FIFO_RA_G3SyncRegs(2) xor RX_FIFO_RA_G2SyncRegs(2) xor RX_FIFO_RA_G1SyncRegs(2) xor RX_FIFO_RA_G0SyncRegs(2);
898  RX_FIFO_WA_RA_D <= RX_FIFO_WA - RX_FIFO_RA_P;
899  if(RX_FIFO_WE = '1' and (skip_RX_FIFO_WE = '1' or RX_FIFO_DI(36) = '1'))then
900  inh <= '1';
901  elsif(inh_cntr(3) = '1')then
902  inh <= '0';
903  end if;
904  if(inh = '0')then
905  inh_cntr <= (others => '0');
906  elsif(GTX_RXHEADERVLD_dl(0) = '1')then
907  inh_cntr <= inh_cntr + 1;
908  end if;
909  end if;
910 end process;
911 i_delete_IDLE : ROM32X1
912  generic map (
913  INIT => X"0000c01f")
914  port map (
915  O => delete_IDLE, -- ROM output
916  A0 => RX_FIFO_WA_RA_D(0), -- ROM address[0]
917  A1 => RX_FIFO_WA_RA_D(1), -- ROM address[1]
918  A2 => RX_FIFO_WA_RA_D(2), -- ROM address[2]
919  A3 => RX_FIFO_WA_RA_D(3), -- ROM address[3]
920  A4 => '0' -- ROM address[4]
921  );
922 i_insert_IDLE : ROM32X1
923  generic map (
924  INIT => X"00000fe0")
925  port map (
926  O => insert_IDLE, -- ROM output
927  A0 => RX_FIFO_WA_RA_D(0), -- ROM address[0]
928  A1 => RX_FIFO_WA_RA_D(1), -- ROM address[1]
929  A2 => RX_FIFO_WA_RA_D(2), -- ROM address[2]
930  A3 => RX_FIFO_WA_RA_D(3), -- ROM address[3]
931  A4 => '0' -- ROM address[4]
932  );
933 g_RX_FIFO: for i in 0 to 36 generate
934  i_RX_FIFO : RAM32X1D
935  generic map (
936  INIT => RxIdle(i)) -- Initial contents of RAM
937  port map (
938  DPO => RX_FIFO_DO(i), -- Read-only 1-bit data output
939  SPO => open, -- R/W 1-bit data output
940  A0 => RX_FIFO_WA(0), -- R/W address[0] input bit
941  A1 => RX_FIFO_WA(1), -- R/W address[1] input bit
942  A2 => RX_FIFO_WA(2), -- R/W address[2] input bit
943  A3 => RX_FIFO_WA(3), -- R/W address[3] input bit
944  A4 => '0', -- R/W address[4] input bit
945  D => RX_FIFO_DI(i), -- Write 1-bit data input
946  DPRA0 => RX_FIFO_RA(0), -- Read-only address[0] input bit
947  DPRA1 => RX_FIFO_RA(1), -- Read-only address[1] input bit
948  DPRA2 => RX_FIFO_RA(2), -- Read-only address[2] input bit
949  DPRA3 => RX_FIFO_RA(3), -- Read-only address[3] input bit
950  DPRA4 => ec_RX_FIFO_RAn , -- Read-only address[4] input bit
951  WCLK => RXUSRCLK, -- Write clock input
952  WE => RX_FIFO_WE -- Write enable input
953  );
954 end generate;
955 -- add or remove idle(Ordered set) will be decided at the RX_FIFO write side
956 process(clk2x)
957 begin
958  if(clk2x'event and clk2x = '1')then
959  ec_RX_FIFO_RAn <= RX_FIFO_DO(36);
960  if(reset = '1')then
961  RX_FIFO_RA <= (others => '0');
962  RX_FIFO_RA_G <= (others => '0');
963  else
964  if(ec_RX_FIFO_RAn = '0')then
965  RX_FIFO_RA <= RX_FIFO_RA +1;
966  end if;
967  RX_FIFO_RA_G(3) <= RX_FIFO_RA(3);
968  RX_FIFO_RA_G(2) <= RX_FIFO_RA(3) xor RX_FIFO_RA(2);
969  RX_FIFO_RA_G(1) <= RX_FIFO_RA(2) xor RX_FIFO_RA(1);
970  RX_FIFO_RA_G(0) <= RX_FIFO_RA(1) xor RX_FIFO_RA(0);
971  end if;
972  PhyEmacRxC <= RX_FIFO_DO(3 downto 0);
973  PhyEmacRxD <= RX_FIFO_DO(35 downto 4);
974  end if;
975 end process;
976 end Behavioral;
977