Behavioral Architecture Reference

List of all members.

Processes
PROCESS_848	( DCLK )
PROCESS_849	( DCLK )
PROCESS_850	( DCLK )
PROCESS_851	( DCLK )
PROCESS_852	( DCLK )
PROCESS_853	( DCLK ,RST )
PROCESS_854	( DCLK ,write_state )
PROCESS_855	( DCLK )
PROCESS_856	( curr_state_reg ,in_progress_b ,done_drp ,downshift_1x ,downshift_4x ,agc_reg ,ctle3_reg ,agc_railing_int )
PROCESS_857	( curr_state_reg ,do_reg ,agc_bw ,ctle3_ld )
PROCESS_858	( DCLK )

Constants
DLY	time := 1 ns
CTLE3_ADDR	std_logic_vector ( 8 downto 0 ) := " 010000011 "
CTLE3_UPPER_LIMIT	integer := 7
CTLE3_LOWER_LIMIT	integer := 0
AGC_UPPER_LIMIT	integer := 30
AGC_LOWER_LIMIT	integer := 1
AGC_BW_ADDR	std_logic_vector ( 8 downto 0 ) := " 000011101 "
AGC_BW_1X	std_logic_vector ( 3 downto 0 ) := " 0000 "
AGC_BW_4X	std_logic_vector ( 3 downto 0 ) := " 0010 "
AGC_BW_8X	std_logic_vector ( 3 downto 0 ) := " 0011 "
UPDATE_TIMER_LIMIT	integer range 0 to 16380 := AGC_TIMER * 4
UPDATE_TIMER_LIMIT_4X	integer range 0 to 32760 := UPDATE_TIMER_LIMIT * 2
IDLE	std_logic_vector ( 3 downto 0 ) := " 0000 "
READ	std_logic_vector ( 3 downto 0 ) := " 0001 "
WAIT_READ	std_logic_vector ( 3 downto 0 ) := " 0010 "
DECIDE	std_logic_vector ( 3 downto 0 ) := " 0011 "
INC_S	std_logic_vector ( 3 downto 0 ) := " 0100 "
DEC_S	std_logic_vector ( 3 downto 0 ) := " 0101 "
WRITE	std_logic_vector ( 3 downto 0 ) := " 0110 "
WAIT_UPDATE	std_logic_vector ( 3 downto 0 ) := " 0111 "
DONE_ST	std_logic_vector ( 3 downto 0 ) := " 1000 "
READ_AGC_BW	std_logic_vector ( 3 downto 0 ) := " 1001 "
WAIT_READ_AGC_BW	std_logic_vector ( 3 downto 0 ) := " 1010 "
MODIFY_AGC_BW	std_logic_vector ( 3 downto 0 ) := " 1011 "
WRITE_AGC_BW	std_logic_vector ( 3 downto 0 ) := " 1100 "
WAIT_WRITE_AGC_BW	std_logic_vector ( 3 downto 0 ) := " 1101 "
DOWNSHIFT_4X_S	std_logic_vector ( 3 downto 0 ) := " 1110 "
WAIT_AGC_4X	std_logic_vector ( 3 downto 0 ) := " 1111 "

Signals
in_progress	std_logic
in_progress_b	std_logic
agc_reg	std_logic_vector ( 4 downto 0 )
agc_reg0	std_logic_vector ( 4 downto 0 )
agc_bw	std_logic_vector ( 3 downto 0 )
ctle3_reg	std_logic_vector ( 3 downto 0 )
ctle3_ld	std_logic_vector ( 3 downto 0 )
next_state	std_logic_vector ( 3 downto 0 )
rxmon_sel	std_logic_vector ( 1 downto 0 )
update_timer	std_logic_vector ( 14 downto 0 )
clk_div_counter	std_logic_vector ( 5 downto 0 )
den_int	std_logic
den_int2	std_logic
dwe_int	std_logic
do_reg	std_logic_vector ( 15 downto 0 )
done_drp	std_logic
di_int	std_logic_vector ( 15 downto 0 )
daddr_int	std_logic_vector ( 8 downto 0 )
inc	std_logic
dec	std_logic
incdec	std_logic_vector ( 1 downto 0 )
curr_state_reg	std_logic_vector ( 3 downto 0 )
clk_int_en	std_logic
clk_timer_en	std_logic
write_state	std_logic
done_state	std_logic
downshift_4x_state	std_logic
read_state	std_logic
wait_agc_4x_state	std_logic
min_agc	std_logic
max_agc	std_logic
agc_not_railed	std_logic
agc_not_railed_l	std_logic
rxmon_ok_l	std_logic
rxmon_ok_l_b	std_logic
downshift_4x	std_logic
downshift_1x	std_logic
DEN_reg	std_logic
DONE_INT	std_logic
agc_railing_int	std_logic
agc_interm	std_logic_vector ( 3 downto 0 )

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Detailed Description

Definition at line 110 of file s6link_ctle_agc_comp.vhd.

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The documentation for this class was generated from the following files:

• src/common/IPBUS/S6Link/s6link_ctle_agc_comp.vhd