Behavioral Architecture Reference

List of all members.

Processes
PROCESS_838	( CLK )
PROCESS_839	( CLK )
PROCESS_840	( CLK )
PROCESS_841	( curr_state )
PROCESS_842	( curr_state ,drdy_s ,counter ,rst_int ,dfe_rst_b_s )

Constants
DLY	time := 1 ns
DFE_RSTB_ADDR	std_logic_vector ( 8 downto 0 ) := " 100000001 "
DFE_RSTB_BIT	integer := 14
IDLE	std_logic_vector ( 3 downto 0 ) := " 0001 "
NOT_IN_RST	std_logic_vector ( 3 downto 0 ) := " 0011 "
READ1	std_logic_vector ( 3 downto 0 ) := " 0010 "
WAIT1	std_logic_vector ( 3 downto 0 ) := " 0110 "
DONE	std_logic_vector ( 3 downto 0 ) := " 0100 "

Signals
curr_state	std_logic_vector ( 3 downto 0 ) := IDLE
next_state	std_logic_vector ( 3 downto 0 ) := IDLE
rst_s	std_logic_vector ( 1 downto 0 )
dfe_rst_b_s	std_logic
drdy_s	std_logic
counter	std_logic_vector ( 3 downto 0 )
rst_int_b	std_logic
rst_int	std_logic
done_state	std_logic
enable	std_logic
enable_b	std_logic
den_pre	std_logic
daddr_pre	std_logic_vector ( 8 downto 0 )
ready_pre	std_logic
rst_b_latch_b	std_logic

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Detailed Description

Definition at line 98 of file s6link_adapt_starter.vhd.

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The documentation for this class was generated from the following files:

• src/common/IPBUS/S6Link/s6link_adapt_starter.vhd