AMC13
Firmwares for the different applications of the AMC13 uTCA board made at Boston University
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s6link_adapt_starter.vhd
1 --////////////////////////////////////////////////////////////////////////////////
2 --// ____ ____
3 --// / /\/ /
4 --// /___/ \ / Vendor: Xilinx
5 --// \ \ \/ Version : 2.5
6 --// \ \ Application : 7 Series FPGAs Transceivers Wizard
7 --// / / Filename :s6link_adapt_starter.vhd
8 --// /___/ /\
9 --// \ \ / \
10 --// \___\/\___\
11 --//
12 --//
13 -- Description : This module performs TX reset and initialization.
14 --
15 --
16 --
17 -- Module S6Link_adapt_starter
18 -- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
19 --
20 --
21 -- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
22 --
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27 --
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66 
67 
68 --*****************************************************************************
69 
70 library IEEE;
71 use IEEE.STD_LOGIC_1164.ALL;
72 use IEEE.STD_LOGIC_UNSIGNED.ALL;
73 use IEEE.STD_LOGIC_ARITH.ALL;
74 use IEEE.NUMERIC_STD.ALL;
75 
76 library unisim;
77 use unisim.vcomponents.all;
78 
80 generic(
81  WAIT_CYC :integer range 0 to 16 := 10
82 );
83 port (
84 RST : in STD_LOGIC;
85 CLK : in STD_LOGIC;
86 DO : in STD_LOGIC_VECTOR(15 downto 0);
87 DRDY : in STD_LOGIC;
88 DADDR : out STD_LOGIC_VECTOR(8 downto 0);
89 DEN : out STD_LOGIC;
90 DWE : out STD_LOGIC;
91 READY : out STD_LOGIC;
92 curr_state_debug : out STD_LOGIC_VECTOR(3 downto 0);
93 counter_debug : out STD_LOGIC_VECTOR(2 downto 0);
94 rst_int_debug : out STD_LOGIC
95 );
96 end S6Link_adapt_starter;
97 
98 architecture Behavioral of S6Link_adapt_starter is
99 
100 constant DLY : time := 1 ns;
101 constant DFE_RSTB_ADDR : std_logic_vector(8 downto 0) := "100000001"; --GTX
102 constant DFE_RSTB_BIT : integer := 14; --GTX
103 
104 constant IDLE : std_logic_vector(3 downto 0) := "0001";
105 constant NOT_IN_RST : std_logic_vector(3 downto 0) := "0011";
106 constant READ1 : std_logic_vector(3 downto 0) := "0010";
107 constant WAIT1 : std_logic_vector(3 downto 0) := "0110";
108 constant DONE : std_logic_vector(3 downto 0) := "0100";
109 
110 signal curr_state : std_logic_vector(3 downto 0) := IDLE;
111 signal next_state : std_logic_vector(3 downto 0) := IDLE;
112 signal rst_s : std_logic_vector(1 downto 0);
113 signal dfe_rst_b_s : std_logic;
114 signal drdy_s : std_logic;
115 signal counter : std_logic_vector(3 downto 0);
116 signal rst_int_b : std_logic;
117 
118 signal rst_int : std_logic;
119 signal done_state : std_logic;
120 signal enable : std_logic;
121 signal enable_b : std_logic;
122 
123 signal den_pre : std_logic;
124 signal daddr_pre : std_logic_vector(8 downto 0);
125 signal ready_pre : std_logic;
126 signal rst_b_latch_b : std_logic;
127 
128 begin
129 
130 rst_b_latch_b <= (rst_s(1) and enable);
131 rst_int_debug <= rst_int;
132 curr_state_debug <= curr_state;
133 counter_debug <= counter(2 downto 0);
134 
135 enable <= not(enable_b);
136 DEN <= den_pre;
137 DADDR <= daddr_pre;
138 done_state <= '1' when (curr_state = DONE) else '0';
139 
140 DWE <= '0';
141 rst_int <= not(rst_int_b);
142 
143 
144 process(CLK)
145 begin
146  if rising_edge(CLK) then
147  if(rst_int='1') then
148  ready_pre <= '0' after DLY;
149  READY <= '0'after DLY;
150  else
151  ready_pre <= done_state after DLY;
152  READY <= ready_pre after DLY;
153  end if;
154  end if;
155 end process;
156 
157 
158 --Logic runs when RST is 0. It runs until hits DONE state and stays there.
159 --When user resets RXRESET, etc, state machine starts again from beginning.
160 --Thus there's an issue for first RST. We don't want logic to start until RST goes high then low.
161 --To circumvent, add another SR latch to detect first RST pulse. This latch's output remains HIGH after first RST pulse.
162 --Before first RST, the latch output is low and gates the set of the 2nd latch
163 
164 
165 --SR latch to guarantee width of reset. CLR dominant.
166 --rst asserted immediately by RST. Deasserted 2 CLK cycles later if RST width is less than DCLK cycle. Deasserted when RST goes low when RST width greater than DCLK cycle.
167 
168 --Logic not enabled until first pulse of RST detected
169 first_pulse_sr_ff : FDCE
170 generic map ( INIT => '1'
171 )
172 port map (
173  Q => enable_b,
174  C => CLK,
175  CE => '0',
176  CLR => RST,
177  D => '1'
178  );
179 
180 rst_b_sr_ff : FDCE
181 generic map ( INIT => '0'
182 )
183 port map (
184  Q => rst_int_b,
185  C => CLK,
186  D => '1',
187  CE => rst_b_latch_b, --(rst_s(1) and enable),
188  CLR => RST
189  );
190 
191 process(CLK)
192 begin
193  if rising_edge(CLK) then
194  rst_s(0) <= not(rst_int_b) after DLY;
195  rst_s(1) <= rst_s(0) after DLY;
196 
197  drdy_s <= DRDY after DLY;
198 
199  dfe_rst_b_s <= DO(DFE_RSTB_BIT) after DLY;
200 
201  curr_state <= next_state after DLY;
202  end if;
203 end process;
204 
205 process(CLK)
206 begin
207  if rising_edge(CLK) then
208  case curr_state is
209  when IDLE =>
210  counter <= (others =>'0') after DLY;
211 
212  when NOT_IN_RST =>
213  counter <= counter + 1 after DLY;
214 
215  when others =>
216  counter <= counter after DLY;
217  end case;
218  end if;
219 end process;
220 
221 --Counter
222 process(curr_state)
223 begin
224  case curr_state is
225  when IDLE =>
226  den_pre <= '0' after DLY;
227  daddr_pre <= (others =>'0') after DLY;
228 
229  when READ1 =>
230  den_pre <= '1' after DLY;
231  daddr_pre <= DFE_RSTB_ADDR;
232 
233  when WAIT1 =>
234  den_pre <= '0' after DLY;
235  daddr_pre <= DFE_RSTB_ADDR;
236 
237  when NOT_IN_RST =>
238  den_pre <= '0' after DLY;
239  daddr_pre <= DFE_RSTB_ADDR;
240 
241  when DONE =>
242  den_pre <= '0' after DLY;
243  daddr_pre <= (others => '0');
244 
245  when others =>
246  den_pre <= '0' after DLY;
247  daddr_pre <= (others => '0');
248 
249  end case;
250 
251 end process;
252 
253 --State Machine
254 process(curr_state,drdy_s,counter,rst_int,dfe_rst_b_s)
255 begin
256  if(rst_int = '1') then
257  next_state <= IDLE after DLY;
258  else
259  case curr_state is
260  when IDLE =>
261  next_state <= READ1 after DLY;
262 
263  when READ1 =>
264  next_state <= WAIT1 after DLY;
265 
266  when WAIT1 =>
267  if(drdy_s = '1') then
268  if(dfe_rst_b_s = '1') then --Out of DFE reset
269  next_state <= NOT_IN_RST after DLY;
270  else
271  next_state <= IDLE after DLY; --Reset counter if see 0 in midst of 1's. Keep reading until see in reset state
272  end if;
273  else
274  next_state <= WAIT1 after DLY;
275  end if;
276 
277  when NOT_IN_RST => --Wait for WAIT_CYC+1 reads non-reset since counter delayed by 1 cyc
278  if(counter = WAIT_CYC) then
279  next_state <= DONE after DLY;
280  else
281  next_state <= READ1 after DLY;
282  end if;
283 
284  when DONE =>
285  next_state <= DONE after DLY;
286 
287  when others =>
288  next_state <= IDLE after DLY;
289 
290  end case;
291  end if;
292 end process;
293 
294 end Behavioral;
295 
296 --For sim: LDCE as SR latch
297 ----module LDCE #(
298 ---- parameter INIT = 1'b0
299 ----)
300 ----(
301 ---- output reg Q,
302 ---- input CLR,
303 ---- input D,
304 ---- input G,
305 ---- input GE
306 ----);
307 ----
308 ---- initial
309 ---- begin
310 ---- Q <= `DLY INIT;
311 ---- end
312 ----
313 ---- always @ (CLR or G)
314 ---- begin
315 ---- if(CLR)
316 ---- Q <= `DLY 1'b0;
317 ---- else if(G)
318 ---- Q <= `DLY 1'b1;
319 ---- end
320 ----
321 ----endmodule
322