1 --////////////////////////////////////////////////////////////////////////////////
4 --// /___/ \ / Vendor: Xilinx
5 --// \ \ \/ Version : 2.
5
6 --// \ \ Application : 7 Series FPGAs Transceivers Wizard
7 --// / / Filename :s6link_adapt_starter.vhd
13 -- Description : This module performs TX reset and initialization.
17 -- Module S6Link_adapt_starter
18 -- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
21 -- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
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68 --*****************************************************************************
71 use IEEE.STD_LOGIC_1164.
ALL;
72 use IEEE.STD_LOGIC_UNSIGNED.
ALL;
73 use IEEE.STD_LOGIC_ARITH.
ALL;
74 use IEEE.NUMERIC_STD.
ALL;
77 use unisim.vcomponents.
all;
81 WAIT_CYC : range 0 to 16 := 10
86 DO : in (15 downto 0);
88 DADDR : out (8 downto 0);
92 curr_state_debug : out (3 downto 0);
93 counter_debug : out (2 downto 0);
96 end S6Link_adapt_starter;
100 constant DLY : := 1 ns;
101 constant DFE_RSTB_ADDR : (8 downto 0) := "100000001";
--GTX
102 constant DFE_RSTB_BIT : := 14;
--GTX
104 constant IDLE : (3 downto 0) := "0001";
105 constant NOT_IN_RST : (3 downto 0) := "0011";
106 constant READ1 : (3 downto 0) := "0010";
107 constant WAIT1 : (3 downto 0) := "0110";
108 constant DONE : (3 downto 0) := "0100";
110 signal curr_state : (3 downto 0) := IDLE;
111 signal next_state : (3 downto 0) := IDLE;
112 signal rst_s : (1 downto 0);
113 signal dfe_rst_b_s : ;
115 signal counter : (3 downto 0);
119 signal done_state : ;
124 signal daddr_pre : (8 downto 0);
126 signal rst_b_latch_b : ;
130 rst_b_latch_b <= (rst_s(1) and enable);
131 rst_int_debug <= rst_int;
132 curr_state_debug <= curr_state;
133 counter_debug <= counter(2 downto 0);
135 enable <=
not(enable_b);
138 done_state <= '1' when (curr_state = DONE) else '0';
141 rst_int <= not(rst_int_b);
146 if rising_edge(CLK) then
148 ready_pre <= '0' after DLY;
149 READY <= '0'after DLY;
151 ready_pre <= done_state after DLY;
152 READY <= ready_pre after DLY;
158 --Logic runs when RST is 0. It runs
until hits DONE state
and stays there.
159 --When user resets RXRESET, etc, state machine starts again from beginning.
160 --Thus there's an issue for first RST. We don't want logic to start until RST goes high then low.
161 --To circumvent, add another SR latch to detect first RST pulse. This latch's output remains HIGH after first RST pulse.
162 --Before first RST, the latch output is low and gates the set of the 2nd latch
165 --SR latch to guarantee width of reset. CLR dominant.
166 --rst asserted immediately by RST. Deasserted 2 CLK cycles later
if RST width
is less than DCLK cycle. Deasserted
when RST goes low
when RST width greater than DCLK cycle.
168 --Logic not enabled until first pulse of RST detected
169 first_pulse_sr_ff : FDCE
170 generic map ( INIT => '1'
181 generic map ( INIT => '0'
187 CE => rst_b_latch_b,
--(rst_s(1)
and enable),
193 if rising_edge(CLK) then
194 rst_s(0) <= not(rst_int_b) after DLY;
195 rst_s(1) <= rst_s(0) after DLY;
197 drdy_s <= DRDY after DLY;
199 dfe_rst_b_s <= DO(DFE_RSTB_BIT) after DLY;
201 curr_state <= next_state after DLY;
207 if rising_edge(CLK) then
210 counter <= (others =>'0') after DLY;
213 counter <= counter + 1 after DLY;
216 counter <= counter after DLY;
226 den_pre <= '0' after DLY;
227 daddr_pre <= (others =>'0') after DLY;
230 den_pre <= '1' after DLY;
231 daddr_pre <= DFE_RSTB_ADDR;
234 den_pre <= '0' after DLY;
235 daddr_pre <= DFE_RSTB_ADDR;
238 den_pre <= '0' after DLY;
239 daddr_pre <= DFE_RSTB_ADDR;
242 den_pre <= '0' after DLY;
243 daddr_pre <= (others => '0');
246 den_pre <= '0' after DLY;
247 daddr_pre <= (others => '0');
254 process(curr_state,drdy_s,counter,rst_int,dfe_rst_b_s)
256 if(rst_int = '1') then
257 next_state <= IDLE after DLY;
261 next_state <= READ1 after DLY;
264 next_state <= WAIT1 after DLY;
267 if(drdy_s = '1') then
268 if(dfe_rst_b_s = '1') then --Out of DFE reset
269 next_state <= NOT_IN_RST after DLY;
271 next_state <= IDLE after DLY;
--Reset counter if see 0 in midst
of 1's. Keep reading
until see
in reset state
274 next_state <= WAIT1 after DLY;
277 when NOT_IN_RST => --Wait for WAIT_CYC+1 reads non-reset since counter delayed by 1 cyc
278 if(counter = WAIT_CYC) then
279 next_state <= DONE after DLY;
281 next_state <= READ1 after DLY;
285 next_state <= DONE after DLY;
288 next_state <= IDLE after DLY;
296 --For sim: LDCE as SR latch
298 ---- parameter INIT = 1'b0
313 ---- always @ (CLR or G)