Behavioral Architecture Reference

List of all members.

Processes
PROCESS_944	( TTC_clk )
PROCESS_945	( TTC_Clk )
PROCESS_946	( ipb_clk )
PROCESS_947	( ipb_addr ,mask ,threshold )
PROCESS_948	( DRPclk )

Components
RAM32x6Db	<Entity RAM32x6Db>
uHTR_trigPD_init	<Entity uHTR_trigPD_init>

Signals
version	std_logic_vector ( 2 downto 0 ) := " 001 "
MaskedTrigdata	array24x32 := ( others = > ( others = > ' 0 ' ) )
mask	array24x32 := ( others = > ( others = > ' 0 ' ) )
threshold	array8x4 := ( others = > ( others = > ' 0 ' ) )
NonZeroByteCnt	array16x4 := ( others = > ( others = > ' 0 ' ) )
NonZeroByte	std_logic_vector ( 95 downto 0 ) := ( others = > ' 0 ' )
TrigDataOut	std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
RXDATA	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
TXDATA	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
Sample	std_logic := ' 0 '
SampleSyncRegs	std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
RXBUF_we	std_logic := ' 0 '
RXBUF_wa	std_logic_vector ( 4 downto 0 ) := ( others = > ' 0 ' )
RXBUF_di	std_logic_vector ( 29 downto 0 ) := ( others = > ' 0 ' )
RXBUF	std_logic_vector ( 29 downto 0 ) := ( others = > ' 0 ' )
PRBSSEL	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
PRBSERR_cnt	std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
RXCHARISK	std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
txfsmresetdone	std_logic := ' 0 '
DATA_VALID	std_logic := ' 0 '
CPLLLOCK	std_logic := ' 0 '
CPLLRESET	std_logic := ' 0 '
REFCLK	std_logic := ' 0 '
PRBSERR	std_logic := ' 0 '
GTRXRESET	std_logic := ' 0 '
RXRESETDONE	std_logic := ' 0 '
GTTXRESET	std_logic := ' 0 '
bcnt	std_logic_vector ( 11 downto 0 ) := ( others = > ' 0 ' )
trigmask	std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
reset_trig_dl_wa	std_logic := ' 0 '
BC0_dl_i	std_logic := ' 0 '
chk_lock	std_logic := ' 0 '
chk_lock_q	std_logic := ' 0 '
trig_dl_ra	std_logic_vector ( 11 downto 0 ) := ( others = > ' 0 ' )
trig_dl_wa	std_logic_vector ( 11 downto 0 ) := ( others = > ' 0 ' )
trig_dl_DI	std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
trig_dl_DO	std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
en_HCAL_trig	std_logic := ' 0 '
ec_BX_offset	std_logic := ' 0 '
BC0_locked	std_logic_vector ( 1 downto 0 ) := ( others = > ' 0 ' )
BX_offset_a	std_logic_vector ( 11 downto 0 ) := ( others = > ' 0 ' )
BX_offset_b	std_logic_vector ( 11 downto 0 ) := ( others = > ' 0 ' )
BX_offset_sum	std_logic_vector ( 12 downto 0 ) := ( others = > ' 0 ' )
LockLossCntr	std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
BX_offset	std_logic_vector ( 11 downto 0 ) := ( others = > ' 0 ' )
en_BC0_gated	std_logic := ' 0 '
got_BC0	std_logic := ' 0 '
catchBC0	std_logic := ' 0 '
BC0_gated	std_logic := ' 0 '
BC0_gated_dl	std_logic := ' 0 '
GT0_RXPD_IN	std_logic_vector ( 1 downto 0 ) := ( others = > ' 0 ' )
GT0_TXPD_IN	std_logic_vector ( 1 downto 0 ) := ( others = > ' 0 ' )
SFP_ABS_q	std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
reset_cntr	std_logic_vector ( 20 downto 0 ) := ( others = > ' 0 ' )
soft_reset	std_logic := ' 0 '
reset_cntr20_q	std_logic := ' 0 '

Instantiations
i_ipbus_rbuf	RAM32x6Db <Entity RAM32x6Db>
uHTR_trig_init_i	uHTR_trigPD_init <Entity uHTR_trigPD_init>

---

Detailed Description

Definition at line 72 of file HCAL_trig.vhd.

---

The documentation for this class was generated from the following files:

• src/HCAL_trig/HCAL_trig.vhd