AMC13
Firmwares for the different applications of the AMC13 uTCA board made at Boston University
 All Classes Variables
HCAL_trig.vhd
1 ----------------------------------------------------------------------------------
2 -- Company:
3 -- Engineer:
4 --
5 -- Create Date: 11:06:56 07/09/2014
6 -- Design Name:
7 -- Module Name: HCAL_trig - Behavioral
8 -- Project Name:
9 -- Target Devices:
10 -- Tool versions:
11 -- Description:
12 --
13 -- Dependencies:
14 --
15 -- Revision:
16 -- Revision 0.01 - File Created
17 -- Additional Comments:
18 -- Byte
19 -- 0 Comma character (0xBC k-char)
20 -- 1 BX0 [7] VER[6:4]=1 BX ID [11:8]
21 -- 2 Bx ID [7:0]
22 -- 3 local trigger word
23 --
24 ----------------------------------------------------------------------------------
25 library IEEE;
26 use IEEE.STD_LOGIC_1164.ALL;
27 use IEEE.STD_LOGIC_ARITH.ALL;
28 use IEEE.STD_LOGIC_UNSIGNED.ALL;
29 use IEEE.std_logic_misc.all;
30 use work.amc13_pack.all;
31 
32 -- Uncomment the following library declaration if using
33 -- arithmetic functions with Signed or Unsigned values
34 --use IEEE.NUMERIC_STD.ALL;
35 
36 -- Uncomment the following library declaration if instantiating
37 -- any Xilinx primitives in this code.
38 library UNISIM;
39 use UNISIM.VComponents.all;
40 Library UNIMACRO;
41 use UNIMACRO.vcomponents.all;
42 
43 entity HCAL_trig is
44  Port ( TTC_clk : in STD_LOGIC;
45  DRPCLK : in STD_LOGIC;
46  reset : in STD_LOGIC;
47 -- en_HCAL_trig : in STD_LOGIC;
48  SFP_ABS : in STD_LOGIC;
49  BC0 : in STD_LOGIC;
50  BC0_dl : out STD_LOGIC;
51  triggerOut : out STD_LOGIC;
52  Trigdata : in array12x8;
53  TTC_lock : in STD_LOGIC;
54  AMC_en : in STD_LOGIC_VECTOR(11 downto 0);
55  BC0_lock : in STD_LOGIC_VECTOR(11 downto 0);
56  BX_offset2SC : out STD_LOGIC_VECTOR(11 downto 0);
57  -- ipbus signals
58  ipb_clk : in STD_LOGIC;
59  ipb_write : in STD_LOGIC;
60  ipb_strobe : in STD_LOGIC;
61  ipb_addr : in STD_LOGIC_VECTOR(31 downto 0);
62  ipb_wdata : in STD_LOGIC_VECTOR(31 downto 0);
63  ipb_rdata : out STD_LOGIC_VECTOR(31 downto 0);
64  GTX_REFCLKp : in STD_LOGIC;
65  GTX_REFCLKn : in STD_LOGIC;
66  GTX_RXp : in STD_LOGIC;
67  GTX_RXn : in STD_LOGIC;
68  GTX_TXp : out STD_LOGIC;
69  GTX_TXn : out STD_LOGIC);
70 end HCAL_trig;
71 
72 architecture Behavioral of HCAL_trig is
73 COMPONENT RAM32x6Db
74  PORT(
75  wclk : IN std_logic;
76  di : IN std_logic_vector(5 downto 0);
77  we : IN std_logic;
78  wa : IN std_logic_vector(4 downto 0);
79  ra : IN std_logic_vector(4 downto 0);
80  do : OUT std_logic_vector(5 downto 0)
81  );
82 END COMPONENT;
83 component uHTR_trigPD_init
84 generic
85 (
86  -- Simulation attributes
87  EXAMPLE_SIM_GTRESET_SPEEDUP : string := "FALSE"; -- Set to 1 to speed up sim reset
88  EXAMPLE_SIMULATION : integer := 0; -- Set to 1 for simulation
89  STABLE_CLOCK_PERIOD : integer := 20; --Period of the stable clock driving this state-machine, unit is [ns]
90  EXAMPLE_USE_CHIPSCOPE : integer := 0 -- Set to 1 to use Chipscope to drive resets
91 
92 );
93 port
94 (
95  SYSCLK_IN : in std_logic;
96  SOFT_RESET_IN : in std_logic;
97  DONT_RESET_ON_DATA_ERROR_IN : in std_logic;
98  GT0_TX_FSM_RESET_DONE_OUT : out std_logic;
99  GT0_RX_FSM_RESET_DONE_OUT : out std_logic;
100  GT0_DATA_VALID_IN : in std_logic;
101 
102  --_________________________________________________________________________
103  --GT0 (X1Y12)
104  --____________________________CHANNEL PORTS________________________________
105  --------------------------------- CPLL Ports -------------------------------
106  GT0_CPLLFBCLKLOST_OUT : out std_logic;
107  GT0_CPLLLOCK_OUT : out std_logic;
108  GT0_CPLLLOCKDETCLK_IN : in std_logic;
109  GT0_CPLLRESET_IN : in std_logic;
110  -------------------------- Channel - Clocking Ports ------------------------
111  GT0_GTREFCLK0_IN : in std_logic;
112  ---------------------------- Channel - DRP Ports --------------------------
113  GT0_DRPADDR_IN : in std_logic_vector(8 downto 0);
114  GT0_DRPCLK_IN : in std_logic;
115  GT0_DRPDI_IN : in std_logic_vector(15 downto 0);
116  GT0_DRPDO_OUT : out std_logic_vector(15 downto 0);
117  GT0_DRPEN_IN : in std_logic;
118  GT0_DRPRDY_OUT : out std_logic;
119  GT0_DRPWE_IN : in std_logic;
120  ------------------------------ Power-Down Ports ----------------------------
121  GT0_RXPD_IN : in std_logic_vector(1 downto 0);
122  GT0_TXPD_IN : in std_logic_vector(1 downto 0);
123  --------------------- RX Initialization and Reset Ports --------------------
124  GT0_RXUSERRDY_IN : in std_logic;
125  -------------------------- RX Margin Analysis Ports ------------------------
126  GT0_EYESCANDATAERROR_OUT : out std_logic;
127  ------------------------- Receive Ports - CDR Ports ------------------------
128  GT0_RXCDRLOCK_OUT : out std_logic;
129  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
130  GT0_RXUSRCLK_IN : in std_logic;
131  GT0_RXUSRCLK2_IN : in std_logic;
132  ------------------ Receive Ports - FPGA RX interface Ports -----------------
133  GT0_RXDATA_OUT : out std_logic_vector(31 downto 0);
134  ------------------- Receive Ports - Pattern Checker Ports ------------------
135  GT0_RXPRBSERR_OUT : out std_logic;
136  GT0_RXPRBSSEL_IN : in std_logic_vector(2 downto 0);
137  ------------------- Receive Ports - Pattern Checker ports ------------------
138  GT0_RXPRBSCNTRESET_IN : in std_logic;
139  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
140  GT0_RXDISPERR_OUT : out std_logic_vector(3 downto 0);
141  GT0_RXNOTINTABLE_OUT : out std_logic_vector(3 downto 0);
142  --------------------------- Receive Ports - RX AFE -------------------------
143  GT0_GTXRXP_IN : in std_logic;
144  ------------------------ Receive Ports - RX AFE Ports ----------------------
145  GT0_GTXRXN_IN : in std_logic;
146  ------------- Receive Ports - RX Initialization and Reset Ports ------------
147  GT0_GTRXRESET_IN : in std_logic;
148  GT0_RXPMARESET_IN : in std_logic;
149  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
150  GT0_RXCHARISK_OUT : out std_logic_vector(3 downto 0);
151  -------------- Receive Ports -RX Initialization and Reset Ports ------------
152  GT0_RXRESETDONE_OUT : out std_logic;
153  --------------------- TX Initialization and Reset Ports --------------------
154  GT0_GTTXRESET_IN : in std_logic;
155  GT0_TXUSERRDY_IN : in std_logic;
156  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
157  GT0_TXUSRCLK_IN : in std_logic;
158  GT0_TXUSRCLK2_IN : in std_logic;
159  ------------------ Transmit Ports - TX Data Path interface -----------------
160  GT0_TXDATA_IN : in std_logic_vector(31 downto 0);
161  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
162  GT0_GTXTXN_OUT : out std_logic;
163  GT0_GTXTXP_OUT : out std_logic;
164  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
165  GT0_TXOUTCLK_OUT : out std_logic;
166  GT0_TXOUTCLKFABRIC_OUT : out std_logic;
167  GT0_TXOUTCLKPCS_OUT : out std_logic;
168  --------------------- Transmit Ports - TX Gearbox Ports --------------------
169  GT0_TXCHARISK_IN : in std_logic_vector(3 downto 0);
170  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
171  GT0_TXRESETDONE_OUT : out std_logic;
172  ------------------ Transmit Ports - pattern Generator Ports ----------------
173  GT0_TXPRBSSEL_IN : in std_logic_vector(2 downto 0);
174 
175 
176  --____________________________COMMON PORTS________________________________
177  ---------------------- Common Block - Ref Clock Ports ---------------------
178  GT0_GTREFCLK0_COMMON_IN : in std_logic;
179  ------------------------- Common Block - QPLL Ports ------------------------
180  GT0_QPLLLOCK_OUT : out std_logic;
181  GT0_QPLLLOCKDETCLK_IN : in std_logic;
182  GT0_QPLLRESET_IN : in std_logic
183 
184 
185 );
186 end component;
187 signal version : std_logic_vector(2 downto 0) := "001";
188 signal MaskedTrigdata : array24x32 := (others => (others => '0'));
189 signal mask : array24x32 := (others => (others => '0'));
190 signal threshold : array8x4 := (others => (others => '0'));
191 signal NonZeroByteCnt : array16x4 := (others => (others => '0'));
192 signal NonZeroByte : std_logic_vector(95 downto 0) := (others => '0');
193 signal TrigDataOut : std_logic_vector(7 downto 0) := (others => '0');
194 signal RXDATA : std_logic_vector(31 downto 0) := (others => '0');
195 signal TXDATA : std_logic_vector(31 downto 0) := (others => '0');
196 signal Sample : std_logic := '0';
197 signal SampleSyncRegs : std_logic_vector(3 downto 0) := (others => '0');
198 signal RXBUF_we : std_logic := '0';
199 signal RXBUF_wa : std_logic_vector(4 downto 0) := (others => '0');
200 signal RXBUF_di : std_logic_vector(29 downto 0) := (others => '0');
201 signal RXBUF : std_logic_vector(29 downto 0) := (others => '0');
202 signal PRBSSEL : std_logic_vector(2 downto 0) := (others => '0');
203 signal PRBSERR_cnt : std_logic_vector(7 downto 0) := (others => '0');
204 signal RXCHARISK : std_logic_vector(3 downto 0) := (others => '0');
205 signal txfsmresetdone : std_logic := '0';
206 signal DATA_VALID : std_logic := '0';
207 signal CPLLLOCK : std_logic := '0';
208 signal CPLLRESET : std_logic := '0';
209 signal REFCLK : std_logic := '0';
210 signal PRBSERR : std_logic := '0';
211 signal GTRXRESET : std_logic := '0';
212 signal RXRESETDONE : std_logic := '0';
213 signal GTTXRESET : std_logic := '0';
214 signal bcnt : std_logic_vector(11 downto 0) := (others => '0');
215 signal trigmask : std_logic_vector(7 downto 0) := (others => '0');
216 signal reset_trig_dl_wa : std_logic := '0';
217 signal BC0_dl_i : std_logic := '0';
218 signal chk_lock : std_logic := '0';
219 signal chk_lock_q : std_logic := '0';
220 signal trig_dl_ra : std_logic_vector(11 downto 0) := (others => '0');
221 signal trig_dl_wa : std_logic_vector(11 downto 0) := (others => '0');
222 signal trig_dl_DI : std_logic_vector(3 downto 0) := (others => '0');
223 signal trig_dl_DO : std_logic_vector(3 downto 0) := (others => '0');
224 signal en_HCAL_trig : std_logic := '0';
225 signal ec_BX_offset : std_logic := '0';
226 signal BC0_locked : std_logic_vector(1 downto 0) := (others =>'0');
227 signal BX_offset_a : std_logic_vector(11 downto 0) := (others =>'0');
228 signal BX_offset_b : std_logic_vector(11 downto 0) := (others =>'0');
229 signal BX_offset_sum : std_logic_vector(12 downto 0) := (others =>'0');
230 signal LockLossCntr : std_logic_vector(3 downto 0) := (others =>'0');
231 signal BX_offset : std_logic_vector(11 downto 0) := (others =>'0');
232 signal en_BC0_gated : std_logic := '0';
233 signal got_BC0 : std_logic := '0';
234 signal catchBC0 : std_logic := '0';
235 signal BC0_gated : std_logic := '0';
236 signal BC0_gated_dl : std_logic := '0';
237 signal GT0_RXPD_IN : std_logic_vector(1 downto 0) := (others =>'0');
238 signal GT0_TXPD_IN : std_logic_vector(1 downto 0) := (others =>'0');
239 signal SFP_ABS_q : std_logic_vector(3 downto 0) := (others => '0');
240 signal reset_cntr : std_logic_vector(20 downto 0) := (others => '0');
241 signal soft_reset : std_logic := '0';
242 signal reset_cntr20_q : std_logic := '0';
243 begin
244 BC0_dl <= BC0_dl_i;
245 triggerOut <= trig_dl_DO(0);
246 GT0_RXPD_IN <= "00" when SFP_ABS = '0' else "11";
247 GT0_TXPD_IN <= "00" when SFP_ABS = '0' else "11";
248 -- this compensates 5 TTC clock delay in HCAL_trig(2) and ttc_if(3)
249 i_reset_trig_dl_wa : SRL16E
250  port map (
251  Q => reset_trig_dl_wa, -- SRL data output
252  A0 => '0', -- Select[0] input
253  A1 => '0', -- Select[1] input
254  A2 => '1', -- Select[2] input
255  A3 => '0', -- Select[3] input
256  CE => '1', -- Clock enable input
257  CLK => TTC_clk, -- Clock input
258  D => BC0_dl_i -- SRL data input
259  );
260 process(TTC_clk)
261 variable dif : std_logic_vector(11 downto 0);
262 begin
263  dif := x"dec" - BX_offset;
264  if(TTC_clk'event and TTC_clk = '1')then
265  if(BC0 = '1')then
266  trig_dl_ra <= (others => '0');
267  else
268  trig_dl_ra <= trig_dl_ra + 1;
269  end if;
270  if(reset_trig_dl_wa = '1')then
271  trig_dl_wa <= (others => '0');
272  else
273  trig_dl_wa <= trig_dl_wa + 1;
274  end if;
275  if(trig_dl_ra = BX_offset)then
276  BC0_dl_i <= '1';
277  else
278  BC0_dl_i <= '0';
279  end if;
280  chk_lock <= BC0_dl_i;
281  chk_lock_q <= chk_lock;
282  if(TTC_lock = '0' or LockLossCntr(3) = '1')then
283  BC0_locked <= "00";
284  elsif(chk_lock = '1')then
285  BC0_locked <= BC0_locked(0) & and_reduce(BC0_lock or (not AMC_en));
286  end if;
287  if(TTC_lock = '0' or LockLossCntr(3) = '1')then
288  BX_offset_a <= x"fff";
289  elsif(en_HCAL_trig = '0' and chk_lock_q = '1' and BC0_locked = "01")then
290  BX_offset_a <= BX_offset;
291  end if;
292  if(TTC_lock = '0' or LockLossCntr(3) = '1')then
293  BX_offset_b <= x"fff";
294  elsif(en_HCAL_trig = '0' and chk_lock_q = '1' and BC0_locked = "10")then
295  BX_offset_b <= BX_offset + 1;
296  end if;
297  BX_offset_sum <= ('0' & BX_offset_a) + ('0' & BX_offset_b);
298  if(TTC_lock = '0' or LockLossCntr(3) = '1')then
299  en_HCAL_trig <= '0';
300  elsif(and_reduce(BX_offset_a) = '0' and and_reduce(BX_offset_b) = '0')then
301  en_HCAL_trig <= '1';
302  end if;
303  if(en_HCAL_trig = '0')then
304  LockLossCntr <= (others => '0');
305  elsif(chk_lock_q = '1' and BC0_locked(1) = '0')then
306  LockLossCntr <= LockLossCntr + 1;
307  end if;
308  if(TTC_lock = '0')then
309  ec_BX_offset <= '0';
310  elsif(chk_lock = '1')then
311  ec_BX_offset <= '1';
312  else
313  ec_BX_offset <= '0';
314  end if;
315  if(TTC_lock = '0' or LockLossCntr(3) = '1')then
316  BX_offset <= x"deb";
317  elsif(en_HCAL_trig = '1')then
318  BX_offset <= BX_offset_sum(12 downto 1);
319  elsif(ec_BX_offset = '1')then
320  if(BX_offset = x"000")then
321  BX_offset <= x"deb";
322  else
323  BX_offset <= BX_offset - 1;
324  end if;
325  end if;
326  if(BX_offset(11) = '1')then
327  BX_offset2SC <= '1' & dif(10 downto 0);
328  else
329  BX_offset2SC <= BX_offset;
330  end if;
331  end if;
332 end process;
333 i_trig_dl : BRAM_SDP_MACRO
334  generic map (
335  BRAM_SIZE => "18Kb", -- Target BRAM, "18Kb" or "36Kb"
336  DEVICE => "7SERIES", -- Target device: "VIRTEX5", "VIRTEX6", "7SERIES", "SPARTAN6"
337  WRITE_WIDTH => 4, -- Valid values are 1-72 (37-72 only valid when BRAM_SIZE="36Kb")
338  READ_WIDTH => 4) -- Valid values are 1-72 (37-72 only valid when BRAM_SIZE="36Kb")
339  port map (
340  DO => trig_dl_DO, -- Output read data port, width defined by READ_WIDTH parameter
341  DI => trig_dl_DI, -- Input write data port, width defined by WRITE_WIDTH parameter
342  RDADDR => trig_dl_ra, -- Input read address, width defined by read port depth
343  RDCLK => TTC_Clk, -- 1-bit input read clock
344  RDEN => '1', -- 1-bit input read port enable
345  REGCE => '1', -- 1-bit input read output register enable
346  RST => '0', -- 1-bit input reset
347  WE => "1", -- Input write enable, width defined by write port depth
348  WRADDR => trig_dl_wa, -- Input write address, width defined by write port depth
349  WRCLK => TTC_Clk, -- 1-bit input write clock
350  WREN => '1' -- 1-bit input write port enable
351  );
352 process(TTC_Clk)
353 begin
354  if(TTC_Clk'event and TTC_Clk = '1')then
355  if(BC0_dl_i = '1')then
356  bcnt <= x"000";
357  else
358  bcnt <= bcnt + 1;
359  end if;
360  for i in 0 to 7 loop
361  if(en_HCAL_trig = '1' and (NonZeroByteCnt(i*2) + NonZeroByteCnt(i*2+1)) > threshold(i))then
362  TrigDataOut(i) <= '1';
363  else
364  TrigDataOut(i) <= '0';
365  end if;
366  end loop;
367  DATA_VALID <= not RXBUF_di(24);
368  if(PRBSSEL = "000")then
369  PRBSERR_cnt <= (others => '0');
370  elsif(PRBSERR = '1')then
371  PRBSERR_cnt <= PRBSERR_cnt + 1;
372  end if;
373  trig_dl_DI(0) <= en_HCAL_trig and or_reduce(trigmask and TrigDataOut);
374  SampleSyncRegs <= SampleSyncRegs(2 downto 0) & Sample;
375  if(SampleSyncRegs(3) /= SampleSyncRegs(2))then
376  RXBUF_we <= '1';
377  elsif((CatchBC0 = '0' and and_reduce(RXBUF_wa) = '1') or BC0_gated_dl = '1')then
378  RXBUF_we <= '0';
379  end if;
380  if(RXBUF_we = '0')then
381  RXBUF_wa <= "00010";
382  elsif(and_reduce(RXBUF_wa) = '1')then
383  RXBUF_wa <= "00010";
384  else
385  RXBUF_wa <= RXBUF_wa + 1;
386  end if;
387  if(got_BC0 = '1' or RXBUF_we = '0')then
388  en_BC0_gated <= '0';
389  elsif(RXBUF_wa(4) = '1')then
390  en_BC0_gated <= '1';
391  end if;
392  if(RXBUF_we = '0')then
393  got_BC0 <= '0';
394  elsif(BC0_gated = '1')then
395  got_BC0 <= '1';
396  end if;
397  BC0_gated <= RXDATA(15) and en_BC0_gated;
398  end if;
399 end process;
400 i_BC0_gated_dl : SRL16E
401  port map (
402  Q => BC0_gated_dl, -- SRL data output
403  A0 => '0', -- Select[0] input
404  A1 => '1', -- Select[1] input
405  A2 => '1', -- Select[2] input
406  A3 => '1', -- Select[3] input
407  CE => '1', -- Clock enable input
408  CLK => TTC_Clk, -- Clock input
409  D => BC0_gated -- SRL data input
410  );
411 g_RXBUF : for i in 0 to 4 generate
412  i_ipbus_rbuf : RAM32x6Db PORT MAP(
413  wclk => TTC_Clk,
414  di => RXBUF_di(i*6+5 downto i*6),
415  we => RXBUF_we,
416  wa => RXBUF_wa,
417  ra => ipb_addr(4 downto 0),
418  do => RXBUF(i*6+5 downto i*6)
419  );
420 end generate;
421 TXDATA <= TrigDataOut & bcnt(7 downto 0) & chk_lock & version & bcnt(11 downto 8) & x"bc";
422 RXBUF_di(24) <= '0' when RXDATA(7 downto 0) = x"bc" and RXCHARISK = x"1" else '1';
423 RXBUF_di(23 downto 0) <= RXDATA(31 downto 24) & RXDATA(15 downto 8) & RXDATA(23 downto 16);
424 process(ipb_clk)
425 begin
426  if(ipb_clk'event and ipb_clk = '1')then
427  if(ipb_addr(27) = '0' and ipb_addr(15 downto 4) = x"100" and ipb_write = '1' and ipb_strobe = '1')then
428  mask(conv_integer(ipb_addr(3 downto 0))) <= ipb_wdata;
429  end if;
430  if(ipb_addr(27) = '0' and ipb_addr(15 downto 4) = x"101" and ipb_write = '1' and ipb_strobe = '1')then
431  if(ipb_addr(3) = '0')then
432  mask(16+conv_integer(ipb_addr(2 downto 0))) <= ipb_wdata;
433  else
434  threshold(conv_integer(ipb_addr(2 downto 0))) <= ipb_wdata(3 downto 0);
435  end if;
436  end if;
437  if(ipb_addr(27) = '0' and ipb_addr(15 downto 0) = x"1020" and ipb_write = '1' and ipb_strobe = '1')then
438  PRBSSEL <= ipb_wdata(2 downto 0);
439  end if;
440  if(ipb_addr(27) = '0' and ipb_addr(15 downto 0) = x"1021" and ipb_write = '1' and ipb_strobe = '1')then
441  Sample <= Sample xor ipb_wdata(0);
442  CatchBC0 <= ipb_wdata(1);
443  end if;
444  if(ipb_addr(27) = '0' and ipb_addr(15 downto 0) = x"1040" and ipb_write = '1' and ipb_strobe = '1')then
445  trigmask <= ipb_wdata(7 downto 0);
446  end if;
447  end if;
448 end process;
449 process(ipb_addr, mask, threshold)
450 begin
451  if(ipb_addr(15 downto 7) = "000100000")then
452  if(ipb_addr(6 downto 0) = "1000000")then
453  ipb_rdata <= x"000000" & trigmask;
454  elsif(ipb_addr(5 downto 4) = "00")then
455  ipb_rdata <= mask(conv_integer(ipb_addr(3 downto 0)));
456  elsif(ipb_addr(5 downto 3) = "010")then
457  ipb_rdata <= mask(16+conv_integer(ipb_addr(2 downto 0)));
458  elsif(ipb_addr(5 downto 3) = "011")then
459  ipb_rdata <= x"0000000" & threshold(conv_integer(ipb_addr(2 downto 0)));
460  elsif(ipb_addr(5 downto 0) = "100000")then
461  ipb_rdata <= x"0000000" & '0' & PRBSSEL;
462  elsif(ipb_addr(5 downto 0) = "100001")then
463  ipb_rdata <= x"000000" & PRBSERR_cnt;
464  elsif(ipb_addr(5) = '1')then
465  ipb_rdata <= RXBUF(24) & "0000000" & RXBUF(23 downto 0);
466  else
467  ipb_rdata <= (others => '0');
468  end if;
469  else
470  ipb_rdata <= (others => '0');
471  end if;
472 end process;
473 g_MaskedTrigdata : for i in 0 to 7 generate
474  g_MaskedTrigdataJ : for j in 0 to 2 generate
475  g_MaskedTrigdataK : for k in 0 to 3 generate
476  MaskedTrigdata(i*3+j)(k*8+7 downto k*8) <= not mask(i*3+j)(k*8+7 downto k*8) and Trigdata(j*4+k);
477  end generate;
478  end generate;
479 end generate;
480 g_NonZeroByte : for i in 0 to 23 generate
481  g_NonZeroByteJ : for j in 0 to 3 generate
482  NonZeroByte(i*4+j) <= '0' when MaskedTrigdata(i)(j*8+7 downto j*8) = x"00" else '1';
483  end generate;
484 end generate;
485 g_NonZeroByteCnt_i : for i in 0 to 1 generate
486  g_NonZeroByteCnt_j : for j in 0 to 7 generate
487  i_bitcount0 : ROM64X1
488  generic map (
489  INIT => X"6996966996696996") -- bit 0
490  port map (
491  O => NonZeroByteCnt (j*2+i)(0), -- ROM output
492  A0 => NonZeroByte(i*6+j*12), -- ROM address[0]
493  A1 => NonZeroByte(i*6+1+j*12), -- ROM address[1]
494  A2 => NonZeroByte(i*6+2+j*12), -- ROM address[2]
495  A3 => NonZeroByte(i*6+3+j*12), -- ROM address[3]
496  A4 => NonZeroByte(i*6+4+j*12), -- ROM address[4]
497  A5 => NonZeroByte(i*6+5+j*12) -- ROM address[5]
498  );
499  i_bitcount1 : ROM64X1
500  generic map (
501  INIT => X"8117177e177e7ee8") -- bit 1
502  port map (
503  O => NonZeroByteCnt (j*2+i)(1), -- ROM output
504  A0 => NonZeroByte(i*6+j*12), -- ROM address[0]
505  A1 => NonZeroByte(i*6+1+j*12), -- ROM address[1]
506  A2 => NonZeroByte(i*6+2+j*12), -- ROM address[2]
507  A3 => NonZeroByte(i*6+3+j*12), -- ROM address[3]
508  A4 => NonZeroByte(i*6+4+j*12), -- ROM address[4]
509  A5 => NonZeroByte(i*6+5+j*12) -- ROM address[5]
510  );
511  i_bitcount2 : ROM64X1
512  generic map (
513  INIT => X"fee8e880e8808000") -- bit 2
514  port map (
515  O => NonZeroByteCnt (j*2+i)(2), -- ROM output
516  A0 => NonZeroByte(i*6+j*12), -- ROM address[0]
517  A1 => NonZeroByte(i*6+1+j*12), -- ROM address[1]
518  A2 => NonZeroByte(i*6+2+j*12), -- ROM address[2]
519  A3 => NonZeroByte(i*6+3+j*12), -- ROM address[3]
520  A4 => NonZeroByte(i*6+4+j*12), -- ROM address[4]
521  A5 => NonZeroByte(i*6+5+j*12) -- ROM address[5]
522  );
523  end generate;
524 end generate;
525 process(DRPclk)
526 begin
527  if(DRPclk'event and DRPclk = '1')then
528  SFP_ABS_q <= SFP_ABS_q(2 downto 0) & SFP_ABS;
529  if(SFP_ABS_q(3 downto 2) = "10")then
530  reset_cntr <= (others => '0');
531  elsif(reset_cntr(20) = '0')then
532  reset_cntr <= reset_cntr + 1;
533  end if;
534  reset_cntr20_q <= reset_cntr(20);
535  soft_reset <= not reset_cntr20_q and reset_cntr(20);
536  end if;
537 end process;
538 uHTR_trig_init_i : uHTR_trigPD_init
539  generic map
540  (
541  EXAMPLE_SIM_GTRESET_SPEEDUP => "TRUE",
542  EXAMPLE_SIMULATION => 0,
543  STABLE_CLOCK_PERIOD => 20,
544  EXAMPLE_USE_CHIPSCOPE => 0
545  )
546  port map
547  (
548  SYSCLK_IN => DRPCLK,
549  SOFT_RESET_IN => soft_reset,
550  DONT_RESET_ON_DATA_ERROR_IN => '0',
551  GT0_TX_FSM_RESET_DONE_OUT => txfsmresetdone,
552  GT0_RX_FSM_RESET_DONE_OUT => open,
553  GT0_DATA_VALID_IN => DATA_VALID,
554 
555 
556 
557 
558 
559  --_____________________________________________________________________
560  --_____________________________________________________________________
561  --GT0 (X1Y12)
562 
563  --------------------------------- CPLL Ports -------------------------------
564  GT0_CPLLFBCLKLOST_OUT => open,
565  GT0_CPLLLOCK_OUT => CPLLLOCK,
566  GT0_CPLLLOCKDETCLK_IN => DRPCLK,
567  GT0_CPLLRESET_IN => CPLLRESET,
568  -------------------------- Channel - Clocking Ports ------------------------
569  GT0_GTREFCLK0_IN => REFCLK,
570  ---------------------------- Channel - DRP Ports --------------------------
571  GT0_DRPADDR_IN => (others => '0'),
572  GT0_DRPCLK_IN => DRPCLK,
573  GT0_DRPDI_IN => (others => '0'),
574  GT0_DRPDO_OUT => open,
575  GT0_DRPEN_IN => '0',
576  GT0_DRPRDY_OUT => open,
577  GT0_DRPWE_IN => '0',
578  ------------------------------ Power-Down Ports ----------------------------
579  GT0_RXPD_IN => GT0_RXPD_IN,
580  GT0_TXPD_IN => GT0_TXPD_IN,
581  --------------------- RX Initialization and Reset Ports --------------------
582  GT0_RXUSERRDY_IN => '0',
583  -------------------------- RX Margin Analysis Ports ------------------------
584  GT0_EYESCANDATAERROR_OUT => open,
585  ------------------------- Receive Ports - CDR Ports ------------------------
586  GT0_RXCDRLOCK_OUT => open,
587  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
588  GT0_RXUSRCLK_IN => TTC_clk,
589  GT0_RXUSRCLK2_IN => TTC_clk,
590  ------------------ Receive Ports - FPGA RX interface Ports -----------------
591  GT0_RXDATA_OUT => RXDATA,
592  ------------------- Receive Ports - Pattern Checker Ports ------------------
593  GT0_RXPRBSERR_OUT => PRBSERR,
594  GT0_RXPRBSSEL_IN => PRBSSEL,
595  ------------------- Receive Ports - Pattern Checker ports ------------------
596  GT0_RXPRBSCNTRESET_IN => '0',
597  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
598  GT0_RXDISPERR_OUT => open,
599  GT0_RXNOTINTABLE_OUT => open,
600  --------------------------- Receive Ports - RX AFE -------------------------
601  GT0_GTXRXP_IN => GTX_RXp,
602  ------------------------ Receive Ports - RX AFE Ports ----------------------
603  GT0_GTXRXN_IN => GTX_RXn,
604  ------------- Receive Ports - RX Initialization and Reset Ports ------------
605  GT0_GTRXRESET_IN => '0',
606  GT0_RXPMARESET_IN => '0',
607  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
608  GT0_RXCHARISK_OUT => RXCHARISK,
609  -------------- Receive Ports -RX Initialization and Reset Ports ------------
610  GT0_RXRESETDONE_OUT => RXRESETDONE,
611  --------------------- TX Initialization and Reset Ports --------------------
612  GT0_GTTXRESET_IN => '0',
613  GT0_TXUSERRDY_IN => '0',
614  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
615  GT0_TXUSRCLK_IN => TTC_Clk,
616  GT0_TXUSRCLK2_IN => TTC_Clk,
617  ------------------ Transmit Ports - TX Data Path interface -----------------
618  GT0_TXDATA_IN => TXDATA,
619  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
620  GT0_GTXTXN_OUT => GTX_TXn,
621  GT0_GTXTXP_OUT => GTX_TXp,
622  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
623  GT0_TXOUTCLK_OUT => open,
624  GT0_TXOUTCLKFABRIC_OUT => open,
625  GT0_TXOUTCLKPCS_OUT => open,
626  --------------------- Transmit Ports - TX Gearbox Ports --------------------
627  GT0_TXCHARISK_IN => x"1",
628  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
629  GT0_TXRESETDONE_OUT => open,
630  ------------------ Transmit Ports - pattern Generator Ports ----------------
631  GT0_TXPRBSSEL_IN => PRBSSEL,
632 
633 
634 
635 
636  --____________________________COMMON PORTS________________________________
637  ---------------------- Common Block - Ref Clock Ports ---------------------
638  GT0_GTREFCLK0_COMMON_IN => '0',
639  ------------------------- Common Block - QPLL Ports ------------------------
640  GT0_QPLLLOCK_OUT => open,
641  GT0_QPLLLOCKDETCLK_IN => '0',
642  GT0_QPLLRESET_IN => '0'
643 
644  );
645 
646 i_REFCLK : IBUFDS_GTE2
647  port map
648  (
649  O => REFCLK,
650  ODIV2 => open,
651  CEB => '0',
652  I => GTX_REFCLKp,
653  IB => GTX_REFCLKn
654  );
655 end Behavioral;
656 
Generated on Wed Apr 18 2018 10:55:28 for AMC13 by   doxygen 1.8.1