Behavioral Architecture Reference

List of all members.

Processes
PROCESS_979	( clk ,fifo_rst )
PROCESS_980	( clk )

Types
array2x7	array ( 0 to 1 ) of std_logic_vector ( 6 downto 0 )
array2x65	array ( 0 to 1 ) of std_logic_vector ( 64 downto 0 )
array15X13	array ( 0 to 14 ) of std_logic_vector ( 12 downto 0 )

Signals
fifo_re	array2X7 := ( others = > ( others = > ' 0 ' ) )
fifo_we	array2X7 := ( others = > ( others = > ' 0 ' ) )
dip	array2X65 := ( others = > ( others = > ' 0 ' ) )
dop	array2X65 := ( others = > ( others = > ' 0 ' ) )
fifo_empty	std_logic_vector ( 13 downto 0 ) := ( others = > ' 0 ' )
fifo_full	std_logic_vector ( 13 downto 0 ) := ( others = > ' 0 ' )
fifo_Almostfull	std_logic_vector ( 13 downto 0 ) := ( others = > ' 0 ' )
rdcount	array15X13 := ( others = > ( others = > ' 0 ' ) )
wrcount	array15X13 := ( others = > ( others = > ' 0 ' ) )
BRAM_re	std_logic := ' 0 '
BRAM_vld	std_logic := ' 0 '
wa_equal_ra_q	std_logic := ' 0 '
do_vld	std_logic_vector ( 1 downto 0 ) := ( others = > ' 0 ' )
wa	std_logic_vector ( 12 downto 0 ) := ( others = > ' 0 ' )
ra	std_logic_vector ( 12 downto 0 ) := ( others = > ' 0 ' )

---

Detailed Description

Definition at line 50 of file FIFO65x12k.vhd.

---

The documentation for this class was generated from the following files:

• src/TCPIP_if/FIFO65x12k.vhd