AMC13
Firmwares for the different applications of the AMC13 uTCA board made at Boston University
 All Classes Variables
FIFO65x12k.vhd
1 ----------------------------------------------------------------------------------
2 -- Company:
3 -- Engineer:
4 --
5 -- Create Date: 10:01:22 10/08/2013
6 -- Design Name:
7 -- Module Name: FIFO72x8192 - Behavioral
8 -- Project Name:
9 -- Target Devices:
10 -- Tool versions:
11 -- Description:
12 --
13 -- Dependencies:
14 --
15 -- Revision:
16 -- Revision 0.01 - File Created
17 -- Additional Comments:
18 --
19 ----------------------------------------------------------------------------------
20 library IEEE;
21 use IEEE.STD_LOGIC_1164.ALL;
22 use IEEE.STD_LOGIC_ARITH.ALL;
23 use IEEE.STD_LOGIC_UNSIGNED.ALL;
24 use IEEE.std_logic_misc.all;
25 
26 -- Uncomment the following library declaration if using
27 -- arithmetic functions with Signed or Unsigned values
28 --use IEEE.NUMERIC_STD.ALL;
29 
30 -- Uncomment the following library declaration if instantiating
31 -- any Xilinx primitives in this code.
32 library UNISIM;
33 use UNISIM.VComponents.all;
34 Library UNIMACRO;
35 use UNIMACRO.vcomponents.all;
36 
37 entity FIFO65x12k is
38  generic(ALMOSTFULL_OFFSET : bit_vector(15 downto 0) := x"0008");
39  Port ( clk : in STD_LOGIC;
40  fifo_rst : in STD_LOGIC;
41  fifo_en : in STD_LOGIC;
42  di : in STD_LOGIC_VECTOR (64 downto 0);
43  we : in STD_LOGIC;
44  re : in STD_LOGIC;
45  do : out STD_LOGIC_VECTOR (64 downto 0);
46  full : out STD_LOGIC;
47  empty : out STD_LOGIC);
48 end FIFO65x12k;
49 
50 architecture Behavioral of FIFO65x12k is
51 type array2x7 is array (0 to 1) of std_logic_vector(6 downto 0);
52 signal fifo_re : array2X7 := (others => (others => '0'));
53 signal fifo_we : array2X7 := (others => (others => '0'));
54 type array2x65 is array (0 to 1) of std_logic_vector(64 downto 0);
55 signal dip : array2X65 := (others => (others => '0'));
56 signal dop : array2X65 := (others => (others => '0'));
57 signal fifo_empty : std_logic_vector(13 downto 0) := (others => '0');
58 signal fifo_full : std_logic_vector(13 downto 0) := (others => '0');
59 signal fifo_Almostfull : std_logic_vector(13 downto 0) := (others => '0');
60 type array15X13 is array (0 to 14) of std_logic_vector(12 downto 0);
61 signal rdcount : array15X13 := (others => (others => '0'));
62 signal wrcount : array15X13 := (others => (others => '0'));
63 signal BRAM_re : std_logic := '0';
64 signal BRAM_vld : std_logic := '0';
65 signal wa_equal_ra_q : std_logic := '0';
66 signal do_vld : std_logic_vector(1 downto 0) := (others => '0');
67 signal wa : std_logic_vector(12 downto 0) := (others => '0');
68 signal ra : std_logic_vector(12 downto 0) := (others => '0');
69 
70 begin
71 g_FIFO_j: for j in 0 to 1 generate
72  g_FIFO: for i in 0 to 6 generate
73  i_FIFO : FIFO_DUALCLOCK_MACRO
74  generic map (
75  DEVICE => "7SERIES", -- Target Device: "VIRTEX5", "VIRTEX6", "7SERIES"
76  ALMOST_FULL_OFFSET => ALMOSTFULL_OFFSET, -- Sets almost full threshold
77  DATA_WIDTH => 9, -- Valid values are 1-72 (37-72 only valid when FIFO_SIZE="36Kb")
78  FIFO_SIZE => "36Kb", -- Target BRAM, "18Kb" or "36Kb"
79  FIRST_WORD_FALL_THROUGH => TRUE) -- Sets the FIFO FWFT to TRUE or FALSE
80  port map (
81  ALMOSTEMPTY => open, -- 1-bit output almost empty
82  ALMOSTFULL => fifo_Almostfull(j*7+i), -- 1-bit output almost full
83  DO => dop(j)(i*9+8 downto i*9), -- Output data, width defined by DATA_WIDTH parameter
84  EMPTY => fifo_empty(j*7+i), -- 1-bit output empty
85  FULL => FIFO_full(j*7+i), -- 1-bit output full
86  RDCOUNT => rdcount(j*7+i)(11 downto 0), -- Output read count, width determined by FIFO depth
87  RDERR => open, -- 1-bit output read error
88  WRCOUNT => wrcount(j*7+i)(11 downto 0), -- Output write count, width determined by FIFO depth
89  WRERR => open, -- 1-bit output write error
90  DI => dip(j)(i*9+8 downto i*9), -- Input data, width defined by DATA_WIDTH parameter
91  RDCLK => clk, -- 1-bit input read clock
92  RDEN => FIFO_re(j)(i), -- 1-bit input read enable
93  RST => fifo_rst, -- 1-bit input reset
94  WRCLK => clk, -- 1-bit input write clock
95  WREN => FIFO_we(j)(i) -- 1-bit input write enable
96  );
97  end generate;
98 end generate;
99 dip(0) <= di;
100 dip(1)(62 downto 0) <= dop(0)(62 downto 0);
101 FIFO6463 : BRAM_SDP_MACRO
102  generic map (
103  BRAM_SIZE => "18Kb", -- Target BRAM, "18Kb" or "36Kb"
104  DEVICE => "7SERIES", -- Target device: "VIRTEX5", "VIRTEX6", "7SERIES", "SPARTAN6"
105  WRITE_WIDTH => 2, -- Valid values are 1-72 (37-72 only valid when BRAM_SIZE="36Kb")
106  READ_WIDTH => 2) -- Valid values are 1-72 (37-72 only valid when BRAM_SIZE="36Kb")
107  port map (
108  DO => dop(1)(64 downto 63), -- Output read data port, width defined by READ_WIDTH parameter
109  DI => dip(0)(64 downto 63), -- Input write data port, width defined by WRITE_WIDTH parameter
110  RDADDR => ra, -- Input read address, width defined by read port depth
111  RDCLK => clk, -- 1-bit input read clock
112  RDEN => BRAM_re, -- 1-bit input read port enable
113  REGCE => '0', -- 1-bit input read output register enable
114  RST => '0', -- 1-bit input reset
115  WE => "1", -- Input write enable, width defined by write port depth
116  WRADDR => wa, -- Input write address, width defined by write port depth
117  WRCLK => clk, -- 1-bit input write clock
118  WREN => we -- 1-bit input write port enable
119  );
120 process(clk,fifo_rst)
121 begin
122  if(fifo_rst = '1')then
123  wa <= (others => '0');
124  ra <= (others => '0');
125  wa_equal_ra_q <= '0';
126  BRAM_vld <= '0';
127  do_vld <= "00";
128  empty <= '1';
129  elsif(clk'event and clk = '1')then
130  if(we = '1' and fifo_en = '1')then
131  wa <= wa + 1;
132  end if;
133  if(BRAM_re = '1')then
134  ra <= ra + 1;
135  end if;
136  if(wa = ra)then
137  wa_equal_ra_q <= '1';
138  else
139  wa_equal_ra_q <= '0';
140  end if;
141  if(BRAM_re = '1')then
142  BRAM_vld <= '1';
143  elsif(do_vld(1) = '0' or re = '1')then
144  BRAM_vld <= '0';
145  end if;
146  if(BRAM_vld = '1')then
147  do_vld(1) <= '1';
148  elsif(re = '1')then
149  do_vld(1) <= '0';
150  end if;
151  if(fifo_empty(13) = '0')then
152  do_vld(0) <= '1';
153  elsif(re = '1')then
154  do_vld(0) <= '0';
155  end if;
156  if(fifo_empty(13) = '0')then
157  empty <= '0';
158  elsif(re = '1')then
159  empty <= '1';
160  end if;
161  end if;
162 end process;
163 BRAM_re <= '1' when fifo_en = '1' and wa /= ra and wa_equal_ra_q = '0' and (BRAM_vld = '0' or do_vld(1) = '0' or re = '1') else '0';
164 process(clk)
165 begin
166  if(clk'event and clk = '1')then
167  if(do_vld(1) = '0' or re = '1')then
168  do(64 downto 63) <= dop(1)(64 downto 63);
169  end if;
170  if(do_vld(0) = '0' or re = '1')then
171  do(62 downto 0) <= dop(1)(62 downto 0);
172  end if;
173  end if;
174 end process;
175 g_we_re : for i in 0 to 6 generate
176  FIFO_we(0)(i) <= '1' when we = '1' and FIFO_en = '1' else '0';
177  FIFO_we(1)(i) <= '1' when FIFO_full(7+i) = '0' and fifo_empty(i) = '0' and FIFO_en = '1' else '0';
178  FIFO_re(1)(i) <= '1' when FIFO_en = '1' and fifo_empty(13) = '0' and (do_vld(0) = '0' or re = '1') else '0';
179 end generate;
180 FIFO_re(0) <= FIFO_we(1);
181 full <= fifo_Almostfull(0);
182 end Behavioral;
183 
Generated on Wed Apr 18 2018 10:55:28 for AMC13 by   doxygen 1.8.1