AMC13
Firmwares for the different applications of the AMC13 uTCA board made at Boston University
|
Functions | |
integer | boolean_to_int_w ( biw: in boolean ) |
integer | boolean_to_int_u ( biu: in boolean ) |
Processes | |
PROCESS_26 | ( EventDataClk ,FIFO_rst ) |
PROCESS_27 | ( UsrClk ) |
PROCESS_28 | ( UsrClk ) |
PROCESS_29 | ( UsrClk ,reset ,RxResetDone ,TxResetDone ,rst_wait ,RXPLLLKDET ) |
PROCESS_30 | ( UsrClk ) |
PROCESS_31 | ( EventDataClk ,reset ,InitLink ,rst_input_evn ) |
PROCESS_32 | ( EventDataClk ,reset ,InitLink ) |
PROCESS_33 | ( UsrClk ) |
PROCESS_34 | ( UsrClk ,EventData_valid ) |
PROCESS_35 | ( UsrClk ) |
PROCESS_36 | ( UsrClk ) |
PROCESS_37 | ( UsrClk ) |
PROCESS_38 | ( UsrClk ) |
PROCESS_39 | ( TTSclk ) |
PROCESS_40 | ( UsrClk ) |
PROCESS_41 | ( sysclk ,InitLink ) |
Components | |
crc16D16 | <Entity crc16D16> |
EthernetCRCD32 | <Entity EthernetCRCD32> |
TTS_TRIG_if | |
fifo66X512 | <Entity fifo66X512> |
cs_delay |
Constants | |
version | std_logic_vector ( 7 downto 0 ) := x " 14 " |
N | integer := 8 |
w | integer := boolean_to_int_w ( simulation ) |
u | integer := boolean_to_int_u ( simulation ) |
Acknowledge | std_logic_vector ( 7 downto 0 ) := x " 12 " |
data | std_logic_vector ( 7 downto 0 ) := x " 34 " |
InitRqst | std_logic_vector ( 7 downto 0 ) := x " 56 " |
Counter | std_logic_vector ( 7 downto 0 ) := x " 78 " |
K_word | std_logic_vector ( 15 downto 0 ) := x " 3cbc " |
R_word | std_logic_vector ( 15 downto 0 ) := x " dcfb " |
eof_word | std_logic_vector ( 15 downto 0 ) := x " 5cf7 " |
IDLE | std_logic_vector ( 3 downto 0 ) := x " 0 " |
SendK | std_logic_vector ( 3 downto 0 ) := x " 1 " |
SendType | std_logic_vector ( 3 downto 0 ) := x " 2 " |
SendSEQ | std_logic_vector ( 3 downto 0 ) := x " 3 " |
SendWC | std_logic_vector ( 3 downto 0 ) := x " 4 " |
WaitCRC | std_logic_vector ( 3 downto 0 ) := x " 5 " |
WaitData | std_logic_vector ( 3 downto 0 ) := x " 6 " |
SendCRC | std_logic_vector ( 3 downto 0 ) := x " 7 " |
SendData | std_logic_vector ( 3 downto 0 ) := x " 8 " |
SendCntr | std_logic_vector ( 3 downto 0 ) := x " 9 " |
SendEOF | std_logic_vector ( 3 downto 0 ) := x " a " |
Signals | |
TxState | std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' ) |
sel_TTS_TRIG | std_logic := ' 0 ' |
bcnt_err_cnt | std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' ) |
reset_sync | std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' ) |
rst_cdr | std_logic := ' 0 ' |
rst_wait | std_logic := ' 0 ' |
wait_cntr | std_logic_vector ( w downto 0 ) := ( others = > ' 0 ' ) |
UsrClkDiv | std_logic_vector ( 1 downto 0 ) := ( others = > ' 0 ' ) |
TTS_TRIG_data | std_logic_vector ( 17 downto 0 ) := ( others = > ' 0 ' ) |
ResetFIFO_sync | std_logic_vector ( 1 downto 0 ) := ( others = > ' 0 ' ) |
AlmostFull_i | std_logic := ' 0 ' |
Init_EventCRC | std_logic := ' 0 ' |
ce_EventCRC | std_logic := ' 0 ' |
EventCRC_d | std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' ) |
EventCRC | std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' ) |
BoE | std_logic := ' 0 ' |
BoE_q | std_logic := ' 0 ' |
EoE | std_logic := ' 0 ' |
FillDataBuf | std_logic := ' 0 ' |
dataBuf_WrEn | std_logic := ' 0 ' |
DataBuf_wa | std_logic_vector ( 14 downto 0 ) := ( others = > ' 0 ' ) |
DataBuf_ra | std_logic_vector ( 14 downto 0 ) := ( others = > ' 0 ' ) |
DataBuf_start | std_logic_vector ( 14 downto 0 ) := ( others = > ' 0 ' ) |
DataBuf_Din | std_logic_vector ( 16 downto 0 ) := ( others = > ' 0 ' ) |
DataBuf_Dout | std_logic_vector ( 16 downto 0 ) := ( others = > ' 0 ' ) |
ec_DataBuf_ra | std_logic := ' 0 ' |
ec_DataBuf_ra_q | std_logic := ' 0 ' |
DataBuf_full | std_logic := ' 0 ' |
DataBuf_used | std_logic_vector ( 14 downto 0 ) := ( others = > ' 0 ' ) |
DataBuf_wc | std_logic_vector ( 14 downto 0 ) := ( others = > ' 0 ' ) |
ReSendQueOut_q | std_logic_vector ( 14 downto 0 ) := ( others = > ' 0 ' ) |
ReSendQue_a | std_logic_vector ( 1 downto 0 ) := ( others = > ' 1 ' ) |
ReSendQue_empty | std_logic := ' 1 ' |
we_DataPipe | std_logic := ' 0 ' |
DataPipeDo | std_logic_vector ( 16 downto 0 ) := ( others = > ' 0 ' ) |
DataPipe_a | std_logic_vector ( 3 downto 0 ) := ( others = > ' 1 ' ) |
DataPipe_empty | std_logic := ' 1 ' |
EventStatus_empty | std_logic := ' 1 ' |
DataPipe_full | std_logic := ' 0 ' |
InitLink | std_logic := ' 0 ' |
InitACK | std_logic := ' 0 ' |
ReSend | std_logic := ' 0 ' |
FoundEOF | std_logic := ' 0 ' |
ACK | std_logic := ' 0 ' |
CntrACK | std_logic := ' 0 ' |
L1Aabort | std_logic := ' 0 ' |
timer | std_logic_vector ( N downto 0 ) := ( others = > ' 0 ' ) |
we_ReSendQue | std_logic := ' 0 ' |
we_TxCRC | std_logic := ' 0 ' |
Init_TxCRC | std_logic := ' 0 ' |
R_word_cnt | std_logic_vector ( 11 downto 0 ) := ( others = > ' 0 ' ) |
TxCRC | std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' ) |
R_word_sent | std_logic := ' 0 ' |
sel_cntr | std_logic := ' 0 ' |
we_TxFIFO | std_logic := ' 0 ' |
TxFIFO_empty | std_logic := ' 1 ' |
TxFIFO_full | std_logic := ' 0 ' |
TxFIFO_a | std_logic_vector ( 3 downto 0 ) := ( others = > ' 1 ' ) |
TxFIFO_Dip | std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' ) |
TxFIFO_Di | std_logic_vector ( 16 downto 0 ) := ( others = > ' 0 ' ) |
TxFIFO_Do | std_logic_vector ( 16 downto 0 ) := ( others = > ' 0 ' ) |
packet_wc | std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' ) |
ACKNUM_IN | std_logic_vector ( 7 downto 0 ) := x " 00 " |
RxSEQNUM | std_logic_vector ( 7 downto 0 ) := x " 00 " |
SEQNUM | std_logic_vector ( 7 downto 0 ) := x " 00 " |
NextSEQNUM | std_logic_vector ( 7 downto 0 ) := x " 00 " |
ACKNUM | std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' ) |
bad_K | std_logic := ' 0 ' |
SEQ_OK | std_logic := ' 0 ' |
IllegalSeq | std_logic := ' 0 ' |
CRC_OK | std_logic := ' 0 ' |
frame_OK | std_logic := ' 0 ' |
TypeInit | std_logic := ' 0 ' |
TypeACK | std_logic := ' 0 ' |
TypeData | std_logic := ' 0 ' |
TypeCntr | std_logic := ' 0 ' |
Receiving | std_logic := ' 0 ' |
Header2 | std_logic := ' 0 ' |
TxType | std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' ) |
AMC_ID | std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' ) |
RxType | std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' ) |
RxWC | std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' ) |
check_packet | std_logic := ' 0 ' |
WC_OKp | std_logic := ' 0 ' |
WC_OK | std_logic := ' 0 ' |
L1Ainfo | std_logic := ' 0 ' |
ACK_OK | std_logic := ' 0 ' |
we_ACKNUM | std_logic := ' 0 ' |
accept | std_logic := ' 0 ' |
IsACK | std_logic := ' 0 ' |
IsCntr | std_logic := ' 0 ' |
IsData | std_logic := ' 0 ' |
CntrSent | std_logic := ' 0 ' |
ReSendQueIn | std_logic_vector ( 27 downto 0 ) := ( others = > ' 0 ' ) |
ReSendQueOut | std_logic_vector ( 27 downto 0 ) := ( others = > ' 0 ' ) |
ACKNUM_full | std_logic := ' 0 ' |
ACKNUM_empty | std_logic := ' 1 ' |
AMC_info | std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' ) |
ACKNUM_l | std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' ) |
ACKNUM_a | std_logic_vector ( 1 downto 0 ) := ( others = > ' 1 ' ) |
we_RxCRC | std_logic := ' 0 ' |
Init_RxCRC | std_logic := ' 0 ' |
RxCRC | std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' ) |
AMCinfo_WrEn | std_logic := ' 0 ' |
AMCinfo_wa | std_logic_vector ( 9 downto 0 ) := ( others = > ' 0 ' ) |
AMCinfo_sel | std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' ) |
AMCinfo_Di | std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' ) |
AMCinfo_Do | std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' ) |
evnLSB | std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' ) |
bad_ID | std_logic := ' 0 ' |
AMC_header | std_logic := ' 0 ' |
L1Ainfo_WrEn | std_logic := ' 0 ' |
OldL1Ainfo_wa | std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' ) |
L1Ainfo_wa | std_logic_vector ( 9 downto 0 ) := ( others = > ' 0 ' ) |
info_ra | std_logic_vector ( 9 downto 0 ) := ( others = > ' 0 ' ) |
L1Ainfo_Di | std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' ) |
L1Ainfo_Do | std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' ) |
L1Ainfo_empty | std_logic := ' 1 ' |
RxL1Ainfo | std_logic := ' 0 ' |
AMCinfo_empty | std_logic := ' 1 ' |
ce_info_ra | std_logic := ' 0 ' |
check_L1Ainfo | std_logic := ' 0 ' |
check_L1Ainfo_q | std_logic := ' 0 ' |
L1AinfoMM | std_logic := ' 0 ' |
info_ra_q | std_logic_vector ( 1 downto 0 ) := ( others = > ' 0 ' ) |
info_ra_q2 | std_logic_vector ( 1 downto 0 ) := ( others = > ' 0 ' ) |
we_EventStatus | std_logic := ' 0 ' |
EventData2Send | std_logic := ' 0 ' |
UnknownEventLength | std_logic := ' 1 ' |
bad_EventLength | std_logic := ' 1 ' |
EventLength | std_logic_vector ( 19 downto 0 ) := ( others = > ' 0 ' ) |
EventWC | std_logic_vector ( 19 downto 0 ) := ( others = > ' 0 ' ) |
EventWCp | std_logic_vector ( 19 downto 0 ) := ( others = > ' 0 ' ) |
EventCnt | std_logic_vector ( 4 downto 0 ) := ( others = > ' 0 ' ) |
WrEventCnt | std_logic_vector ( 4 downto 0 ) := ( others = > ' 0 ' ) |
RdEventCnt | std_logic_vector ( 4 downto 0 ) := ( others = > ' 0 ' ) |
EventStatus | std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' ) |
EventStatus_Di | std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' ) |
EventStatusCnt | std_logic_vector ( 4 downto 0 ) := ( others = > ' 1 ' ) |
EventStatus_wa | std_logic_vector ( 4 downto 0 ) := ( others = > ' 1 ' ) |
EventStatus_ra | std_logic_vector ( 4 downto 0 ) := ( others = > ' 1 ' ) |
idle_cntr | std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' ) |
CntrTimeout | std_logic := ' 0 ' |
cntr_timer | std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' ) |
cntrs | std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' ) |
cntr0 | std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' ) |
cntr1 | std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' ) |
cntr2 | std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' ) |
cntr3 | std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' ) |
cntr4 | std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' ) |
cntr5 | std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' ) |
cntr6 | std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' ) |
cntr7 | std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' ) |
cntr8 | std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' ) |
cntr9 | std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' ) |
cntra | std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' ) |
cntrb | std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' ) |
cntrc | std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' ) |
cntrd | std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' ) |
cntre | std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' ) |
cntrf | std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' ) |
cntr10 | std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' ) |
cntr11 | std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' ) |
cntr12 | std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' ) |
cntr13 | std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' ) |
cntr14 | std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' ) |
cntr15 | std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' ) |
cntr16 | std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' ) |
short_event_cntr | std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' ) |
bad_word_cntr | std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' ) |
input_word_cntr | std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' ) |
input_header_cntr | std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' ) |
input_trailer_cntr | std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' ) |
input_evnErr_cntr | std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' ) |
input_evn | std_logic_vector ( 23 downto 0 ) := ( others = > ' 0 ' ) |
sample_sync | std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' ) |
sample | std_logic := ' 0 ' |
FIFO_ovf | std_logic := ' 0 ' |
RXCHARISK_q | std_logic_vector ( 1 downto 0 ) := ( others = > ' 1 ' ) |
RXCHARISCOMMA_q | std_logic_vector ( 1 downto 0 ) := ( others = > ' 1 ' ) |
RXLOSSOFSYNC_q | std_logic_vector ( 1 downto 0 ) := ( others = > ' 1 ' ) |
RXDATA_q | std_logic_vector ( 15 downto 0 ) := ( others = > ' 1 ' ) |
FIFO_rst | std_logic := ' 0 ' |
DataFIFO_FULL | std_logic := ' 1 ' |
DataFIFO_EMPTY | std_logic := ' 1 ' |
DataFIFO_WRERR | std_logic := ' 0 ' |
DataFIFO_RdEn | std_logic := ' 0 ' |
DataFIFO_RdEnp | std_logic := ' 0 ' |
DataFIFO_WrEn | std_logic := ' 0 ' |
DataFIFO_di | std_logic_vector ( 65 downto 0 ) := ( others = > ' 0 ' ) |
DataFIFO_do | std_logic_vector ( 65 downto 0 ) := ( others = > ' 0 ' ) |
RDCOUNT | std_logic_vector ( 8 downto 0 ) := ( others = > ' 0 ' ) |
WRCOUNT | std_logic_vector ( 8 downto 0 ) := ( others = > ' 0 ' ) |
ChkEvtLen_in | std_logic_vector ( 1 downto 0 ) := ( others = > ' 1 ' ) |
ChkEvtLen | std_logic_vector ( 1 downto 0 ) := ( others = > ' 0 ' ) |
L1A_DATA_o | std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' ) |
L1A_DATA_ra | std_logic_vector ( 4 downto 0 ) := ( others = > ' 0 ' ) |
L1A_DATA_wa | std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' ) |
OldL1Ainfo_wa0_SyncRegs | std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' ) |
ce_L1A_DATA_ra | std_logic := ' 0 ' |
CriticalTTS | std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' ) |
ReSyncAndEmptySync | std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' ) |
ReSyncState | std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' ) |
dl_cntr | std_logic_vector ( u downto 0 ) := ( others = > ' 0 ' ) |
GotBoE | std_logic := ' 0 ' |
GotOrN | std_logic := ' 0 ' |
FakeEvN | std_logic_vector ( 23 downto 0 ) := ( others = > ' 0 ' ) |
Board_ID | std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' ) |
DataFIFO_RdEn_i | std_logic := ' 0 ' |
DataFIFO_EMPTY_i | std_logic := ' 1 ' |
DataFIFO_do_i | std_logic_vector ( 65 downto 0 ) := ( others = > ' 0 ' ) |
rst_input_evn | std_logic := ' 0 ' |
Initwait_cntr | std_logic_vector ( 8 downto 0 ) := ( others = > ' 0 ' ) |
wait_header | std_logic := ' 0 ' |
wait_trailer | std_logic := ' 0 ' |
bad_header | std_logic := ' 0 ' |
bad_trailer | std_logic := ' 0 ' |
bad_data | std_logic := ' 0 ' |
bad_size | std_logic := ' 0 ' |
input_wc | std_logic_vector ( 19 downto 0 ) := ( others = > ' 0 ' ) |
cs_in | std_logic_vector ( 143 downto 0 ) := ( others = > ' 0 ' ) |
Instantiations | |
i_DataFIFO | fifo66X512 <Entity fifo66X512> |
i_EventCRC | EthernetCRCD32 <Entity EthernetCRCD32> |
i_TxCRC | crc16D16 <Entity crc16D16> |
i_RxCRC | crc16D16 <Entity crc16D16> |
Definition at line 81 of file DAQ_Link_V6.vhd.