AMC13
Firmwares for the different applications of the AMC13 uTCA board made at Boston University
All Classes Variables
DAQ_Link_V6.vhd
1 ----------------------------------------------------------------------------------
2 -- Company:
3 -- Engineer:
4 --
5 -- Create Date: 10:25:43 01/28/2012
6 -- Design Name:
7 -- Module Name: miniCTR - Behavioral
8 -- Project Name:
9 -- Target Devices:
10 -- Tool versions:
11 -- Description:
12 --
13 -- Dependencies:
14 --
15 -- Revision:
16 -- Revision 0.01 - File Created
17 -- Additional Comments:
18 --
19 ----------------------------------------------------------------------------------
20 library IEEE;
21 use IEEE.STD_LOGIC_1164.ALL;
22 use IEEE.STD_LOGIC_ARITH.ALL;
23 use IEEE.STD_LOGIC_UNSIGNED.ALL;
24 use IEEE.std_logic_misc.all;
25 
26 -- Uncomment the following library declaration if using
27 -- arithmetic functions with Signed or Unsigned values
28 --use IEEE.NUMERIC_STD.ALL;
29 
30 -- Uncomment the following library declaration if instantiating
31 -- any Xilinx primitives in this code.
32 library UNISIM;
33 use UNISIM.VComponents.all;
34 Library UNIMACRO;
35 use UNIMACRO.vcomponents.all;
36 
37 entity DAQ_Link_V6 is
38  Generic (
39 -- If you do not use the trigger port, set it to false
40 -- USE_TRIGGER_PORT : boolean := true;
41  simulation : boolean := false);
42  Port (
43  reset : in STD_LOGIC; -- asynchronous reset, assert reset until GTX REFCLK stable
44  USE_TRIGGER_PORT : boolean;
45 -- MGT signals
46  UsrClk : in STD_LOGIC; -- it must have a frequency of 250MHz
47  RXPLLLKDET : in STD_LOGIC;
48  RxResetDone : in STD_LOGIC;
49  TxResetDone : in STD_LOGIC;
50  RXCDRRESET : out STD_LOGIC;
51  RXENPCOMMAALIGN : out STD_LOGIC;
52  RXENMCOMMAALIGN : out STD_LOGIC;
53  RXLOSSOFSYNC : in STD_LOGIC_VECTOR (1 downto 0);
54  RXCHARISCOMMA : in STD_LOGIC_VECTOR (1 downto 0);
55  RXCHARISK : in STD_LOGIC_VECTOR (1 downto 0);
56  RXDATA : in STD_LOGIC_VECTOR (15 downto 0);
57  TXCHARISK : out STD_LOGIC_VECTOR (1 downto 0);
58  TXDATA : out STD_LOGIC_VECTOR (15 downto 0);
59 -- TRIGGER port
60  TTCclk : in STD_LOGIC;
61  BcntRes : in STD_LOGIC;
62  trig : in STD_LOGIC_VECTOR (7 downto 0);
63 -- TTS port
64  TTSclk : in STD_LOGIC; -- clock source which clocks TTS signals
65  TTS : in STD_LOGIC_VECTOR (3 downto 0);
66 -- Data port
67  ReSyncAndEmpty : in STD_LOGIC;
68  EventDataClk : in STD_LOGIC;
69  EventData_valid : in STD_LOGIC; -- used as data write enable
70  EventData_header : in STD_LOGIC; -- first data word
71  EventData_trailer : in STD_LOGIC; -- last data word
72  EventData : in STD_LOGIC_VECTOR (63 downto 0);
73  AlmostFull : out STD_LOGIC; -- buffer almost full
74  Ready : out STD_LOGIC;
75  sysclk : in STD_LOGIC;
76  L1A_DATA_we : out STD_LOGIC; -- last data word
77  L1A_DATA : out STD_LOGIC_VECTOR (15 downto 0)
78  );
79 end DAQ_Link_V6;
80 
81 architecture Behavioral of DAQ_Link_V6 is
82 COMPONENT crc16D16
83  PORT(
84  clk : IN std_logic;
85  init_crc : IN std_logic;
86  we_crc : IN std_logic;
87  d : IN std_logic_vector(15 downto 0);
88  crc : OUT std_logic_vector(15 downto 0)
89  );
90 END COMPONENT;
91 COMPONENT EthernetCRCD32
92  PORT(
93  clk : IN std_logic;
94  init : IN std_logic;
95  ce : IN std_logic;
96  d : IN std_logic_vector(31 downto 0);
97  crc : OUT std_logic_vector(31 downto 0);
98  bad_crc : OUT std_logic
99  );
100 END COMPONENT;
101 COMPONENT TTS_TRIG_if
102  Generic (simulation : boolean := false);
103  PORT(
104  reset : IN std_logic;
105  USE_TRIGGER_PORT : boolean;
106  UsrClk : IN std_logic;
107  TTCclk : IN std_logic;
108  BcntRes : IN std_logic;
109  trig : IN std_logic_vector(7 downto 0);
110  TTSclk : IN std_logic;
111  TTS : IN std_logic_vector(3 downto 0);
112  RXCHARISK : IN std_logic_vector(1 downto 0);
113  RXDATA : IN std_logic_vector(15 downto 0);
114  sel_TTS_TRIG : OUT std_logic;
115  TTS_TRIG_data : OUT std_logic_vector(17 downto 0)
116  );
117 END COMPONENT;
118 COMPONENT fifo66X512
119  generic (ALMOST_FULL_OFFSET : STD_LOGIC_VECTOR (15 downto 0) := x"000a";
120  ALMOST_EMPTY_OFFSET : STD_LOGIC_VECTOR (15 downto 0) := x"0004");
121  PORT(
122  wclk : IN std_logic;
123  rclk : IN std_logic;
124  reset : IN std_logic;
125  Di : IN std_logic_vector(65 downto 0);
126  we : IN std_logic;
127  re : IN std_logic;
128  Do : OUT std_logic_vector(65 downto 0);
129  almostfull : OUT std_logic;
130  almostempty : OUT std_logic;
131  full : OUT std_logic;
132  empty : OUT std_logic
133  );
134 END COMPONENT;
135 function boolean_to_int_w(biw : boolean) return integer is
136  begin
137  if(biw) then
138  return 8;
139  else
140  return 16;
141  end if;
142 end function;
143 function boolean_to_int_u(biu : boolean) return integer is
144  begin
145  if(biu) then
146  return 2;
147  else
148  return 7;
149  end if;
150 end function;
151 constant version : std_logic_vector(7 downto 0) := x"14";
152 constant N : integer := 8;
153 constant w : integer := boolean_to_int_w(simulation);
154 constant u : integer := boolean_to_int_u(simulation);
155 constant Acknowledge : std_logic_vector(7 downto 0) := x"12";
156 constant data : std_logic_vector(7 downto 0) := x"34";
157 constant InitRqst : std_logic_vector(7 downto 0) := x"56";
158 constant Counter : std_logic_vector(7 downto 0) := x"78";
159 constant K_word : std_logic_vector(15 downto 0) := x"3cbc"; -- sequence K28.5 K28.1
160 constant R_word : std_logic_vector(15 downto 0) := x"dcfb"; -- sequence K27.7 K28.6
161 constant eof_word : std_logic_vector(15 downto 0) := x"5cf7"; -- sequence K23.7 K28.2
162 constant IDLE : std_logic_vector(3 downto 0) := x"0"; -- TxState
163 constant SendK : std_logic_vector(3 downto 0) := x"1"; -- TxState sending comma
164 constant SendType : std_logic_vector(3 downto 0) := x"2"; -- TxState sending event data words
165 constant SendSEQ : std_logic_vector(3 downto 0) := x"3"; -- TxState sending sequence number
166 constant SendWC : std_logic_vector(3 downto 0) := x"4"; -- TxState sending payload word count
167 constant WaitCRC : std_logic_vector(3 downto 0) := x"5"; -- TxState same as IDLE
168 constant WaitData : std_logic_vector(3 downto 0) := x"6"; -- TxState same as IDLE, used during sending packets
169 constant SendCRC : std_logic_vector(3 downto 0) := x"7"; -- TxState sending CRC
170 constant SendData : std_logic_vector(3 downto 0) := x"8"; -- TxState sending event data words
171 constant SendCntr : std_logic_vector(3 downto 0) := x"9"; -- TxState sending event data words
172 constant SendEOF : std_logic_vector(3 downto 0) := x"a"; -- TxState sending EOF
173 signal TxState: std_logic_vector(3 downto 0) := (others => '0');
174 signal sel_TTS_TRIG : std_logic := '0';
175 signal bcnt_err_cnt : std_logic_vector(3 downto 0) := (others => '0');
176 signal reset_sync : std_logic_vector(3 downto 0) := (others => '0');
177 signal rst_cdr : std_logic := '0';
178 signal rst_wait : std_logic := '0';
179 signal wait_cntr : std_logic_vector(w downto 0) := (others => '0');
180 signal UsrClkDiv : std_logic_vector(1 downto 0) := (others => '0');
181 signal TTS_TRIG_data : std_logic_vector(17 downto 0) := (others => '0');
182 signal ResetFIFO_sync : std_logic_vector(1 downto 0) := (others => '0');
183 signal AlmostFull_i : std_logic := '0';
184 --signal AlmostFull_sync : std_logic_vector(2 downto 0) := (others => '0');
185 signal Init_EventCRC : std_logic := '0';
186 signal ce_EventCRC : std_logic := '0';
187 signal EventCRC_d : std_logic_vector(31 downto 0) := (others => '0');
188 signal EventCRC : std_logic_vector(31 downto 0) := (others => '0');
189 signal BoE : std_logic := '0';
190 signal BoE_q : std_logic := '0';
191 signal EoE : std_logic := '0';
192 signal FillDataBuf : std_logic := '0';
193 signal dataBuf_WrEn : std_logic := '0';
194 signal DataBuf_wa : std_logic_vector(14 downto 0) := (others => '0');
195 signal DataBuf_ra : std_logic_vector(14 downto 0) := (others => '0');
196 signal DataBuf_start : std_logic_vector(14 downto 0) := (others => '0');
197 signal DataBuf_Din : std_logic_vector(16 downto 0) := (others => '0');
198 signal DataBuf_Dout : std_logic_vector(16 downto 0) := (others => '0');
199 signal ec_DataBuf_ra : std_logic := '0';
200 signal ec_DataBuf_ra_q : std_logic := '0';
201 signal DataBuf_full : std_logic := '0';
202 signal DataBuf_used : std_logic_vector(14 downto 0) := (others => '0');
203 signal DataBuf_wc : std_logic_vector(14 downto 0) := (others => '0');
204 signal ReSendQueOut_q : std_logic_vector(14 downto 0) := (others => '0');
205 signal ReSendQue_a : std_logic_vector(1 downto 0) := (others => '1');
206 signal ReSendQue_empty : std_logic := '1';
207 signal we_DataPipe : std_logic := '0';
208 signal DataPipeDo : std_logic_vector(16 downto 0) := (others => '0');
209 signal DataPipe_a : std_logic_vector(3 downto 0) := (others => '1');
210 signal DataPipe_empty : std_logic := '1';
211 signal EventStatus_empty : std_logic := '1';
212 signal DataPipe_full : std_logic := '0';
213 signal InitLink : std_logic := '0';
214 signal InitACK : std_logic := '0';
215 signal ReSend : std_logic := '0';
216 --signal Ready_i : std_logic := '1';
217 signal FoundEOF : std_logic := '0';
218 signal ACK : std_logic := '0';
219 signal CntrACK : std_logic := '0';
220 signal L1Aabort : std_logic := '0';
221 signal timer : std_logic_vector(N downto 0) := (others => '0');
222 signal we_ReSendQue : std_logic := '0';
223 signal we_TxCRC : std_logic := '0';
224 signal Init_TxCRC : std_logic := '0';
225 signal R_word_cnt : std_logic_vector(11 downto 0) := (others => '0');
226 signal TxCRC : std_logic_vector(15 downto 0) := (others => '0');
227 signal R_word_sent : std_logic := '0';
228 signal sel_cntr : std_logic := '0';
229 signal we_TxFIFO : std_logic := '0';
230 signal TxFIFO_empty : std_logic := '1';
231 signal TxFIFO_full : std_logic := '0';
232 signal TxFIFO_a : std_logic_vector(3 downto 0) := (others => '1');
233 signal TxFIFO_Dip : std_logic_vector(15 downto 0) := (others => '0');
234 signal TxFIFO_Di : std_logic_vector(16 downto 0) := (others => '0');
235 signal TxFIFO_Do : std_logic_vector(16 downto 0) := (others => '0');
236 signal packet_wc : std_logic_vector(15 downto 0) := (others => '0');
237 signal ACKNUM_IN : std_logic_vector(7 downto 0) := x"00";
238 signal RxSEQNUM : std_logic_vector(7 downto 0) := x"00";
239 signal SEQNUM : std_logic_vector(7 downto 0) := x"00";
240 signal NextSEQNUM : std_logic_vector(7 downto 0) := x"00";
241 signal ACKNUM : std_logic_vector(7 downto 0) := (others => '0');
242 signal bad_K : std_logic := '0';
243 signal SEQ_OK : std_logic := '0';
244 signal IllegalSeq : std_logic := '0';
245 signal CRC_OK : std_logic := '0';
246 signal frame_OK : std_logic := '0';
247 signal TypeInit : std_logic := '0';
248 signal TypeACK : std_logic := '0';
249 signal TypeData : std_logic := '0';
250 signal TypeCntr : std_logic := '0';
251 signal Receiving : std_logic := '0';
252 signal Header2 : std_logic := '0';
253 signal TxType : std_logic_vector(7 downto 0) := (others => '0');
254 signal AMC_ID : std_logic_vector(7 downto 0) := (others => '0');
255 signal RxType : std_logic_vector(15 downto 0) := (others => '0');
256 signal RxWC : std_logic_vector(2 downto 0) := (others => '0');
257 signal check_packet : std_logic := '0';
258 signal WC_OKp : std_logic := '0';
259 signal WC_OK : std_logic := '0';
260 signal L1Ainfo : std_logic := '0';
261 signal ACK_OK : std_logic := '0';
262 signal we_ACKNUM : std_logic := '0';
263 signal accept : std_logic := '0';
264 signal IsACK : std_logic := '0';
265 signal IsCntr : std_logic := '0';
266 signal IsData : std_logic := '0';
267 signal CntrSent : std_logic := '0';
268 signal ReSendQueIn : std_logic_vector(27 downto 0) := (others => '0');
269 signal ReSendQueOut : std_logic_vector(27 downto 0) := (others => '0');
270 signal ACKNUM_full : std_logic := '0';
271 signal ACKNUM_empty : std_logic := '1';
272 signal AMC_info : std_logic_vector(7 downto 0) := (others => '0');
273 signal ACKNUM_l : std_logic_vector(7 downto 0) := (others => '0');
274 signal ACKNUM_a : std_logic_vector(1 downto 0) := (others => '1');
275 signal we_RxCRC : std_logic := '0';
276 signal Init_RxCRC : std_logic := '0';
277 signal RxCRC : std_logic_vector(15 downto 0) := (others => '0');
278 signal AMCinfo_WrEn : std_logic := '0';
279 signal AMCinfo_wa : std_logic_vector(9 downto 0) := (others => '0');
280 signal AMCinfo_sel : std_logic_vector(2 downto 0) := (others => '0');
281 signal AMCinfo_Di : std_logic_vector(15 downto 0) := (others => '0');
282 signal AMCinfo_Do : std_logic_vector(15 downto 0) := (others => '0');
283 signal evnLSB : std_logic_vector(7 downto 0) := (others => '0');
284 signal bad_ID : std_logic := '0';
285 signal AMC_header : std_logic := '0';
286 signal L1Ainfo_WrEn : std_logic := '0';
287 signal OldL1Ainfo_wa : std_logic_vector(7 downto 0) := (others => '0');
288 signal L1Ainfo_wa : std_logic_vector(9 downto 0) := (others => '0');
289 signal info_ra : std_logic_vector(9 downto 0) := (others => '0');
290 signal L1Ainfo_Di : std_logic_vector(15 downto 0) := (others => '0');
291 signal L1Ainfo_Do : std_logic_vector(15 downto 0) := (others => '0');
292 signal L1Ainfo_empty : std_logic := '1';
293 signal RxL1Ainfo : std_logic := '0';
294 signal AMCinfo_empty : std_logic := '1';
295 signal ce_info_ra : std_logic := '0';
296 signal check_L1Ainfo : std_logic := '0';
297 signal check_L1Ainfo_q : std_logic := '0';
298 signal L1AinfoMM : std_logic := '0';
299 signal info_ra_q : std_logic_vector(1 downto 0) := (others => '0');
300 signal info_ra_q2 : std_logic_vector(1 downto 0) := (others => '0');
301 signal we_EventStatus : std_logic := '0';
302 signal EventData2Send : std_logic := '0';
303 signal UnknownEventLength : std_logic := '1';
304 signal bad_EventLength : std_logic := '1';
305 signal EventLength : std_logic_vector(19 downto 0) := (others => '0');
306 signal EventWC : std_logic_vector(19 downto 0) := (others => '0');
307 signal EventWCp : std_logic_vector(19 downto 0) := (others => '0');
308 signal EventCnt : std_logic_vector(4 downto 0) := (others => '0');
309 signal WrEventCnt : std_logic_vector(4 downto 0) := (others => '0');
310 signal RdEventCnt : std_logic_vector(4 downto 0) := (others => '0');
311 signal EventStatus : std_logic_vector(7 downto 0) := (others => '0');
312 signal EventStatus_Di : std_logic_vector(7 downto 0) := (others => '0');
313 signal EventStatusCnt : std_logic_vector(4 downto 0) := (others => '1');
314 signal EventStatus_wa : std_logic_vector(4 downto 0) := (others => '1');
315 signal EventStatus_ra : std_logic_vector(4 downto 0) := (others => '1');
316 signal idle_cntr : std_logic_vector(3 downto 0) := (others => '0');
317 signal CntrTimeout : std_logic := '0';
318 signal cntr_timer : std_logic_vector(15 downto 0) := (others => '0');
319 signal cntrs : std_logic_vector(15 downto 0) := (others => '0');
320 signal cntr0 : std_logic_vector(15 downto 0) := (others => '0');
321 signal cntr1 : std_logic_vector(15 downto 0) := (others => '0');
322 signal cntr2 : std_logic_vector(15 downto 0) := (others => '0');
323 signal cntr3 : std_logic_vector(15 downto 0) := (others => '0');
324 signal cntr4 : std_logic_vector(15 downto 0) := (others => '0');
325 signal cntr5 : std_logic_vector(15 downto 0) := (others => '0');
326 signal cntr6 : std_logic_vector(15 downto 0) := (others => '0');
327 signal cntr7 : std_logic_vector(15 downto 0) := (others => '0');
328 signal cntr8 : std_logic_vector(15 downto 0) := (others => '0');
329 signal cntr9 : std_logic_vector(15 downto 0) := (others => '0');
330 signal cntra : std_logic_vector(15 downto 0) := (others => '0');
331 signal cntrb : std_logic_vector(15 downto 0) := (others => '0');
332 signal cntrc : std_logic_vector(15 downto 0) := (others => '0');
333 signal cntrd : std_logic_vector(15 downto 0) := (others => '0');
334 signal cntre : std_logic_vector(15 downto 0) := (others => '0');
335 signal cntrf : std_logic_vector(15 downto 0) := (others => '0');
336 signal cntr10 : std_logic_vector(15 downto 0) := (others => '0');
337 signal cntr11 : std_logic_vector(15 downto 0) := (others => '0');
338 signal cntr12 : std_logic_vector(15 downto 0) := (others => '0');
339 signal cntr13 : std_logic_vector(15 downto 0) := (others => '0');
340 signal cntr14 : std_logic_vector(15 downto 0) := (others => '0');
341 signal cntr15 : std_logic_vector(15 downto 0) := (others => '0');
342 signal cntr16 : std_logic_vector(15 downto 0) := (others => '0');
343 signal short_event_cntr : std_logic_vector(15 downto 0) := (others => '0');
344 signal bad_word_cntr : std_logic_vector(15 downto 0) := (others => '0');
345 signal input_word_cntr : std_logic_vector(15 downto 0) := (others => '0');
346 signal input_header_cntr : std_logic_vector(15 downto 0) := (others => '0');
347 signal input_trailer_cntr : std_logic_vector(15 downto 0) := (others => '0');
348 signal input_evnErr_cntr : std_logic_vector(15 downto 0) := (others => '0');
349 signal input_evn : std_logic_vector(23 downto 0) := (others => '0');
350 signal sample_sync : std_logic_vector(3 downto 0) := (others => '0');
351 signal sample : std_logic := '0';
352 signal FIFO_ovf : std_logic := '0';
353 signal RXCHARISK_q : std_logic_vector(1 downto 0) := (others => '1');
354 signal RXCHARISCOMMA_q : std_logic_vector(1 downto 0) := (others => '1');
355 signal RXLOSSOFSYNC_q : std_logic_vector(1 downto 0) := (others => '1');
356 signal RXDATA_q : std_logic_vector(15 downto 0) := (others => '1');
357 signal FIFO_rst : std_logic := '0';
358 signal DataFIFO_FULL : std_logic := '1';
359 signal DataFIFO_EMPTY : std_logic := '1';
360 signal DataFIFO_WRERR : std_logic := '0';
361 signal DataFIFO_RdEn : std_logic := '0';
362 signal DataFIFO_RdEnp : std_logic := '0';
363 signal DataFIFO_WrEn : std_logic := '0';
364 signal DataFIFO_di : std_logic_vector(65 downto 0) := (others => '0');
365 signal DataFIFO_do : std_logic_vector(65 downto 0) := (others => '0');
366 signal RDCOUNT : std_logic_vector(8 downto 0) := (others => '0');
367 signal WRCOUNT : std_logic_vector(8 downto 0) := (others => '0');
368 signal ChkEvtLen_in : std_logic_vector(1 downto 0) := (others => '1');
369 signal ChkEvtLen : std_logic_vector(1 downto 0) := (others => '0');
370 signal L1A_DATA_o : std_logic_vector(15 downto 0) := (others => '0');
371 signal L1A_DATA_ra : std_logic_vector(4 downto 0) := (others => '0');
372 signal L1A_DATA_wa : std_logic_vector(2 downto 0) := (others => '0');
373 signal OldL1Ainfo_wa0_SyncRegs : std_logic_vector(3 downto 0) := (others => '0');
374 signal ce_L1A_DATA_ra : std_logic := '0';
375 signal CriticalTTS : std_logic_vector(2 downto 0) := (others => '0');
376 -- resync logic
377 signal ReSyncAndEmptySync : std_logic_vector(3 downto 0) := (others => '0');
378 signal ReSyncState : std_logic_vector(2 downto 0) := (others => '0');
379 signal dl_cntr : std_logic_vector(u downto 0) := (others => '0');
380 --signal : std_logic_vector(2 downto 0) := (others => '0');
381 signal GotBoE : std_logic := '0';
382 signal GotOrN : std_logic := '0';
383 signal FakeEvN : std_logic_vector(23 downto 0) := (others => '0');
384 signal Board_ID : std_logic_vector(15 downto 0) := (others => '0');
385 signal DataFIFO_RdEn_i : std_logic := '0';
386 signal DataFIFO_EMPTY_i : std_logic := '1';
387 signal DataFIFO_do_i : std_logic_vector(65 downto 0) := (others => '0');
388 signal rst_input_evn : std_logic := '0';
389 signal Initwait_cntr : std_logic_vector(8 downto 0) := (others => '0');
390 signal wait_header : std_logic := '0';
391 signal wait_trailer : std_logic := '0';
392 signal bad_header : std_logic := '0';
393 signal bad_trailer : std_logic := '0';
394 signal bad_data : std_logic := '0';
395 signal bad_size : std_logic := '0';
396 signal input_wc : std_logic_vector(19 downto 0) := (others => '0');
397 -- chipscope
398 COMPONENT cs_delay
399  PORT(
400  clk : IN std_logic;
401  reset : IN std_logic;
402  cs_in : IN std_logic_vector(71 downto 0);
403  cs_out : OUT std_logic_vector(71 downto 0)
404  );
405 END COMPONENT;
406 signal cs_in : std_logic_vector(143 downto 0) := (others => '0');
407 begin
408 process(EventDataClk,FIFO_rst)
409 begin
410  if(FIFO_rst = '1')then
411  wait_header <= '1';
412  wait_trailer <= '0';
413  input_wc <= (others => '0');
414  bad_header <= '0';
415  bad_trailer <= '0';
416  bad_data <= '0';
417  bad_size <= '0';
418  elsif(EventDataClk'event and EventDataClk = '1')then
419  if(EventData_valid = '1')then
420  if(EventData_header = '1')then
421  wait_header <= '0';
422  elsif(EventData_trailer = '1')then
423  wait_header <= '1';
424  end if;
425  if(EventData_trailer = '1')then
426  input_wc <= (others => '0');
427  wait_trailer <= '0';
428  else
429  input_wc <= input_wc + 1;
430  if(input_wc = x"ffffd")then
431  wait_trailer <= '1';
432  end if;
433  end if;
434  if(wait_header = '1')then
435  if(EventData_trailer = '1')then
436  bad_trailer <= '1';
437  elsif(EventData_header = '0')then
438  bad_data <= '1';
439  end if;
440  elsif(EventData_header = '1')then
441  bad_header <= '1';
442  end if;
443  if(wait_trailer = '1' and EventData_trailer = '0')then
444  bad_size <= '1';
445  end if;
446  end if;
447  end if;
448 end process;
449 -- resync logic
450 process(UsrClk)
451 begin
452  if(UsrClk'event and UsrClk = '1')then
453  if(FIFO_rst = '1' or InitLink ='1')then
454  ReSyncAndEmptySync <= (others => '0');
455  else
456  ReSyncAndEmptySync <= ReSyncAndEmptySync(2 downto 0) & ReSyncAndEmpty;
457  end if;
458  if(FIFO_rst = '1' or InitLink = '1')then
459  GotBoE <= '0';
460  GotOrN <= '0';
461  elsif(ReSyncState(2) = '0' and ce_EventCRC = '1')then
462  if(EoE = '1')then
463  GotBoE <= '0';
464  GotOrN <= '0';
465  elsif(BoE = '1')then
466  GotBoE <= '1';
467  elsif(BoE_q = '1')then
468  GotOrN <= '1';
469  end if;
470  elsif(ReSyncState = "111")then
471  GotBoE <= '0';
472  GotOrN <= '0';
473  end if;
474  if(DataFIFO_RdEn = '1')then
475  BOE_q <= BOE;
476  end if;
477  if(FIFO_rst = '1' or InitLink = '1')then
478  ReSyncState <= "000";
479  dl_cntr <= (others => '0');
480  rst_input_evn <= '0';
481  elsif(ReSyncState(2) = '0')then
482  case ReSyncState(1 downto 0) is
483  when "00" =>
484  if(ReSyncAndEmptySync(3 downto 2) = "01")then
485  ReSyncState <= "001";
486  end if;
487  rst_input_evn <= '0';
488  when "01" =>
489  if(and_reduce(dl_cntr) = '1')then
490  ReSyncState <= "010";
491  end if;
492  dl_cntr <= dl_cntr + 1;
493  when "10" =>
494  if(DataFIFO_EMPTY_i = '1' and EventStatusCnt(4 downto 1) = x"0" and (GotOrN = '1' or EventStatusCnt(0) = '0'))then
495  ReSyncState <= "011";
496  end if;
497  when others =>
498  if(and_reduce(dl_cntr) = '1')then
499  if(L1Ainfo_empty = '0' or GotBoE = '1')then
500  ReSyncState <= "100";
501  else
502  ReSyncState <= "000";
503  end if;
504  rst_input_evn <= '1';
505  end if;
506  dl_cntr <= dl_cntr + 1;
507  end case;
508  elsif(UsrClkDiv = "10")then
509  case ReSyncState(1 downto 0) is
510  when "00" =>
511  if((L1Ainfo_empty = '0' or GotBoE = '1') and EventStatusCnt(4) = '0' and DataBuf_used(14) = '0')then
512  if(GotOrN = '1')then
513  ReSyncState <= "111";
514  elsif(GotBoE = '1')then
515  ReSyncState <= "110";
516  else
517  ReSyncState <= "101";
518  end if;
519  end if;
520  when "01" => ReSyncState <= "110";
521  when "10" => ReSyncState <= "111";
522  when others => ReSyncState <= "100";
523  end case;
524  end if;
525  if(ReSyncState = "011")then
526  FakeEvN <= input_evn;
527  elsif(ReSyncState = "111" and UsrClkDiv = "10")then
528  FakeEvN <= FakeEvN + 1;
529  end if;
530  if(FIFO_rst = '1' or InitLink ='1')then
531  DataFIFO_EMPTY <= '1';
532  DataFIFO_RdEn_i <= '0';
533  elsif(ReSyncState(2) = '0')then
534  if(DataFIFO_EMPTY_i = '0')then
535  DataFIFO_EMPTY <= '0';
536  elsif(DataFIFO_RdEn = '1')then
537  DataFIFO_EMPTY <= '1';
538  end if;
539  if(DataFIFO_EMPTY_i = '1')then
540  DataFIFO_RdEn_i <= '0';
541  elsif((DataFIFO_EMPTY = '1' and DataFIFO_RdEn_i = '0') or DataFIFO_RdEn = '1')then
542  DataFIFO_RdEn_i <= '1';
543  else
544  DataFIFO_RdEn_i <= '0';
545  end if;
546  else
547  case ReSyncState(1 downto 0) is
548  when "00" => DataFIFO_EMPTY <= '1';
549  when others => DataFIFO_EMPTY <= '0';
550  end case;
551  DataFIFO_RdEn_i <= '0';
552  end if;
553  if(ReSyncState(2) = '0')then
554  if(DataFIFO_EMPTY = '1' or DataFIFO_RdEn = '1')then
555  DataFIFO_do <= DataFIFO_do_i;
556  end if;
557  else
558  case ReSyncState(1 downto 0) is
559  when "01" => DataFIFO_do <= "10" & x"00" & FakeEvN & x"00000003";
560  when "10" => DataFIFO_do <= "00" & x"000000000000" & Board_ID;
561  when "11" => DataFIFO_do <= "01" & x"00000000" & FakeEvN(7 downto 0) & x"8" & EventWCp;
562  when others => DataFIFO_do <= (others => '0');
563  end case;
564  end if;
565  if(GotOrN = '1')then
566  EventWCp <= EventWC;
567  else
568  EventWCp <= x"00003";
569  end if;
570  end if;
571 end process;
572 -- chipscope
573 --i_cs_delay: cs_delay PORT MAP(
574 -- clk => UsrClk,
575 -- reset => reset,
576 -- cs_in => cs_in(71 downto 0),
577 -- cs_out => open
578 -- );
579 --i_cs_delay2: cs_delay PORT MAP(
580 -- clk => UsrClk,
581 -- reset => reset,
582 -- cs_in => cs_in(143 downto 72),
583 -- cs_out => open
584 -- );
585 cs_in(16 downto 0) <= DataBuf_Din;
586 cs_in(19 downto 18) <= UsrClkDiv;
587 --cs_in(19 downto 18) <= RXCHARISK;
588 cs_in(29 downto 20) <= info_ra;
589 cs_in(39 downto 30) <= l1Ainfo_wa;
590 cs_in(55 downto 40) <= l1Ainfo_di;
591 cs_in(71 downto 56) <= l1Ainfo_do;
592 cs_in(87 downto 72) <= AMCinfo_do;
593 cs_in(90 downto 88) <= EventStatus_Di(2 downto 0);
594 cs_in(92 downto 91) <= info_ra_q2;
595 cs_in(96 downto 93) <= TxState;
596 cs_in(97) <= we_EventStatus;
597 cs_in(98) <= L1AinfoMM;
598 cs_in(99) <= check_L1Ainfo_q;
599 cs_in(100) <= l1Ainfo_wren;
600 cs_in(101) <= L1Ainfo_empty;
601 cs_in(102) <= AMCinfo_empty;
602 cs_in(103) <= AMCinfo_WrEn;
603 cs_in(104) <= filldatabuf;
604 cs_in(105) <= Init_EventCRC;
605 cs_in(106) <= DataFIFO_EMPTY;
606 cs_in(109 downto 107) <= AMCinfo_sel;
607 --cs_in(107) <= frame_OK;
608 --cs_in(108) <= bad_k;
609 --cs_in(109) <= typeinit;
610 --cs_in(110) <= typedata;
611 --cs_in(111) <= accept;
612 --cs_in(112) <= check_packet;
613 --cs_in(113) <= receiving;
614 --cs_in(114) <= sel_tts_trig;
615 --cs_in(115) <= ReSend;
616 cs_in(131 downto 116) <= AMCinfo_di;
617 cs_in(141 downto 132) <= AMCinfo_wa;
618 cs_in(143 downto 142) <= "00";
619 -- start of code
620 --Ready <= Ready_i;
621 Ready <= '1';
622 AlmostFull <= AlmostFull_i;
623 i_DataFIFO: fifo66X512 PORT MAP(
624  wclk => EventDataClk,
625  rclk => UsrClk ,
626  reset => FIFO_rst,
627  Di => DataFIFO_di,
628  we => DataFIFO_WrEn,
629  re => DataFIFO_RdEn_i,
630  Do => DataFIFO_do_i,
631  almostfull => AlmostFull_i,
632  almostempty => open,
633  full => DataFIFO_FULL,
634  empty => DataFIFO_EMPTY_i
635  );
636 DataFIFO_WrEn <= EventData_valid and ((wait_header and EventData_header) or (wait_trailer and EventData_trailer) or (not wait_header and not wait_trailer and not EventData_header));
637 DataFIFO_di <= EventData_header & EventData_trailer & EventData;
638 process(UsrClk)
639 begin
640  if(UsrClk'event and UsrClk = '1')then
641  UsrClkDiv <= UsrClkDiv + 1;
642  if(UsrClkDiv(1) = '0')then
643  EventCRC_d <= DataFIFO_do(31 downto 0);
644  elsif(DataFIFO_do(65) = '1')then
645  EventCRC_d <= x"0" & AMC_ID(3 downto 0) & DataFIFO_do(55 downto 32);
646  else
647  EventCRC_d <= DataFIFO_do(63 downto 32);
648  end if;
649  if(DataFIFO_do(65) = '1' and DataFIFO_RdEnp = '1')then
650  EventLength <= DataFIFO_do(19 downto 0);
651  end if;
652  if(FIFO_rst = '1' or InitLink ='1')then
653  ChkEvtLen <= (others => '0');
654  elsif(DataFIFO_RdEnp = '1')then
655  if(DataFIFO_do(64) = '1' and ChkEvtLen(1) = '1')then
656  ChkEvtLen <= (others => '0');
657  else
658  ChkEvtLen(0) <= not ChkEvtLen(0);
659  ChkEvtLen(1) <= ChkEvtLen(1) or ChkEvtLen(0);
660  end if;
661  end if;
662  if(DataFIFO_RdEnp = '1')then
663  if(DataFIFO_do(65) = '1')then
664  EventWC <= x"00002";
665  else
666  EventWC <= EventWC + 1;
667  end if;
668  end if;
669  UnknownEventLength <= and_reduce(EventLength);
670  if(DataFIFO_RdEnp = '1' and DataFIFO_do(64) = '1' and (EventWC /= DataFIFO_do(19 downto 0) or (UnknownEventLength = '0' and EventLength /= EventWC)))then
671  bad_EventLength <= '1';
672  else
673  bad_EventLength <= '0';
674  end if;
675  Init_EventCRC <= not UsrClkDiv(1) and not UsrClkDiv(0) and DataFIFO_do(65) and not ChkEvtLen(1) and not ChkEvtLen(0) and not DataFIFO_EMPTY;
676  if(FIFO_rst = '1' or InitLink = '1' or DataFIFO_EMPTY = '1')then
677  FillDataBuf <= '0';
678  elsif(UsrClkDiv = "00")then
679  if(DataBuf_full = '1' or EventCnt(4 downto 3) = "11")then
680  FillDataBuf <= '0';
681  else
682  FillDataBuf <= '1';
683  end if;
684  end if;
685  ce_EventCRC <= UsrClkDiv(0) and FillDataBuf;
686  DataFIFO_RdEn <= UsrClkDiv(1) and not UsrClkDiv(0) and FillDataBuf and (ChkEvtLen(1) or not DataFIFO_do(64));
687  DataFIFO_RdEnp <= UsrClkDiv(1) and not UsrClkDiv(0) and FillDataBuf;
688  DataBuf_wrEn <= FillDataBuf;
689  BoE <= DataFIFO_do(65) and not DataFIFO_EMPTY;
690  EoE <= DataFIFO_do(64) and not DataFIFO_EMPTY and ChkEvtLen(1);
691 -- if(BoE = '1' and ce_EventCRC = '1')then
692 -- evnLSB <= EventCRC_d(7 downto 0);
693 -- end if;
694 -- if(EventCRC_d(31 downto 24) = evnLSB)then
695 -- bad_ID <= '0';
696 -- else
697 -- bad_ID <= '1';
698 -- end if;
699  if(DataFIFO_do(65) = '1' and DataFIFO_RdEn = '1')then
700  evnLSB <= DataFIFO_do(39 downto 32);
701  end if;
702  if(DataFIFO_do(64) = '1' and DataFIFO_RdEn = '1' and DataFIFO_do(31 downto 24) /= evnLSB)then
703  bad_ID <= '1';
704  else
705  bad_ID <= '0';
706  end if;
707  if(UsrClkDiv(0) = '1')then
708  if(EoE = '1' and UsrClkDiv(1) = '1')then
709  DataBuf_Din(15 downto 0) <= EventCRC(15 downto 0);
710  else
711  DataBuf_Din(15 downto 0) <= EventCRC_d(15 downto 0);
712  end if;
713  elsif(EoE = '1' and UsrClkDiv(1) = '0')then
714  DataBuf_Din(15 downto 0) <= EventCRC(31 downto 16);
715  else
716  DataBuf_Din(15 downto 0) <= EventCRC_d(31 downto 16);
717  end if;
718  DataBuf_Din(16) <= not UsrClkDiv(1) and not UsrClkDiv(0) and EoE;
719  end if;
720 end process;
721 i_EventCRC: EthernetCRCD32 PORT MAP(
722  clk => UsrClk ,
723  init => Init_EventCRC,
724  ce => ce_EventCRC,
725  d => EventCRC_d,
726  crc => EventCRC,
727  bad_crc => open
728  );
729 process(UsrClk,reset,RxResetDone,TxResetDone,rst_wait,RXPLLLKDET)
730 begin
731  if(reset = '1' or (RxResetDone = '0' and rst_wait = '0') or TxResetDone = '0' or RXPLLLKDET = '0')then
732  reset_sync <= (others => '1');
733  elsif(UsrClk'event and UsrClk = '1')then
734  reset_sync <= reset_sync(2 downto 0) & '0';
735  end if;
736 end process;
737 -- following is used to reset CDR when sync get lost
738 process(UsrClk)
739 begin
740  if(UsrClk'event and UsrClk = '1')then
741  RXCHARISCOMMA_q <= RXCHARISCOMMA;
742  RXCHARISK_q <= RXCHARISK;
743  RXDATA_q <= RXDATA;
744  RXLOSSOFSYNC_q <= RXLOSSOFSYNC;
745  RXENMCOMMAALIGN <= rst_wait;
746  RXENPCOMMAALIGN <= rst_wait;
747  if(wait_cntr(w) = '1')then
748  rst_wait <= '0';
749  elsif(RXLOSSOFSYNC_q(1) = '1')then
750  rst_wait <= '1';
751  end if;
752  rst_cdr <= not rst_wait and RXLOSSOFSYNC_q(1);
753  RXCDRRESET <= rst_cdr;
754  if(wait_cntr(w) = '1' or rst_wait = '0')then
755  wait_cntr <= (others => '0');
756  else
757  wait_cntr <= wait_cntr + 1;
758  end if;
759  end if;
760 end process;
761 process(EventDataClk,reset,InitLink,rst_input_evn)
762 begin
763  if(reset = '1' or rst_input_evn = '1' or FIFO_rst = '1')then
764  input_evn <= x"000001";
765  elsif(EventDataClk'event and EventDataClk = '1')then
766  if(EventData_valid = '1')then
767  if(DataFIFO_di(65) = '1')then
768  input_evn <= DataFIFO_di(55 downto 32);
769  elsif(DataFIFO_di(64) = '1')then
770  input_evn <= input_evn + 1;
771  end if;
772  end if;
773  end if;
774 end process;
775 process(EventDataClk,reset,InitLink)
776 begin
777  if(reset = '1' or FIFO_rst = '1')then
778  ChkEvtLen_in <= (others => '0');
779  sample_sync <= (others => '0');
780  FIFO_ovf <= '0';
781  cntrb <= (others => '0');
782  cntrc <= (others => '0');
783  cntrd <= (others => '0');
784  cntre <= (others => '0');
785  cntrf <= (others => '0');
786  cntr16 <= (others => '0');
787  short_event_cntr <= (others => '0');
788  input_word_cntr <= (others => '0');
789  input_header_cntr <= (others => '0');
790  input_trailer_cntr <= (others => '0');
791  input_evnErr_cntr <= (others => '0');
792  elsif(EventDataClk'event and EventDataClk = '1')then
793  sample_sync <= sample_sync(2 downto 0) & sample;
794  if(EventData_valid = '1' and DataFIFO_FULL = '1')then
795  FIFO_ovf <= '1';
796  end if;
797  if(EventData_valid = '1')then
798  input_word_cntr <= input_word_cntr + 1;
799  if(DataFIFO_di(65) = '1')then
800  input_header_cntr <= input_header_cntr + 1;
801  if(DataFIFO_di(55 downto 32) /= input_evn)then
802  input_evnErr_cntr <= input_evnErr_cntr + 1;
803  end if;
804  end if;
805  if(DataFIFO_di(64) = '1')then
806  ChkEvtLen_in <= (others => '0');
807  else
808  ChkEvtLen_in(0) <= not ChkEvtLen_in(0);
809  ChkEvtLen_in(1) <= ChkEvtLen_in(1) or ChkEvtLen_in(0);
810  end if;
811  if(DataFIFO_di(64) = '1')then
812  input_trailer_cntr <= input_trailer_cntr + 1;
813  if(ChkEvtLen_in(1) = '0')then
814  short_event_cntr <= short_event_cntr + 1;
815  end if;
816  end if;
817  end if;
818  if(sample_sync(3) /= sample_sync(2))then -- update after Counters sent
819  cntr16 <= short_event_cntr;
820  cntrb <= bad_word_cntr;
821  cntrc <= input_word_cntr;
822  cntrd <= input_header_cntr;
823  cntre <= input_trailer_cntr;
824  cntrf <= input_evnErr_cntr;
825  end if;
826  end if;
827 end process;
828 process(UsrClk)
829 begin
830  if(UsrClk'event and UsrClk = '1')then
831  if(FIFO_rst = '1' or InitLink = '1')then
832  DataBuf_wa <= (others => '0');
833  ReSendQueOut_q <= (others => '0');
834  DataBuf_used <= (others => '0');
835  DataBuf_wc <= (others => '0');
836  ec_DataBuf_ra_q <= '0';
837  ec_DataBuf_ra <= '0';
838  DataBuf_full <= '0';
839  we_DataPipe <= '0';
840  DataPipe_a <= (others => '1');
841  DataPipe_empty <= '1';
842  DataPipe_full <= '0';
843  RdEventCnt <= (others => '0');
844  WrEventCnt <= (others => '0');
845  EventData2Send <= '0';
846  EventCnt <= (others => '0');
847  ReSendQue_a <= (others => '1');
848  we_ReSendQue <= '0';
849  ReSendQue_empty <= '1';
850  timer <= (others => '0');
851  DataBuf_start <= (others => '0');
852  DataBuf_ra <= (others => '0');
853  else
854  if(DataBuf_wrEn = '1')then
855  DataBuf_wa <= DataBuf_wa + 1;
856  end if;
857  if(ReSendQue_a /= "11")then
858  ReSendQueOut_q <= ReSendQueOut(14 downto 0);
859  end if;
860  DataBuf_used <= DataBuf_wa - ReSendQueOut_q;
861  DataBuf_wc <= DataBuf_wa - DataBuf_ra;
862  if(or_reduce(DataBuf_wc(14 downto 2)) = '0' and (DataBuf_wc(1 downto 0) = "00" or ec_DataBuf_ra = '1' or ec_DataBuf_ra_q = '1'))then
863  ec_DataBuf_ra <= '0';
864  else
865  ec_DataBuf_ra <= not DataPipe_full and not Resend;
866  end if;
867  ec_DataBuf_ra_q <= ec_DataBuf_ra and not Resend;
868  DataBuf_full <= and_reduce(DataBuf_used(14 downto 3));
869  we_DataPipe <= ec_DataBuf_ra_q and not Resend;
870  if(Resend = '1')then
871  DataPipe_a <= (others => '1');
872  elsif(we_DataPipe = '1' and (TxFIFO_full = '1' or TxState /= SendData))then
873  DataPipe_a <= DataPipe_a + 1;
874  elsif(we_DataPipe = '0' and TxFIFO_full = '0' and TxState = SendData)then
875  DataPipe_a <= DataPipe_a - 1;
876  end if;
877  if(DataPipe_a = x"f" or Resend = '1' or (DataPipe_a = x"0" and TxFIFO_full = '0' and TxState = SendData))then
878  DataPipe_empty <= '1';
879  else
880  DataPipe_empty <= '0';
881  end if;
882  case DataPipe_a is
883  when x"e" | x"d" | x"c" | x"b" | x"a" | x"9" | x"8" => DataPipe_full <= '1';
884  when others => DataPipe_full <= '0';
885  end case;
886  if(DataBuf_Din(16) = '1' and DataBuf_wrEn = '1')then
887  WrEventCnt <= WrEventCnt + 1;
888  end if;
889  if(ReSend = '1')then
890  RdEventCnt <= ReSendQueOut(27 downto 23);
891  elsif(TxState = SendEOF and TxFIFO_full = '0')then
892  RdEventCnt <= RdEventCnt + 1;
893  end if;
894  if(WrEventCnt = RdEventCnt and DataBuf_wc(14 downto 12) = "000")then
895  EventData2Send <= '0';
896  else
897  EventData2Send <= '1';
898  end if;
899  EventCnt <= WrEventCnt - RdEventCnt;
900  if(ReSend = '1')then
901  ReSendQue_a <= (others => '1');
902  elsif(we_ReSendQue = '1' and ACK = '0')then
903  ReSendQue_a <= ReSendQue_a + 1;
904  elsif(we_ReSendQue = '0' and ACK = '1' and ReSendQue_a /= "11")then
905  ReSendQue_a <= ReSendQue_a - 1;
906  end if;
907  if(TxState = SendWC and TxFIFO_full = '0' and IsData = '1' and ReSend = '0')then
908  we_ReSendQue <= '1';
909  else
910  we_ReSendQue <= '0';
911  end if;
912  if(ReSend = '1')then
913  ReSendQue_empty <= '1';
914  elsif(we_ReSendQue = '1')then
915  ReSendQue_empty <= '0';
916  elsif(ACK = '1' and ReSendQue_a = "00")then
917  ReSendQue_empty <= '1';
918  end if;
919  if(timer(N) = '1' or ACK = '1' or ReSendQue_empty = '1')then
920  timer <= (others => '0');
921  else
922  timer <= timer + 1;
923  end if;
924  if(Resend = '1')then
925  DataBuf_start <= ReSendQueOut_q;
926  elsif(we_ReSendQue = '1')then
927  DataBuf_start <= DataBuf_start + packet_wc(14 downto 0);
928  end if;
929  if(ReSend = '1' and ReSendQue_empty = '0')then
930  DataBuf_ra <= ReSendQueOut_q;
931  elsif(ec_DataBuf_ra = '1')then
932  DataBuf_ra <= DataBuf_ra + 1;
933  end if;
934  end if;
935  end if;
936 end process;
937 -- ReSendQueue holds the starting address of the oldest unacknowledged packet
938 g_ReSendQueue : for i in 0 to 27 generate
939  i_ReSendQueue : SRL16E
940  port map (
941  Q => ReSendQueOut(i), -- SRL data output
942  A0 => ReSendQue_a(0), -- Select[0] input
943  A1 => ReSendQue_a(1), -- Select[1] input
944  A2 => '0', -- Select[2] input
945  A3 => '0', -- Select[3] input
946  CE => we_ReSendQue, -- Clock enable input
947  CLK => UsrClk, -- Clock input
948  D => ReSendQueIn(i) -- SRL data input
949  );
950 end generate;
951 ReSendQueIn <= RdEventCnt & SEQNUM & DataBuf_start;
952 ReSend <= timer(N);
953 g_DataBufPipe: for i in 0 to 16 generate
954  i_DataBuf : BRAM_SDP_MACRO
955  generic map (
956  BRAM_SIZE => "36Kb", -- Target BRAM, "18Kb" or "36Kb"
957  DEVICE => "VIRTEX6", -- Target device: "VIRTEX5", "VIRTEX6", "SPARTAN6"
958  WRITE_WIDTH => 1, -- Valid values are 1-72 (37-72 only valid when BRAM_SIZE="36Kb")
959  READ_WIDTH => 1, -- Valid values are 1-72 (37-72 only valid when BRAM_SIZE="36Kb")
960  DO_REG => 1) -- Optional output register (0 or 1)
961  port map (
962  DO => DataBuf_Dout(i downto i), -- Output read data port, width defined by READ_WIDTH parameter
963  DI => DataBuf_Din(i downto i), -- Input write data port, width defined by WRITE_WIDTH parameter
964  RDADDR => DataBuf_ra, -- Input read address, width defined by read port depth
965  RDCLK => UsrClk, -- 1-bit input read clock
966  RDEN => '1', -- 1-bit input read port enable
967  REGCE => '1', -- 1-bit input read output register enable
968  RST => '0', -- 1-bit input reset
969  WE => "1", -- Input write enable, width defined by write port depth
970  WRADDR => DataBuf_wa, -- Input write address, width defined by write port depth
971  WRCLK => UsrClk, -- 1-bit input write clock
972  WREN => DataBuf_WrEn -- 1-bit input write port enable
973  );
974  i_DataPipe : SRL16E
975  port map (
976  Q => DataPipeDo(i), -- SRL data output
977  A0 => DataPipe_a(0), -- Select[0] input
978  A1 => DataPipe_a(1), -- Select[1] input
979  A2 => DataPipe_a(2), -- Select[2] input
980  A3 => DataPipe_a(3), -- Select[3] input
981  CE => we_DataPipe, -- Clock enable input
982  CLK => UsrClk, -- Clock input
983  D => DataBuf_Dout(i) -- SRL data input
984  );
985 end generate;
986 g_TxFIFO : for i in 0 to 16 generate
987  i_TxFIFO : SRL16E
988  port map (
989  Q => TxFIFO_Do(i), -- SRL data output
990  A0 => TxFIFO_a(0), -- Select[0] input
991  A1 => TxFIFO_a(1), -- Select[1] input
992  A2 => TxFIFO_a(2), -- Select[2] input
993  A3 => TxFIFO_a(3), -- Select[3] input
994  CE => we_TxFIFO, -- Clock enable input
995  CLK => UsrClk, -- Clock input
996  D => TxFIFO_Di(i) -- SRL data input
997  );
998 end generate;
999 TxFIFO_Di(15 downto 0) <= cntrs when sel_cntr = '1' else TxFIFO_Dip;
1000 process(UsrClk,EventData_valid)
1001 begin
1002  if(EventData_valid = '1')then
1003  Initwait_cntr <= (others => '0');
1004  elsif(UsrClk'event and UsrClk = '1')then
1005  if(InitLink = '0')then
1006  Initwait_cntr <= (others => '0');
1007  else
1008  Initwait_cntr <= Initwait_cntr + 1;
1009  end if;
1010  end if;
1011 end process;
1012 process(UsrClk)
1013 begin
1014  if(UsrClk'event and UsrClk = '1')then
1015  if(InitLink = '1' or TxFIFO_a = x"f" or (TxFIFO_a = x"0" and sel_TTS_TRIG = '0' and we_TxFIFO = '0' and R_word_cnt(11) = '0'))then
1016  TxFIFO_empty <= '1';
1017  else
1018  TxFIFO_empty <= '0';
1019  end if;
1020  if(TxFIFO_empty = '0' or idle_cntr(3) = '1')then
1021  idle_cntr <= x"0";
1022  else
1023  idle_cntr <= idle_cntr + 1;
1024  end if;
1025  if(TxFIFO_a(3 downto 2) = "10")then
1026  TxFIFO_full <= '1';
1027  else
1028  TxFIFO_full <= '0';
1029  end if;
1030  if(InitLink = '1')then
1031  TxFIFO_a <= x"f";
1032  elsif((sel_TTS_TRIG = '1' or TxFIFO_empty = '1' or R_word_cnt(11) = '1') and we_TxFIFO = '1')then
1033  TxFIFO_a <= TxFIFO_a + 1;
1034  elsif(sel_TTS_TRIG = '0' and we_TxFIFO = '0' and TxFIFO_empty = '0' and R_word_cnt(11) = '0')then
1035  TxFIFO_a <= TxFIFO_a - 1;
1036  end if;
1037  if(sel_TTS_TRIG = '1')then
1038  TXCHARISK <= TTS_TRIG_data(17 downto 16);
1039  TXDATA <= TTS_TRIG_data(15 downto 0);
1040  R_word_sent <= '0';
1041  elsif(R_word_cnt(11) = '1' or TxFIFO_empty = '1')then
1042  TXCHARISK <= "11";
1043  TXDATA <= R_word;
1044  R_word_sent <= '1';
1045  else
1046  TXCHARISK <= TxFIFO_Do(16) & TxFIFO_Do(16);
1047  TXDATA <= TxFIFO_Do(15 downto 0);
1048  R_word_sent <= '0';
1049  end if;
1050  if(reset_sync(3) = '1')then
1051  InitLink <= '0';
1052  else
1053 -- whenever a good initialization packet is received, (re)initializa miniCTR
1054  if(check_packet = '1' and CRC_OK = '1' and TypeInit = '1' and frame_OK = '1' and WC_OK = '1' and bad_K = '0')then
1055  InitLink <= '1';
1056  elsif(Initwait_cntr(8) = '1')then
1057  InitLink <= '0';
1058  end if;
1059  end if;
1060 -- if(reset_sync(3) = '1' or rst_cdr = '1')then
1061 -- Ready <= '0';
1062 -- elsif(InitACK = '1' and TxState = SendCRC and TxType = InitRqst)then
1063 -- Ready <= '1';
1064 -- end if;
1065  if(reset_sync(3) = '1' or rst_cdr = '1' or InitLink = '1')then
1066  FIFO_rst <= '1';
1067  elsif(InitACK = '1' and TxState = SendCRC and TxType = InitRqst)then
1068  FIFO_rst <= '0';
1069  end if;
1070  if(InitLink = '1')then
1071  SEQNUM <= x"00";
1072  elsif(ReSend = '1')then
1073  SEQNUM <= ReSendQueOut(22 downto 15);
1074  elsif(we_ReSendQue = '1')then
1075  SEQNUM <= SEQNUM(6 downto 0) & not(SEQNUM(7) xor SEQNUM(5) xor SEQNUM(4) xor SEQNUM(3));
1076  end if;
1077  if(InitLink = '1')then
1078  InitACK <= '1';
1079  elsif(TxState = SendCRC and TxType = InitRqst)then
1080  InitACK <= '0';
1081  end if;
1082  if(InitACK = '1')then
1083  AMC_info <= version;
1084  else
1085  AMC_info <= EventStatus;
1086  end if;
1087  if((rst_wait = '1' and TxState /= IDLE) or reset_sync(3) = '1' or InitLink = '1' or ReSend = '1')then
1088  TxState <= SendK;
1089  elsif(TxFIFO_full = '0')then
1090  case TxState is
1091  when IDLE => -- send R_word (idle)
1092  if((ReSendQue_a(1) = ReSendQue_a(0) and EventStatus_empty = '0' and EventData2Send = '1' and DataPipe_empty = '0') or ACKNUM_empty = '0' or CntrTimeout = '1')then
1093  TxState <= SendSEQ;
1094  elsif(idle_cntr(3) = '1')then
1095  TxState <= SendK;
1096  end if;
1097  if(InitACK = '1')then
1098  TxType <= InitRqst;
1099  IsData <= '0';
1100  IsCntr <= '0';
1101  IsACK <= '1';
1102  elsif(ACKNUM_empty = '0')then
1103  TxType <= Acknowledge;
1104  IsData <= '0';
1105  IsCntr <= '0';
1106  IsACK <= '1';
1107  elsif(CntrTimeout = '1')then
1108  IsData <= '0';
1109  IsCntr <= '1';
1110  IsACK <= '0';
1111  TxType <= Counter;
1112  else
1113  IsData <= '1';
1114  IsCntr <= '0';
1115  IsACK <= '0';
1116  TxType <= data;
1117  end if;
1118  when SendK => -- send K_word
1119  TxState <= IDLE;
1120  when SendSEQ => -- send packet_seq
1121  FoundEOF <= '0';
1122  TxState <= SendType;
1123  when SendType => -- send data type
1124  if(IsData = '1')then
1125  TxState <= SendData;
1126  elsif(IsCntr = '1')then
1127  TxState <= SendCntr;
1128  else
1129  TxState <= SendWC;
1130  end if;
1131  when SendWC => -- send packet_wc
1132  TxState <= WaitCRC;
1133  when WaitCRC => -- wait for CRC
1134  TxState <= SendCRC;
1135  when SendCntr => -- send counter data
1136  if(packet_wc(4 downto 0) = "11111")then -- 32 counters sent, it has to be multiple of 4, i.e. packet_wc(1 downto 0) must always be "11"
1137  TxState <= SendWC;
1138  end if;
1139  when SendData => -- send payload data
1140  if(and_reduce(packet_wc(10 downto 0)) = '1' or DataPipeDo(16) = '1')then -- 4K bytes limit or eof reached
1141  TxState <= SendWC;
1142  FoundEOF <= DataPipeDo(16);
1143  elsif(DataPipe_a = x"0")then
1144  TxState <= WaitData;
1145  end if;
1146  when WaitData => -- wait for data
1147  if(DataPipe_empty = '0')then
1148  TxState <= SendData;
1149  end if;
1150  when SendCRC => -- send TxCRC
1151  if(FoundEOF = '1')then
1152  TxState <= SendEOF;
1153  else
1154  TxState <= SendK;
1155  end if;
1156  when SendEOF => -- send eof_word
1157  TxState <= SendK;
1158  when others => TxState <= x"0";
1159  end case;
1160  end if;
1161  case TxState is
1162  when SendK => TxFIFO_Dip <= K_word;
1163  when SendData => TxFIFO_Dip <= DataPipeDo(15 downto 0);
1164  when SendSEQ => TxFIFO_Dip <= SEQNUM & TxType;
1165  when SendType => TxFIFO_Dip <= ACKNUM_l & AMC_info;
1166  when SendWC => TxFIFO_Dip <= packet_wc;
1167  when SendCRC => TxFIFO_Dip <= TxCRC;
1168  when SendEOF => TxFIFO_Dip <= eof_word;
1169  when others => TxFIFO_Dip <= (others => '0');
1170  end case;
1171  if(InitLink = '1')then
1172  cntrs <= (others => '0');
1173  elsif(packet_wc(4) = '0')then
1174  case packet_wc(3 downto 0) is
1175  when x"0" => cntrs <= cntr0;
1176  when x"1" => cntrs <= cntr1;
1177  when x"2" => cntrs <= cntr2;
1178  when x"3" => cntrs <= cntr3;
1179  when x"4" => cntrs <= cntr4;
1180  when x"5" => cntrs <= cntr5;
1181  when x"6" => cntrs <= cntr6;
1182  when x"7" => cntrs <= cntr7;
1183  when x"8" => cntrs <= cntr8;
1184  when x"9" => cntrs <= cntr9;
1185  when x"a" => cntrs <= cntra;
1186  when x"b" => cntrs <= cntrb;
1187  when x"c" => cntrs <= cntrc;
1188  when x"d" => cntrs <= cntrd;
1189  when x"e" => cntrs <= cntre;
1190  when others => cntrs <= cntrf;
1191  end case;
1192  else
1193  case packet_wc(3 downto 0) is
1194  when x"0" => cntrs <= FIFO_ovf & "00" & EventStatus_ra & "000" & EventStatus_wa;
1195  when x"1" => cntrs <= '0' & DataBuf_wa;
1196  when x"2" => cntrs <= '0' & DataBuf_ra;
1197  when x"3" => cntrs <= "000000" & L1Ainfo_wa;
1198  when x"4" => cntrs <= "000000" & info_ra;
1199  when x"5" => cntrs <= bad_header & bad_trailer & bad_data & bad_size & "00" & AMCinfo_wa;
1200  when x"6" => cntrs <= x"00" & version;
1201  when x"7" => cntrs <= '0' & EventStatus_empty & EventData2Send & DataPipe_empty & CriticalTTS & EventCnt & ReSendQue_a & AlmostFull_i & dataFIFO_Empty;
1202  when x"8" => cntrs <= cntr10;
1203  when x"9" => cntrs <= cntr11;
1204  when x"a" => cntrs <= cntr12;
1205  when x"b" => cntrs <= cntr13;
1206  when x"c" => cntrs <= cntr14;
1207  when x"d" => cntrs <= cntr15;
1208  when x"f" => cntrs <= cntr16; -- add more counter needs to update line if(packet_wc(4 downto 0) = "11110")then -- 16 counters and 15 status words sent
1209  when others => cntrs <= (others => '0');
1210  end case;
1211  end if;
1212  case TxState is
1213  when SendK | SendEOF | IDLE | WaitData | WaitCRC => TxFIFO_Di(16) <= '1';
1214  when others => TxFIFO_Di(16) <= '0';
1215  end case;
1216  if(InitLink = '1' or TxFIFO_full = '1')then
1217  we_TxFIFO <= '0';
1218  else
1219  case TxState is
1220  when IDLE | WaitData | WaitCRC => we_TxFIFO <= '0';
1221  when others => we_TxFIFO <= '1';
1222  end case;
1223  end if;
1224  if(TxState = SendCntr)then
1225  sel_cntr <= '1';
1226  else
1227  sel_cntr <= '0';
1228  end if;
1229  if(TxState = SendK)then
1230  packet_wc(11 downto 0) <= x"000";
1231  elsif(TxFIFO_full = '0' and (TxState = SendData or TxState = SendCntr))then
1232  packet_wc(11 downto 0) <= packet_wc(11 downto 0) + 1;
1233  end if;
1234  if(TxState = IDLE or TxState = SendK)then
1235  Init_TxCRC <= '1';
1236  else
1237  Init_TxCRC <= '0';
1238  end if;
1239  if(R_word_sent = '1')then
1240  R_word_cnt <= (others => '0');
1241  else
1242  R_word_cnt <= R_word_cnt + 1;
1243  end if;
1244  end if;
1245 end process;
1246 i_TxCRC: crc16D16 PORT MAP(
1247  clk => UsrClk ,
1248  init_crc => Init_TxCRC,
1249  we_crc => we_TxCRC,
1250  d => TxFIFO_Di(15 downto 0),
1251  crc => TxCRC
1252  );
1253 we_TxCRC <= not TxFIFO_Di(16) and we_TxFIFO;
1254 -- received data processing starts here
1255 process(UsrClk)
1256 begin
1257  if(UsrClk'event and UsrClk = '1')then
1258 -- Comma ends a packet and after that, any D-word marks the beginning of a packet
1259  if(RXCHARISCOMMA_q = "11" or (L1Ainfo_wa(1 downto 0) = "11" and L1Ainfo_WrEn = '1'))then
1260  L1Ainfo <= '0';
1261  elsif(RXCHARISK_q = "00" and Header2 = '1' and FIFO_rst = '0' and TypeData = '1')then
1262  L1Ainfo <= '1';
1263  end if;
1264  if(RXCHARISCOMMA_q = "11")then
1265  Receiving <= '0';
1266  elsif(RXCHARISK_q = "00")then
1267  Receiving <= '1';
1268  end if;
1269 -- first word of a packet is the packet sequence number
1270  if(rst_wait = '1')then
1271  bad_K <= '1';
1272  elsif(RXCHARISK_q = "00")then
1273  if(Receiving = '0')then
1274  bad_K <= '0';
1275  RxSEQNUM <= RXDATA_q(15 downto 8);
1276  if(RXDATA_q(7 downto 0) = InitRqst)then
1277  TypeInit <= '1';
1278  else
1279  TypeInit <= '0';
1280  end if;
1281  if(RXDATA_q(7 downto 0) = Acknowledge)then
1282  TypeACK <= '1';
1283  else
1284  TypeACK <= '0';
1285  end if;
1286  if(RXDATA_q(7 downto 0) = data)then
1287  TypeData <= '1';
1288  else
1289  TypeData <= '0';
1290  end if;
1291  if(RXDATA_q(7 downto 0) = Counter)then
1292  TypeCntr <= '1';
1293  else
1294  TypeCntr <= '0';
1295  end if;
1296  Header2 <= '1';
1297  else
1298  Header2 <= '0';
1299  end if;
1300  if(Header2 = '1')then
1301  RxType <= RXDATA_q;
1302  RxWC <= "000";
1303  else
1304  RxWC <= RxWC + 1;
1305  end if;
1306  if(RxWC = RXDATA_q(2 downto 0))then
1307  WC_OKp <= '1';
1308  else
1309  WC_OKp <= '0';
1310  end if;
1311  WC_OK <= WC_OKp;
1312  elsif(RXDATA_q(7 downto 0) = x"5c" and RXCHARISK_q = "01")then
1313 -- acknowledge of TTS data, this will be processed by TTS_TRIG_if
1314  elsif((RXDATA_q /= R_word and RXCHARISCOMMA_q /= "11") or RXCHARISK_q(1) /= RXCHARISK_q(0))then
1315  bad_K <= '1';
1316  end if;
1317  if(Receiving = '0')then
1318  ACKNUM_IN <= RxSEQNUM;
1319  end if;
1320  if(TypeACK = '1' and RXType(15 downto 8) = ReSendQueOut(22 downto 15) and ReSendQue_empty = '0')then -- incoming acknowledge number is what waited for
1321  ACK_OK <= '1';
1322  else
1323  ACK_OK <= '0';
1324  end if;
1325  if(InitLink = '1')then
1326  AMC_ID <= RxType(7 downto 0);
1327  end if;
1328  if((RxSEQNUM = NextSEQNUM and TypeInit = '0') or (RxSEQNUM = x"00" and TypeInit = '1'))then -- incoming sequence number is what waited for
1329  SEQ_OK <= '1';
1330  else
1331  SEQ_OK <= '0';
1332  end if;
1333  if(WC_OK = '1' and (TypeInit = '1' or TypeCntr = '1' or TypeData = '1' or TypeACK = '1'))then
1334  frame_OK <= '1';
1335  else
1336  frame_OK <= '0';
1337  end if;
1338  if(or_reduce(RxCRC) = '0')then
1339  CRC_OK <= '1';
1340  else
1341  CRC_OK <= '0';
1342  end if;
1343  if(RXCHARISCOMMA_q = "11" and Receiving = '1')then
1344  check_packet <= '1';
1345  else
1346  check_packet <= '0';
1347  end if;
1348  accept <= check_packet and SEQ_OK and CRC_OK and frame_OK and not bad_K and not ACKNUM_full and (TypeInit or TypeData);
1349 -- acknowledge even received packet is not the expected one
1350  we_ACKNUM <= check_packet and CRC_OK and frame_OK and not bad_K and not ACKNUM_full and (TypeInit or TypeData);
1351  ACK <= check_packet and SEQ_OK and ACK_OK and CRC_OK and frame_OK and not bad_K;
1352  CntrACK <= check_packet and TypeCntr and CRC_OK and frame_OK and not bad_K;
1353  L1Aabort <= check_packet and TypeData and not(SEQ_OK and CRC_OK and frame_OK and not bad_K and not ACKNUM_full);
1354  if(reset_sync(3) = '1')then
1355  ACKNUM_a <= (others => '1');
1356  elsif(InitLink = '1')then
1357  ACKNUM_a <= (others => '0');
1358  elsif(we_ACKNUM = '1' and (TxFIFO_full = '1' or TxState /= SendCRC or IsACK = '0'))then
1359  ACKNUM_a <= ACKNUM_a + 1;
1360  elsif(we_ACKNUM = '0' and TxFIFO_full = '0' and TxState = SendCRC and IsACK = '1')then
1361  ACKNUM_a <= ACKNUM_a - 1;
1362  end if;
1363  if(InitLink = '1')then
1364  NextSEQNUM <= x"01";
1365  elsif(accept = '1')then
1366  NextSEQNUM <= NextSEQNUM(6 downto 0) & not(NextSEQNUM(7) xor NextSEQNUM(5) xor NextSEQNUM(4) xor NextSEQNUM(3));
1367  end if;
1368  if(ACKNUM_a = "11")then
1369  ACKNUM_empty <= '1';
1370  else
1371  ACKNUM_empty <= '0';
1372  end if;
1373  if(ACKNUM_a = "10")then
1374  ACKNUM_full <= '1';
1375  else
1376  ACKNUM_full <= '0';
1377  end if;
1378  if(ACKNUM_a /= "11")then
1379  ACKNUM_l <= ACKNUM;
1380  end if;
1381  if(InitLink = '1')then
1382  cntr0 <= (others => '0');
1383  elsif(accept = '1')then
1384  cntr0 <= cntr0 + 1;
1385  end if;
1386  if(InitLink = '1')then
1387  cntr1 <= (others => '0');
1388  elsif(ACK = '1')then
1389  cntr1 <= cntr1 + 1;
1390  end if;
1391  if(InitLink = '1')then
1392  cntr2 <= (others => '0');
1393  cntr10 <= (others => '0');
1394  cntr11 <= (others => '0');
1395  cntr12 <= (others => '0');
1396  cntr13 <= (others => '0');
1397  cntr14 <= (others => '0');
1398  elsif(L1Aabort = '1')then
1399  cntr2 <= cntr2 + 1;
1400  if(SEQ_OK = '0')then
1401  cntr10 <= cntr10 + 1;
1402  end if;
1403  if(CRC_OK = '0')then
1404  cntr11 <= cntr11 + 1;
1405  end if;
1406  if(frame_OK = '0')then
1407  cntr12 <= cntr12 + 1;
1408  end if;
1409  if(bad_K = '1')then
1410  cntr13 <= cntr13 + 1;
1411  end if;
1412  if(ACKNUM_full = '1')then
1413  cntr14 <= cntr14 + 1;
1414  end if;
1415  end if;
1416  if(InitLink = '1')then
1417  cntr15 <= (others => '0');
1418  elsif(DataFIFO_RdEnp = '1' and DataFIFO_do(64) = '1' and ChkEvtLen(1) = '0')then
1419  cntr15 <= cntr15 + 1;
1420  end if;
1421  if(InitLink = '1')then
1422  cntr3 <= (others => '0');
1423  cntr4 <= (others => '0');
1424  cntr5 <= (others => '0');
1425  cntr6 <= (others => '0');
1426  elsif(we_EventStatus = '1')then
1427  if(EventStatus_Di(0) = '0')then
1428  cntr3 <= cntr3 + 1;
1429  end if;
1430  if(EventStatus_Di(1) = '0')then
1431  cntr4 <= cntr4 + 1;
1432  end if;
1433  if(EventStatus_Di(2) = '0')then
1434  cntr5 <= cntr5 + 1;
1435  end if;
1436  cntr6 <= cntr6 + 1;
1437  end if;
1438  if(InitLink = '1')then
1439  cntr7 <= (others => '0');
1440  elsif(CntrACK = '1')then
1441  cntr7 <= cntr7 + 1;
1442  end if;
1443  if(InitLink = '1')then
1444  cntr8 <= (others => '0');
1445  elsif(ReSend = '1')then
1446  cntr8 <= cntr8 + 1;
1447  end if;
1448  if(InitLink = '1')then
1449  cntr9 <= (others => '0');
1450  elsif(bad_EventLength = '1')then
1451  cntr9 <= cntr9 + 1;
1452  end if;
1453  if(InitLink = '1')then
1454  cntra <= (others => '0');
1455 -- elsif(EoE = '1' and UsrClkDiv = "11" and bad_ID = '1')then
1456  elsif(bad_ID = '1')then
1457  cntra <= cntra + 1;
1458  end if;
1459 -- AlmostFull_sync <= AlmostFull_sync(1 downto 0) & AlmostFull_i;
1460 -- if(InitLink = '1')then
1461 -- cntrb <= (others => '0');
1462 -- elsif(AlmostFull_sync(2) = '1')then
1463 -- cntrb <= cntrb + 1;
1464 -- end if;
1465  if(FIFO_rst = '1' or CntrACK = '1')then
1466  CntrSent <= '0';
1467  elsif(TxState = SendCRC and IsCntr = '1')then
1468  CntrSent <= '1';
1469  end if;
1470  if(FIFO_rst = '1' or CntrACK = '1' or (TxState = SendCRC and IsCntr = '1'))then
1471  cntr_timer <= (others => '0');
1472  elsif(CntrTimeout = '0')then
1473  cntr_timer <= cntr_timer + 1;
1474  end if;
1475  if(CntrSent = '1')then
1476  CntrTimeout <= cntr_timer(8);
1477  elsif(simulation)then
1478  CntrTimeout <= cntr_timer(8);
1479  else
1480  CntrTimeout <= cntr_timer(15);
1481  end if;
1482  if(TxState = SendCRC and IsCntr = '1')then
1483  sample <= not sample;
1484  end if;
1485  end if;
1486 end process;
1487 i_RxCRC: crc16D16 PORT MAP(
1488  clk => UsrClk ,
1489  init_crc => Init_RxCRC,
1490  we_crc => we_RxCRC,
1491  d => RXDATA_q,
1492  crc => RxCRC
1493  );
1494 we_RxCRC <= '1' when RXCHARISK_q = "00" else '0';
1495 Init_RxCRC <= '1' when RXCHARISCOMMA_q = "11" else '0';
1496 g_ACKNUM : for i in 0 to 7 generate
1497  i_ACKNUM : SRL16E
1498  port map (
1499  Q => ACKNUM(i), -- SRL data output
1500  A0 => ACKNUM_a(0), -- Select[0] input
1501  A1 => ACKNUM_a(1), -- Select[1] input
1502  A2 => '0', -- Select[2] input
1503  A3 => '0', -- Select[3] input
1504  CE => we_ACKNUM, -- Clock enable input
1505  CLK => UsrClk, -- Clock input
1506  D => ACKNUM_IN(i) -- SRL data input
1507  );
1508 end generate;
1509 process(UsrClk)
1510 begin
1511  if(UsrClk'event and UsrClk = '1')then
1512  if(Init_EventCRC = '1')then
1513  AMCinfo_sel <= "010";
1514  elsif(FillDataBuf = '1')then
1515  case AMCinfo_sel is
1516  when "010" => AMCinfo_sel <= "100";
1517  when "100" => AMCinfo_sel <= "101";
1518  when "101" => AMCinfo_sel <= "110";
1519  when "110" => AMCinfo_sel <= "011";
1520  when "011" => AMCinfo_sel <= "111";
1521  when others => AMCinfo_sel <= "000";
1522  end case;
1523  end if;
1524  AMCinfo_WrEn <= DataBuf_WrEn and AMCinfo_sel(2);
1525  case AMCinfo_sel(1 downto 0) is
1526  when "00" => AMCinfo_Di <= DataBuf_Din(15 downto 4) & x"0";-- BX
1527  when "01" => AMCinfo_Di <= DataBuf_Din(15 downto 0);--evn(15 downto 0)
1528  when "10" => AMCinfo_Di <= x"00" & DataBuf_Din(7 downto 0);--evn(23 downto 16)
1529  when others => AMCinfo_Di <= DataBuf_Din(15 downto 0);--OrN(15 downto 0)
1530  end case;
1531  if(InitLink = '1')then
1532  AMCinfo_wa <= (others => '0');
1533  elsif(AMCinfo_WrEn = '1')then
1534  AMCinfo_wa <= AMCinfo_wa + 1;
1535  end if;
1536  if(ReSyncState(2) = '0' and AMCinfo_sel = "111")then
1537  Board_ID <= AMCinfo_Di;
1538  end if;
1539  end if;
1540 end process;
1541 i_AMCinfo : BRAM_SDP_MACRO
1542  generic map (
1543  BRAM_SIZE => "18Kb", -- Target BRAM, "18Kb" or "36Kb"
1544  DEVICE => "VIRTEX6", -- Target device: "VIRTEX5", "VIRTEX6", "SPARTAN6"
1545  WRITE_WIDTH => 16, -- Valid values are 1-72 (37-72 only valid when BRAM_SIZE="36Kb")
1546  READ_WIDTH => 16) -- Valid values are 1-72 (37-72 only valid when BRAM_SIZE="36Kb")
1547  port map (
1548  DO => AMCinfo_Do, -- Output read data port, width defined by READ_WIDTH parameter
1549  DI => AMCinfo_Di, -- Input write data port, width defined by WRITE_WIDTH parameter
1550  RDADDR => info_ra, -- Input read address, width defined by read port depth
1551  RDCLK => UsrClk, -- 1-bit input read clock
1552  RDEN => '1', -- 1-bit input read port enable
1553  REGCE => '1', -- 1-bit input read output register enable
1554  RST => '0', -- 1-bit input reset
1555  WE => "11", -- Input write enable, width defined by write port depth
1556  WRADDR => AMCinfo_wa, -- Input write address, width defined by write port depth
1557  WRCLK => UsrClk, -- 1-bit input write clock
1558  WREN => AMCinfo_WrEn -- 1-bit input write port enable
1559  );
1560 process(UsrClk)
1561 begin
1562  if(UsrClk'event and UsrClk = '1')then
1563  L1Ainfo_Di <= RXDATA_q;
1564  if(InitLink = '1')then
1565  OldL1Ainfo_wa <= (others => '0');
1566  elsif(accept = '1')then
1567  OldL1Ainfo_wa <= L1Ainfo_wa(9 downto 2);
1568  end if;
1569  if(InitLink = '1')then
1570  L1Ainfo_wa <= (others => '0');
1571  elsif(L1Aabort = '1')then
1572  L1Ainfo_wa(9 downto 2) <= OldL1Ainfo_wa;
1573  elsif(Receiving = '0')then
1574  L1Ainfo_wa(1 downto 0) <= "00";
1575  elsif(L1Ainfo_WrEn = '1')then
1576  L1Ainfo_wa <= L1Ainfo_wa + 1;
1577  end if;
1578  if(L1Ainfo = '1' and RXCHARISK_q = "00" and (L1Ainfo_wa(1 downto 0) /= "11" or L1Ainfo_WrEn = '0'))then
1579  L1Ainfo_WrEn <= '1';
1580  else
1581  L1Ainfo_WrEn <= '0';
1582  end if;
1583  end if;
1584 end process;
1585 i_L1Ainfo : BRAM_SDP_MACRO
1586  generic map (
1587  BRAM_SIZE => "18Kb", -- Target BRAM, "18Kb" or "36Kb"
1588  DEVICE => "VIRTEX6", -- Target device: "VIRTEX5", "VIRTEX6", "SPARTAN6"
1589  WRITE_WIDTH => 16, -- Valid values are 1-72 (37-72 only valid when BRAM_SIZE="36Kb")
1590  READ_WIDTH => 16) -- Valid values are 1-72 (37-72 only valid when BRAM_SIZE="36Kb")
1591  port map (
1592  DO => L1Ainfo_Do, -- Output read data port, width defined by READ_WIDTH parameter
1593  DI => L1Ainfo_Di, -- Input write data port, width defined by WRITE_WIDTH parameter
1594  RDADDR => info_ra, -- Input read address, width defined by read port depth
1595  RDCLK => UsrClk, -- 1-bit input read clock
1596  RDEN => '1', -- 1-bit input read port enable
1597  REGCE => '1', -- 1-bit input read output register enable
1598  RST => '0', -- 1-bit input reset
1599  WE => "11", -- Input write enable, width defined by write port depth
1600  WRADDR => L1Ainfo_wa, -- Input write address, width defined by write port depth
1601  WRCLK => UsrClk, -- 1-bit input write clock
1602  WREN => L1Ainfo_WrEn -- 1-bit input write port enable
1603  );
1604 process(TTSclk)
1605 begin
1606  if(TTSclk'event and TTSclk = '1')then
1607  if(InitLink = '1')then
1608  CriticalTTS <= "000";
1609  else
1610  if(TTS = x"0" or TTS = x"f")then
1611  CriticalTTS(2) <= '1';
1612  end if;
1613  if(TTS = x"c")then
1614  CriticalTTS(1) <= '1';
1615  end if;
1616  if(TTS = x"2")then
1617  CriticalTTS(0) <= '1';
1618  end if;
1619  end if;
1620  end if;
1621 end process;
1622 i_TTS_TRIG_if: TTS_TRIG_if generic map(simulation => simulation)
1623  PORT MAP(
1624  reset => reset,
1625  USE_TRIGGER_PORT => USE_TRIGGER_PORT,
1626  UsrClk => UsrClk,
1627  TTCclk => TTCclk,
1628  BcntRes => BcntRes,
1629  trig => trig,
1630  TTSclk => TTSclk,
1631  TTS => TTS,
1632  RXCHARISK => RXCHARISK,
1633  RXDATA => RXDATA,
1634  sel_TTS_TRIG => sel_TTS_TRIG,
1635  TTS_TRIG_data => TTS_TRIG_data
1636  );
1637 process(UsrClk)
1638 begin
1639  if(UsrClk'event and UsrClk = '1')then
1640  if(info_ra(9 downto 2) = OldL1Ainfo_wa or check_L1Ainfo = '1')then
1641  L1Ainfo_empty <= '1';
1642  elsif(RxL1Ainfo = '0')then
1643  L1Ainfo_empty <= '0';
1644  end if;
1645  if(Header2 = '1' and TypeData = '1')then
1646  RxL1Ainfo <= '1';
1647  elsif(accept = '1' or L1Aabort = '1')then
1648  RxL1Ainfo <= '0';
1649  end if;
1650  if(info_ra(9 downto 2) = AMCinfo_wa(9 downto 2) or check_L1Ainfo = '1')then
1651  AMCinfo_empty <= '1';
1652  else
1653  AMCinfo_empty <= '0';
1654  end if;
1655  if(info_ra(1 downto 0) = "11")then
1656  ce_info_ra <= '0';
1657  elsif(EventStatusCnt(4 downto 3) /= "11" and L1Ainfo_empty = '0' and AMCinfo_empty = '0')then
1658  ce_info_ra <= '1';
1659  end if;
1660  if(InitLink = '1')then
1661  info_ra <= (others => '0');
1662  elsif(ce_info_ra = '1')then
1663  info_ra <= info_ra + 1;
1664  end if;
1665  check_L1Ainfo <= ce_info_ra;
1666  check_L1Ainfo_q <= check_L1Ainfo;
1667  if(L1Ainfo_Do = AMCinfo_Do(15 downto 0))then
1668  L1AinfoMM <= '0';
1669  else
1670  L1AinfoMM <= '1';
1671  end if;
1672  we_EventStatus <= check_L1Ainfo_q and not check_L1Ainfo;
1673  info_ra_q <= info_ra(1 downto 0);
1674  info_ra_q2 <= info_ra_q;
1675  if(check_L1Ainfo_q = '0')then
1676  EventStatus_Di(2 downto 0) <= "111";
1677  elsif(L1AinfoMM = '1')then
1678  case info_ra_q2 is
1679  when "00" => EventStatus_Di(2) <= '0'; -- BcN mismatch
1680  when "11" => EventStatus_Di(1) <= '0'; -- OrN mismatch
1681  when others => EventStatus_Di(0) <= '0'; -- EvN mismatch
1682  end case;
1683  end if;
1684  EventStatusCnt <= EventStatus_wa - EventStatus_ra;
1685  if(EventStatus_wa = EventStatus_ra)then
1686  EventStatus_empty <= '1';
1687  else
1688  EventStatus_empty <= '0';
1689  end if;
1690  if(FIFO_rst = '1' or InitLink = '1')then
1691  EventStatus_wa <= (others => '0');
1692  elsif(we_EventStatus = '1')then
1693  EventStatus_wa <= EventStatus_wa + 1;
1694  end if;
1695  end if;
1696 end process;
1697 g_EventStatus : for i in 0 to 2 generate
1698  i_EventStatus : RAM32X1D
1699  port map (
1700  DPO => EventStatus(i), -- Read-only 1-bit data output
1701  SPO => open, -- R/W 1-bit data output
1702  A0 => EventStatus_wa (0), -- R/W address[0] input bit
1703  A1 => EventStatus_wa (1), -- R/W address[1] input bit
1704  A2 => EventStatus_wa (2), -- R/W address[2] input bit
1705  A3 => EventStatus_wa (3), -- R/W address[3] input bit
1706  A4 => EventStatus_wa (4), -- R/W address[4] input bit
1707  D => EventStatus_Di (i), -- Write 1-bit data input
1708  DPRA0 => EventStatus_ra (0), -- Read-only address[0] input bit
1709  DPRA1 => EventStatus_ra (1), -- Read-only address[1] input bit
1710  DPRA2 => EventStatus_ra (2), -- Read-only address[2] input bit
1711  DPRA3 => EventStatus_ra (3), -- Read-only address[3] input bit
1712  DPRA4 => EventStatus_ra (4), -- Read-only address[4] input bit
1713  WCLK => UsrClk, -- Write clock input
1714  WE => we_EventStatus -- Write enable input
1715  );
1716 end generate;
1717 EventStatus(3) <= ReSyncState(2);
1718 EventStatus(7 downto 4) <= (others => '0');
1719 EventStatus_ra <= RdEventCnt;
1720 g_L1A_DATA: for i in 0 to 15 generate
1721  i_L1Adata : RAM32X1D
1722  port map (
1723  DPO => L1A_DATA_o(i), -- Read-only 1-bit data output
1724  SPO => open, -- R/W 1-bit data output
1725  A0 => L1Ainfo_wa(0), -- R/W address[0] input bit
1726  A1 => L1Ainfo_wa(1), -- R/W address[1] input bit
1727  A2 => L1Ainfo_wa(2), -- R/W address[2] input bit
1728  A3 => L1Ainfo_wa(3), -- R/W address[3] input bit
1729  A4 => L1Ainfo_wa(4), -- R/W address[4] input bit
1730  D => L1Ainfo_Di(i), -- Write 1-bit data input
1731  DPRA0 => L1A_DATA_ra(0), -- Read-only address[0] input bit
1732  DPRA1 => L1A_DATA_ra(1), -- Read-only address[1] input bit
1733  DPRA2 => L1A_DATA_ra(2), -- Read-only address[2] input bit
1734  DPRA3 => L1A_DATA_ra(3), -- Read-only address[3] input bit
1735  DPRA4 => L1A_DATA_ra(4), -- Read-only address[4] input bit
1736  WCLK => UsrClk, -- Write clock input
1737  WE => L1Ainfo_WrEn -- Write enable input
1738  );
1739 end generate;
1740 process(sysclk, InitLink)
1741 begin
1742  if(InitLink = '1')then
1743  L1A_DATA_ra <= (others => '0');
1744  L1A_DATA_wa <= (others => '0');
1745  OldL1Ainfo_wa0_SyncRegs <= (others => '0');
1746  L1A_DATA_we <= '0';
1747  L1A_DATA <= (others => '0');
1748  elsif(sysclk'event and sysclk = '1')then
1749  OldL1Ainfo_wa0_SyncRegs <= OldL1Ainfo_wa0_SyncRegs(2 downto 0) & OldL1Ainfo_wa(0);
1750  if(OldL1Ainfo_wa0_SyncRegs(3) /= OldL1Ainfo_wa0_SyncRegs(2))then
1751  L1A_DATA_wa <= L1A_DATA_wa + 1;
1752  end if;
1753  if(L1A_DATA_ra(1 downto 0) = "11")then
1754  ce_L1A_DATA_ra <= '0';
1755  elsif(L1A_DATA_wa /= L1A_DATA_ra(4 downto 2))then
1756  ce_L1A_DATA_ra <= '1';
1757  end if;
1758  if(ce_L1A_DATA_ra = '1')then
1759  L1A_DATA_ra <= L1A_DATA_ra + 1;
1760  end if;
1761  L1A_DATA_we <= ce_L1A_DATA_ra;
1762  L1A_DATA <= L1A_DATA_o;
1763  end if;
1764 end process;
1765 end Behavioral;