Behavioral Architecture Reference

List of all members.

Functions
string	GTXRESET_SPEEDUP ( is_sim: in boolean )

Processes
PROCESS_0	( TTCclk )
PROCESS_1	( fake_clk ,reset ,ready )
PROCESS_2	( EventDataClk ,reset ,Ready )
PROCESS_3	( sysclk ,reset )
PROCESS_4	( sysclk )
PROCESS_5	( fake_clk ,reset )
PROCESS_6	( fake_lengthA ,fake_lengthB )
PROCESS_7	( UsrClk ,RxResetDone )
PROCESS_8	( UsrClk ,reset ,RxResetDone ,txfsmresetdone ,cplllock )
PROCESS_9	( UsrClk )

Components
DAQ_Link_7S	<Entity DAQ_Link_7S>
DAQLINK_7S_init	<Entity DAQLINK_7S_init>
fake_event	<Entity fake_event>
FIFO_RESET_7S	<Entity FIFO_RESET_7S>

Signals
UsrClk	std_logic := ' 0 '
cplllock	std_logic := ' 0 '
TXOUTCLK	std_logic := ' 0 '
RxResetDone	std_logic := ' 0 '
txfsmresetdone	std_logic := ' 0 '
LoopBack	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
K_Cntr	std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
reset_SyncRegs	std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
RxResetDoneSyncRegs	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
DATA_VALID	std_logic := ' 0 '
RXNOTINTABLE	std_logic_vector ( 1 downto 0 ) := ( others = > ' 0 ' )
RXCHARISCOMMA	std_logic_vector ( 1 downto 0 ) := ( others = > ' 0 ' )
RXCHARISK	std_logic_vector ( 1 downto 0 ) := ( others = > ' 0 ' )
RXDATA	std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
TXDIFFCTRL	std_logic_vector ( 3 downto 0 ) := x " b "
TXCHARISK	std_logic_vector ( 1 downto 0 ) := ( others = > ' 0 ' )
TXDATA	std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
EventData_valid	std_logic := ' 0 '
EventData_header	std_logic := ' 0 '
EventData_trailer	std_logic := ' 0 '
EventData	std_logic_vector ( 63 downto 0 ) := ( others = > ' 0 ' )
EventDatap	std_logic_vector ( 63 downto 0 ) := ( others = > ' 0 ' )
AlmostFull	std_logic
fakereset	std_logic
Ready	std_logic
AMC_REFCLK	std_logic := ' 0 '
toggle	std_logic := ' 0 '
toggle_r	std_logic_vector ( 4 downto 0 ) := ( others = > ' 0 ' )
fake_header	std_logic
fake_header_q	std_logic
fake_CRC	std_logic
fake_length	std_logic_vector ( 17 downto 0 )
fake_DATA	std_logic_vector ( 15 downto 0 )
fake_WrEn	std_logic
sync	std_logic := ' 1 '
LinkFull	std_logic := ' 0 '
L1A_DATA	std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
L1A_DATAp	std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
L1A_DATA_wa	std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
L1A_DATA_we	std_logic := ' 0 '
L1A_WrEn	std_logic := ' 0 '
ec_byte_cnt	std_logic := ' 0 '
byte_cnt	std_logic_vector ( 1 downto 0 ) := ( others = > ' 0 ' )
ld_data	std_logic := ' 1 '
fake_CRC_q	std_logic_vector ( 1 downto 0 ) := ( others = > ' 0 ' )
fifo_rst	std_logic := ' 0 '
fifo_en	std_logic := ' 0 '
BcntRes	std_logic := ' 0 '
trig	std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
bcnt	std_logic_vector ( 11 downto 0 ) := ( others = > ' 0 ' )
ec_FIFO_RA	std_logic := ' 0 '
FIFO_DI	std_logic_vector ( 17 downto 0 ) := ( others = > ' 0 ' )
FIFO_DO	std_logic_vector ( 71 downto 0 ) := ( others = > ' 0 ' )
FIFO_WA	std_logic_vector ( 10 downto 0 ) := ( others = > ' 0 ' )
FIFO_RA	std_logic_vector ( 8 downto 0 ) := ( others = > ' 0 ' )
FIFO_WC	std_logic_vector ( 8 downto 0 ) := ( others = > ' 0 ' )
A	std_logic_vector ( 29 downto 0 ) := ( others = > ' 0 ' )
C	std_logic_vector ( 47 downto 0 ) := ( others = > ' 0 ' )
D	std_logic_vector ( 24 downto 0 ) := ( others = > ' 0 ' )
P	std_logic_vector ( 47 downto 0 ) := ( others = > ' 0 ' )
lfsr	std_logic_vector ( 17 downto 0 ) := ( others = > ' 0 ' )

Instantiations
i_DAQ_Link_7S	DAQ_Link_7S <Entity DAQ_Link_7S>
i_fake_event	fake_event <Entity fake_event>
i_FIFO_RESET_7S	FIFO_RESET_7S <Entity FIFO_RESET_7S>
i_DAQLINK_7S_init	DAQLINK_7S_init <Entity DAQLINK_7S_init>

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Detailed Description

Definition at line 76 of file DAQ_LINK.vhd.

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The documentation for this class was generated from the following files:

• src/AMC_DAQ_LINK/DAQ_LINK.vhd